dt-bindings: fpga: Add bindings document for Xilinx LogiCore PR Decoupler

PATCH In review Moritz Fischer 3 participants 4 messages Apr 9, 2017 – Apr 13, 2017

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Device tree bindings Arm/Zynq architecture FPGA manager framework

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Moritz Fischer

author maintainer

2017-04-09 17:10 UTC #0 lore raw

PATCH v5 1/1 dt-bindings: fpga: Add bindings document for Xilinx LogiCore PR Decoupler

This adds the binding documentation for the Xilinx LogiCORE PR Decoupler soft core.

Signed-off-by Moritz Fischer <[email protected]>

Signed-off-by Michal Simek <[email protected]>

Acked-by Alan Tull <[email protected]>

Cc Sören Brinkmann <[email protected]>

Cc [email protected]

---

Changes from v4:
- Ssubject line
- Replaced 'or' by 'followed by' as suggested by Rob

Changes from v3:
- Addressed Michal's comments
- Addressed Alan's Comments
- Added Alan's Acked-by

Changes from v2:
- Added refence to generic fpga-region bindings
- Fixed up reg property in example
- Added fallback to "xlnx,pr-decoupler" without version

Changes from v1:
- Added clock names & clock to example
- Merged some of the description from Michal's version

---
 .../bindings/fpga/xilinx-pr-decoupler.txt          | 36 ++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt

Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file +36 -0

new file mode 100644
index 0000000..b2c58fb
@@ -0,0 +1,36 @@
+Xilinx LogiCORE Partial Reconfig Decoupler Softcore
+
+The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
+decouplers / fpga bridges.
+The controller can decouple/disable the bridges which prevents signal
+changes from passing through the bridge.  The controller can also
+couple / enable the bridges which allows traffic to pass through the
+bridge normally.
+
+The Driver supports only MMIO handling. A PR region can have multiple
+PR Decouplers which can be handled independently or chained via decouple/
+decouple_status signals.
+
+Required properties:
+- compatible		: Should contain "xlnx,pr-decoupler-1.00" followed by
+                          "xlnx,pr-decoupler"
+- regs			: base address and size for decoupler module
+- clocks		: input clock to IP
+- clock-names		: should contain "aclk"
+
+Optional properties:
+- bridge-enable		: 0 if driver should disable bridge at startup
+			  1 if driver should enable bridge at startup
+			  Default is to leave bridge in current state.
+
+See Documentation/devicetree/bindings/fpga/fpga-region.txt for generic bindings.
+
+Example:
+	fpga-bridge@100000450 {
+		compatible = "xlnx,pr-decoupler-1.00",
+			     "xlnx-pr-decoupler";
+		regs = <0x10000045 0x10>;
+		clocks = <&clkc 15>;
+		clock-names = "aclk";
+		bridge-enable = <0>;
+	};

Signature · 6 lines

2.7.4

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Rob Herring

maintainer

2017-04-13 20:07 UTC #1 lore raw

Quoted 54 lines · Moritz Fischer

This adds the binding documentation for the Xilinx LogiCORE PR Decoupler soft core.
Signed-off-by Moritz Fischer <[email protected]>
Signed-off-by Michal Simek <[email protected]>
Acked-by Alan Tull <[email protected]>
Cc Sören Brinkmann <[email protected]>
Cc [email protected]
Cc [email protected]
---
Changes from v4:
- Ssubject line
- Replaced 'or' by 'followed by' as suggested by Rob
Changes from v3:
- Addressed Michal's comments
- Addressed Alan's Comments
- Added Alan's Acked-by
Changes from v2:
- Added refence to generic fpga-region bindings
- Fixed up reg property in example
- Added fallback to "xlnx,pr-decoupler" without version
Changes from v1:
- Added clock names & clock to example
- Merged some of the description from Michal's version
---
 .../bindings/fpga/xilinx-pr-decoupler.txt          | 36 ++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file +14 -0
new file mode 100644
index 0000000..b2c58fb
@@ -0,0 +1,36 @@
+Xilinx LogiCORE Partial Reconfig Decoupler Softcore
+
+The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
+decouplers / fpga bridges.
+The controller can decouple/disable the bridges which prevents signal
+changes from passing through the bridge.  The controller can also
+couple / enable the bridges which allows traffic to pass through the
+bridge normally.
+
+The Driver supports only MMIO handling. A PR region can have multiple
+PR Decouplers which can be handled independently or chained via decouple/
+decouple_status signals.
+
+Required properties:

Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt line 24

Quoted 10 lines

Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file +10 -0

+- compatible		: Should contain "xlnx,pr-decoupler-1.00" followed by
+                          "xlnx,pr-decoupler"
+- regs			: base address and size for decoupler module
+- clocks		: input clock to IP
+- clock-names		: should contain "aclk"
+
+Optional properties:
+- bridge-enable		: 0 if driver should disable bridge at startup
+			  1 if driver should enable bridge at startup
+			  Default is to leave bridge in current state.

Did this get into a common location? If so, then just "see .../?.txt" is enough of a description.

Rob

Alan Tull

2017-04-13 20:25 UTC #2 lore raw

Quoted 60 lines · Rob Herring

Quoted 59 lines · Moritz Fischer
This adds the binding documentation for the Xilinx LogiCORE PR Decoupler soft core.
Signed-off-by Moritz Fischer <[email protected]>
Signed-off-by Michal Simek <[email protected]>
Acked-by Alan Tull <[email protected]>
Cc Sören Brinkmann <[email protected]>
Cc [email protected]
Cc [email protected]
---
Changes from v4:
- Ssubject line
- Replaced 'or' by 'followed by' as suggested by Rob
Changes from v3:
- Addressed Michal's comments
- Addressed Alan's Comments
- Added Alan's Acked-by
Changes from v2:
- Added refence to generic fpga-region bindings
- Fixed up reg property in example
- Added fallback to "xlnx,pr-decoupler" without version
Changes from v1:
- Added clock names & clock to example
- Merged some of the description from Michal's version
---
 .../bindings/fpga/xilinx-pr-decoupler.txt          | 36 ++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file +19 -0
new file mode 100644
index 0000000..b2c58fb
@@ -0,0 +1,36 @@
+Xilinx LogiCORE Partial Reconfig Decoupler Softcore
+
+The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
+decouplers / fpga bridges.
+The controller can decouple/disable the bridges which prevents signal
+changes from passing through the bridge.  The controller can also
+couple / enable the bridges which allows traffic to pass through the
+bridge normally.
+
+The Driver supports only MMIO handling. A PR region can have multiple
+PR Decouplers which can be handled independently or chained via decouple/
+decouple_status signals.
+
+Required properties:
+- compatible         : Should contain "xlnx,pr-decoupler-1.00" followed by
+                          "xlnx,pr-decoupler"
+- regs                       : base address and size for decoupler module
+- clocks             : input clock to IP
+- clock-names                : should contain "aclk"

Quoted 8 lines

Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt line 24
Quoted 5 lines
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file +5 -0
+
+Optional properties:
+- bridge-enable              : 0 if driver should disable bridge at startup
+                       1 if driver should enable bridge at startup
+                       Default is to leave bridge in current state.
Did this get into a common location? If so, then just "see .../?.txt" is enough of a description.

IIRC we went with this as is, with the intent of moving it to a common location in a separate patch. This binding shows up in a a few bindings docs, so one patch could move it from all of them at the same time. That hasn't happened yet.

Alan

Quoted 6 lines

Rob
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Rob Herring

maintainer Acked-by

2017-04-13 21:24 UTC #3 lore raw

Quoted 70 lines · Alan Tull

Quoted 60 lines · Rob Herring
Quoted 59 lines · Moritz Fischer
This adds the binding documentation for the Xilinx LogiCORE PR Decoupler soft core.
Signed-off-by Moritz Fischer <[email protected]>
Signed-off-by Michal Simek <[email protected]>
Acked-by Alan Tull <[email protected]>
Cc Sören Brinkmann <[email protected]>
Cc [email protected]
Cc [email protected]
---
Changes from v4:
- Ssubject line
- Replaced 'or' by 'followed by' as suggested by Rob
Changes from v3:
- Addressed Michal's comments
- Addressed Alan's Comments
- Added Alan's Acked-by
Changes from v2:
- Added refence to generic fpga-region bindings
- Fixed up reg property in example
- Added fallback to "xlnx,pr-decoupler" without version
Changes from v1:
- Added clock names & clock to example
- Merged some of the description from Michal's version
---
 .../bindings/fpga/xilinx-pr-decoupler.txt          | 36 ++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file +19 -0
new file mode 100644
index 0000000..b2c58fb
@@ -0,0 +1,36 @@
+Xilinx LogiCORE Partial Reconfig Decoupler Softcore
+
+The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
+decouplers / fpga bridges.
+The controller can decouple/disable the bridges which prevents signal
+changes from passing through the bridge.  The controller can also
+couple / enable the bridges which allows traffic to pass through the
+bridge normally.
+
+The Driver supports only MMIO handling. A PR region can have multiple
+PR Decouplers which can be handled independently or chained via decouple/
+decouple_status signals.
+
+Required properties:
+- compatible         : Should contain "xlnx,pr-decoupler-1.00" followed by
+                          "xlnx,pr-decoupler"
+- regs                       : base address and size for decoupler module
+- clocks             : input clock to IP
+- clock-names                : should contain "aclk"
Quoted 8 lines
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt line 24
Quoted 5 lines
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file +5 -0
+
+Optional properties:
+- bridge-enable              : 0 if driver should disable bridge at startup
+                       1 if driver should enable bridge at startup
+                       Default is to leave bridge in current state.
Did this get into a common location? If so, then just "see .../?.txt" is enough of a description.

Quoted 4 lines

IIRC we went with this as is, with the intent of moving it to a common location in a separate patch. This binding shows up in a a few bindings docs, so one patch could move it from all of them at the same time. That hasn't happened yet.

Okay, I'll trust you to do that.

Acked-by Rob Herring <[email protected]>

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To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html