armv8: ls1088a: Add NXP LS1088A SoC support

PATCH Superseded Ashish Kumar 3 participants 5 messages Aug 11, 2017 – Aug 13, 2017

Subsystems (3)

Network drivers Arm (32-bit) Arm/actions semi architecture

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Ashish Kumar

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2017-08-11 07:24 UTC #0 lore raw

PATCH v3 1/3 armv8: ls1088a: Add NXP LS1088A SoC support

The QorIQ LS1088A processor is built on the Layerscape architecture combining eight ARM A53 processor cores with advanced, high-performance datapath acceleration and networks, peripheral interfaces required for networking, wireless infrastructure, and general-purpose embedded applications.

LS1088A is compliant to the Layerscape Chassis Generation 3.

Features summary:
- Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs
- Cores are in 2 cluster of 4-cores each
- Cache coherent interconnect (CCI-400)
- One 64-bit DDR4 SDRAM memory controller with ECC
- Data path acceleration architecture 2.0 (DPAA2)
- Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs
- QSPI, IFC, 3 PCIe, 1 SATA, 2 USB, 1 SDXC, 2 DUARTs etc

Signed-off-by Alison Wang <[email protected]>

Signed-off-by Prabhakar Kushwaha <[email protected]>

Signed-off-by Ashish Kumar <[email protected]>

Signed-off-by Raghav Dogra <[email protected]>

Signed-off-by Shaohui Xie <[email protected]>

---

v2:
Fix indentaion in commit msg
Separate RDB and Si specific file
Move Macros to Kconfig

v3:
1.Re-based on top of
commit d529124fdcf941c34074fd1ce600f4b1b4a7dd07
Merge: f0ca30f 6a5691e
Author: Tom Rini <[email protected]>
Date: Tue Aug 8 17:06:19 2017 -0400

    Merge git://git.denx.de/u-boot-x86

2.Incorporate review comments on v2
Clean up done

3.Migrate changes from ls1088ardb_stream_id.h to stream_id_lsch3.h

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig          |  39 ++++++-
 arch/arm/cpu/armv8/fsl-layerscape/Makefile         |   4 +
 .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c    |  10 ++
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S       |   6 +-
 arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 126 +++++++++++++++++++++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c            |   5 +
 arch/arm/dts/fsl-ls1088a.dtsi                      |  78 +++++++++++++
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |  62 +++++++++-
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h     |   4 +
 .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |   3 +-
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  11 ++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h     |   4 +
 .../asm/arch-fsl-layerscape/stream_id_lsch3.h      |  14 +++
 drivers/ddr/fsl/util.c                             |   2 +-
 drivers/net/ldpaa_eth/Makefile                     |   1 +
 drivers/net/ldpaa_eth/ls1088a.c                    |  87 ++++++++++++++
 16 files changed, 447 insertions(+), 9 deletions(-)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
 create mode 100644 arch/arm/dts/fsl-ls1088a.dtsi
 create mode 100644 drivers/net/ldpaa_eth/ls1088a.c

arch/arm/cpu/armv8/fsl-layerscape/Kconfig +35 -4

index 1132969..a3c7490 100644
@@ -49,6 +49,29 @@ config ARCH_LS1046A
 	select BOARD_EARLY_INIT_F
 	imply SCSI
 
+config ARCH_LS1088A
+	bool
+	select ARMV8_SET_SMPEN
+	select FSL_LSCH3
+	select SYS_FSL_DDR
+	select SYS_FSL_DDR_LE
+	select SYS_FSL_DDR_VER_50
+	select SYS_FSL_ERRATUM_A009803
+	select SYS_FSL_ERRATUM_A009942
+	select SYS_FSL_ERRATUM_A010165
+	select SYS_FSL_ERRATUM_A008511
+	select SYS_FSL_ERRATUM_A008850
+	select SYS_FSL_HAS_CCI400
+	select SYS_FSL_HAS_DDR4
+	select SYS_FSL_HAS_SEC
+	select SYS_FSL_SEC_COMPAT_5
+	select SYS_FSL_SEC_LE
+	select SYS_FSL_SRDS_1
+	select SYS_FSL_SRDS_2
+	select FSL_TZASC_1
+	select ARCH_EARLY_INIT_R
+	select BOARD_EARLY_INIT_F
+
 config ARCH_LS2080A
 	bool
 	select ARMV8_SET_SMPEN

@@ -60,6 +83,7 @@ config ARCH_LS2080A
 	select SYS_FSL_DDR
 	select SYS_FSL_DDR_LE
 	select SYS_FSL_DDR_VER_50
+	select SYS_FSL_HAS_CCN504
 	select SYS_FSL_HAS_DP_DDR
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_HAS_DDR4

@@ -98,7 +122,7 @@ config FSL_LSCH3
 
 config FSL_MC_ENET
 	bool "Management Complex network"
-	depends on ARCH_LS2080A
+	depends on ARCH_LS2080A || ARCH_LS1088A
 	default y
 	select RESV_RAM
 	help

@@ -114,6 +138,7 @@ config FSL_PCIE_COMPAT
 	default "fsl,ls1043a-pcie" if ARCH_LS1043A
 	default "fsl,ls1046a-pcie" if ARCH_LS1046A
 	default "fsl,ls2080a-pcie" if ARCH_LS2080A
+	default "fsl,ls1080a-pcie" if ARCH_LS1088A
 	help
 	  This compatible is used to find pci controller node in Kernel DT
 	  to complete fixup.

@@ -228,6 +253,7 @@ config MAX_CPUS
 	default 4 if ARCH_LS1043A
 	default 4 if ARCH_LS1046A
 	default 16 if ARCH_LS2080A
+	default 8 if ARCH_LS1088A
 	default 1
 	help
 	  Set this number to the maximum number of possible CPUs in the SoC.

@@ -259,14 +285,17 @@ config SYS_CCI400_OFFSET
 
 config SYS_FSL_IFC_BANK_COUNT
 	int "Maximum banks of Integrated flash controller"
-	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
+	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
 	default 4 if ARCH_LS1043A
 	default 4 if ARCH_LS1046A
-	default 8 if ARCH_LS2080A
+	default 8 if ARCH_LS2080A || ARCH_LS1088A
 
 config SYS_FSL_HAS_CCI400
 	bool
 
+config SYS_FSL_HAS_CCN504
+	bool
+
 config SYS_FSL_HAS_DP_DDR
 	bool

@@ -308,6 +337,7 @@ config SYS_FSL_PCLK_DIV
 	int "Platform clock divider"
 	default 1 if ARCH_LS1043A
 	default 1 if ARCH_LS1046A
+	default 1 if ARCH_LS1088A
 	default 2
 	help
 	  This is the divider that is used to derive Platform clock from

@@ -401,7 +431,8 @@ config SYS_FSL_ERRATUM_A009929
 config SYS_MC_RSV_MEM_ALIGN
 	hex "Management Complex reserved memory alignment"
 	depends on RESV_RAM
-	default 0x20000000
+	default 0x20000000 if ARCH_LS2080A
+	default 0x70000000 if ARCH_LS1088A
 	help
 	  Reserved memory needs to be aligned for MC to use. Default value
 	  is 512MB.

arch/arm/cpu/armv8/fsl-layerscape/Makefile +4 -0

index e3ce018..115c3fc 100644
@@ -38,3 +38,7 @@ endif
 ifneq ($(CONFIG_ARCH_LS1046A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
 endif
+
+ifneq ($(CONFIG_ARCH_LS1088A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o
+endif

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +10 -0

index ef97556..13def18 100644
@@ -28,6 +28,11 @@ __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
 	return;
 }
 
+__weak int serdes_get_number(int serdes, int cfg)
+{
+	return cfg;
+}
+
 int is_serdes_configured(enum srds_prtcl device)
 {
 	int ret = 0;

@@ -73,6 +78,9 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 		printf("invalid SerDes%d\n", sd);
 		break;
 	}
+
+	cfg = serdes_get_number(sd, cfg);
+
 	/* Is serdes enabled at all? */
 	if (cfg == 0)
 		return -ENODEV;

@@ -99,6 +107,8 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
 
 	cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
 	cfg >>= sd_prctl_shift;
+
+	cfg = serdes_get_number(sd, cfg);
 	printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
 
 	if (!is_serdes_prtcl_valid(sd, cfg))

arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +4 -2

index 3136e3f..d943f84 100644
@@ -76,7 +76,7 @@ ENTRY(lowlevel_init)
 	switch_el x1, 1f, 100f, 100f	/* skip if not in EL3 */
 1:
 
-#ifdef CONFIG_FSL_LSCH3
+#if defined(CONFIG_FSL_LSCH3) && defined (CONFIG_SYS_FSL_HAS_CCN504)
 
 	/* Set Wuo bit for RN-I 20 */
 #ifdef CONFIG_ARCH_LS2080A

@@ -338,7 +338,9 @@ get_svr:
 	ldr	x1, =FSL_LSCH3_SVR
 	ldr	w0, [x1]
 	ret
+#endif
 
+#ifdef CONFIG_SYS_FSL_HAS_CCN504
 hnf_pstate_poll:
 	/* x0 has the desired status, return 0 for success, 1 for timeout
 	 * clobber x1, x2, x3, x4, x6, x7

@@ -420,7 +422,7 @@ ENTRY(__asm_flush_l3_dcache)
 	mov	lr, x29
 	ret
 ENDPROC(__asm_flush_l3_dcache)
-#endif
+#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
 
 #ifdef CONFIG_MP
 	/* Keep literals not used by the secondary boot code outside it */

arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c new file +126 -0

126 lines not on this page · raw message

arch/arm/cpu/armv8/fsl-layerscape/soc.c +5 -0

index ddb7d82..18820f6 100644
@@ -24,6 +24,7 @@
 #ifdef CONFIG_CHAIN_OF_TRUST
 #include <fsl_validate.h>
 #endif
+#include <fsl_immap.h>
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -215,11 +216,14 @@ int sata_init(void)
 {
 	struct ccsr_ahci __iomem *ccsr_ahci;
 
+#ifdef CONFIG_SYS_SATA2
 	ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
 	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
 	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
 	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
+#endif
 
+#ifdef CONFIG_SYS_SATA1
 	ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
 	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
 	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);

@@ -227,6 +231,7 @@ int sata_init(void)
 
 	ahci_init((void __iomem *)CONFIG_SYS_SATA1);
 	scsi_scan(false);
+#endif
 
 	return 0;
 }

arch/arm/dts/fsl-ls1088a.dtsi new file +78 -0

78 lines not on this page · raw message

arch/arm/include/asm/arch-fsl-layerscape/config.h +61 -1

74 lines not on this page · raw message

arch/arm/include/asm/arch-fsl-layerscape/cpu.h +4 -0

index c4e5ecc..0126783 100644
@@ -24,6 +24,10 @@ static struct cpu_type cpu_type_list[] = {
 	CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
 	CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
 	CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
+	CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
+	CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
+	CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
+	CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
 };
 
 #ifndef CONFIG_SYS_DCACHE_OFF

arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +2 -1

index a8f9a50..a2c7578 100644
@@ -9,7 +9,7 @@
 
 #include <config.h>
 
-#ifdef CONFIG_ARCH_LS2080A
+#ifdef CONFIG_FSL_LSCH3
 enum srds_prtcl {
 	/*
 	 * Nobody will check whether the device 'NONE' has been configured,

@@ -158,6 +158,7 @@ void fsl_serdes_init(void);
 int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
 int is_serdes_prtcl_valid(int serdes, u32 prtcl);
+int serdes_get_number(int serdes, int cfg);
 
 #ifdef CONFIG_FSL_LSCH2
 const char *serdes_clock_to_string(u32 clock);

arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +11 -0

index 59410aa..99a7413 100644
@@ -246,6 +246,17 @@ struct ccsr_gur {
 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT	FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
 #define FSL_CHASSIS3_SRDS1_REGSR	29
 #define FSL_CHASSIS3_SRDS2_REGSR	29
+#elif defined(CONFIG_ARCH_LS1088A)
+#define	FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK	0xFFFF0000
+#define	FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT	16
+#define	FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK	0x0000FFFF
+#define	FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT	0
+#define FSL_CHASSIS3_SRDS1_PRTCL_MASK	FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT	FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS2_PRTCL_MASK	FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT	FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS1_REGSR	29
+#define FSL_CHASSIS3_SRDS2_REGSR	30
 #endif
 #define RCW_SB_EN_REG_INDEX	9
 #define RCW_SB_EN_MASK		0x00000400

arch/arm/include/asm/arch-fsl-layerscape/soc.h +4 -0

index aeb1273..ea8aced 100644
@@ -57,6 +57,10 @@ struct cpu_type {
 #define SVR_LS1023A		0x879208
 #define SVR_LS1046A		0x870700
 #define SVR_LS1026A		0x870708
+#define SVR_LS1048A		0x870320
+#define SVR_LS1084A		0x870302
+#define SVR_LS1088A		0x870300
+#define SVR_LS1044A		0x870322
 #define SVR_LS2045A		0x870120
 #define SVR_LS2080A		0x870110
 #define SVR_LS2085A		0x870100

arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +14 -0

index d7d527d..d1891c4 100644
@@ -66,12 +66,26 @@
 #define FSL_USB2_STREAM_ID		2
 #define FSL_SDMMC_STREAM_ID		3
 #define FSL_SATA1_STREAM_ID		4
+
+#if defined(CONFIG_ARCH_LS2080A)
 #define FSL_SATA2_STREAM_ID		5
+#endif
+
+#if defined(CONFIG_ARCH_LS2080A)
 #define FSL_DMA_STREAM_ID		6
+#elif defined(CONFIG_ARCH_LS1088A)
+#define FSL_DMA_STREAM_ID		5
+#endif
 
 /* PCI - programmed in PEXn_LUT */
 #define FSL_PEX_STREAM_ID_START		7
+
+#if defined(CONFIG_ARCH_LS2080A)
 #define FSL_PEX_STREAM_ID_END		22
+#elif defined(CONFIG_ARCH_LS1088A)
+#define FSL_PEX_STREAM_ID_END		18
+#endif
+
 
 /* DPAA2 - set in MC DPC and alloced by MC */
 #define FSL_DPAA2_STREAM_ID_START	23

drivers/ddr/fsl/util.c +1 -1

index 0a305b3..d6e6e78 100644
@@ -390,7 +390,7 @@ void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
 
 void remove_unused_controllers(fsl_ddr_info_t *info)
 {
-#ifdef CONFIG_FSL_LSCH3
+#ifdef CONFIG_SYS_FSL_HAS_CCN504
 	int i;
 	u64 nodeid;
 	void *hnf_sam_ctrl = (void *)(CCI_HN_F_0_BASE + CCN_HN_F_SAM_CTL);

drivers/net/ldpaa_eth/Makefile +1 -0

index 08675ec..13ecd38 100644
@@ -7,3 +7,4 @@
 obj-y += ldpaa_wriop.o
 obj-y += ldpaa_eth.o
 obj-$(CONFIG_ARCH_LS2080A) += ls2080a.o
+obj-$(CONFIG_ARCH_LS1088A) += ls1088a.o

drivers/net/ldpaa_eth/ls1088a.c new file +87 -0

87 lines not on this page · raw message

Signature · 1 line

2.7.4

Ashish Kumar

author

2017-08-11 07:24 UTC #1 lore raw

PATCH v3 2/3 armv8: ls1088ardb: Add support for LS1088ARDB platform

LS1088A is an ARMv8 implementation. The LS1088ARDB is an evaluatoin platform that supports the LS1088A family SoCs. This patch add basic support of the platform.

Signed-off-by Alison Wang <[email protected]>

Signed-off-by Prabhakar Kushwaha <[email protected]>

Signed-off-by Ashish Kumar <[email protected]>

Signed-off-by Raghav Dogra <[email protected]>

Signed-off-by Shaohui Xie <[email protected]>

---
v2:
Fix indentaion in commit msg
Separate RDB and Si specific file

v3:
1.Re-based on top of
commit d529124fdcf941c34074fd1ce600f4b1b4a7dd07
Merge: f0ca30f 6a5691e
Author: Tom Rini <[email protected]>
Date: Tue Aug 8 17:06:19 2017 -0400

    Merge git://git.denx.de/u-boot-x86

2.Incorporate review comments on v2
Remove EMU support
Remove RAW timings
Disable default enabled CONFIG_DISPLAY_BOARDINFO and enable LATE_CONFIG_DISPLAY_BOARDINFO

3.Include PPA support

 arch/arm/Kconfig                          |  12 ++
 arch/arm/cpu/armv8/Kconfig                |   1 +
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig |   1 +
 arch/arm/dts/Makefile                     |   3 +-
 arch/arm/dts/fsl-ls1088a-rdb.dts          |  40 ++++
 board/freescale/ls1088a/Kconfig           |  15 ++
 board/freescale/ls1088a/MAINTAINERS       |   9 +
 board/freescale/ls1088a/Makefile          |   9 +
 board/freescale/ls1088a/ddr.c             | 106 ++++++++++
 board/freescale/ls1088a/ddr.h             |  44 ++++
 board/freescale/ls1088a/eth_ls1088ardb.c  | 102 +++++++++
 board/freescale/ls1088a/ls1088a.c         | 340 ++++++++++++++++++++++++++++++
 board/freescale/ls1088a/ls1088a_qixis.h   |  34 +++
 configs/ls1088ardb_qspi_defconfig         |  35 +++
 include/configs/ls1088a_common.h          | 204 ++++++++++++++++++
 include/configs/ls1088ardb.h              | 335 +++++++++++++++++++++++++++++
 16 files changed, 1289 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/fsl-ls1088a-rdb.dts
 create mode 100644 board/freescale/ls1088a/Kconfig
 create mode 100644 board/freescale/ls1088a/MAINTAINERS
 create mode 100644 board/freescale/ls1088a/Makefile
 create mode 100644 board/freescale/ls1088a/ddr.c
 create mode 100644 board/freescale/ls1088a/ddr.h
 create mode 100644 board/freescale/ls1088a/eth_ls1088ardb.c
 create mode 100644 board/freescale/ls1088a/ls1088a.c
 create mode 100644 board/freescale/ls1088a/ls1088a_qixis.h
 create mode 100644 configs/ls1088ardb_qspi_defconfig
 create mode 100644 include/configs/ls1088a_common.h
 create mode 100644 include/configs/ls1088ardb.h

arch/arm/Kconfig +12 -0

index 9cfeede..dcff602 100644
@@ -892,6 +892,17 @@ config TARGET_LS1012AFRDM
 	  development platform that supports the QorIQ LS1012A
 	  Layerscape Architecture processor.
 
+config TARGET_LS1088ARDB
+	bool "Support ls1088ardb"
+	select ARCH_LS1088A
+	select ARM64
+	select ARMV8_MULTIENTRY
+	help
+	  Support for NXP LS1088ARDB platform.
+	  The LS1088AA Reference design board (RDB) is a high-performance
+	  development platform that supports the QorIQ LS1088A
+	  Layerscape Architecture processor.
+
 config TARGET_LS1021AQDS
 	bool "Support ls1021aqds"
 	select BOARD_LATE_INIT

@@ -1174,6 +1185,7 @@ source "board/creative/xfi3/Kconfig"
 source "board/freescale/ls2080a/Kconfig"
 source "board/freescale/ls2080aqds/Kconfig"
 source "board/freescale/ls2080ardb/Kconfig"
+source "board/freescale/ls1088a/Kconfig"
 source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"

arch/arm/cpu/armv8/Kconfig +1 -0

index 8e4c3dd..aecdf81 100644
@@ -88,6 +88,7 @@ config PSCI_RESET
 	depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && !TARGET_LS2080A_EMU && \
 		   !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
 		   !TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \
+		   !TARGET_LS1088ARDB && \
 		   !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
 		   !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
 		   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \

arch/arm/cpu/armv8/fsl-layerscape/Kconfig +1 -0

index a3c7490..35f3118 100644
@@ -207,6 +207,7 @@ config SYS_LS_PPA_FW_ADDR
 	default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
 	default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
 	default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
+	default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A
 	default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
 	default 0x400000 if SYS_LS_PPA_FW_IN_MMC
 	default 0x400000 if SYS_LS_PPA_FW_IN_NAND

arch/arm/dts/Makefile +2 -1

index c2dc240..6f03a3f 100644
@@ -188,7 +188,8 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 	fsl-ls2080a-rdb.dtb \
 	fsl-ls2081a-rdb.dtb \
-	fsl-ls2088a-rdb-qspi.dtb
+	fsl-ls2088a-rdb-qspi.dtb \
+	fsl-ls1088a-rdb.dtb
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
 	fsl-ls1043a-qds-lpuart.dtb \
 	fsl-ls1043a-rdb.dtb \

arch/arm/dts/fsl-ls1088a-rdb.dts new file +40 -0

new file mode 100644
index 0000000..30ceed8
@@ -0,0 +1,40 @@
+/*
+ * NXP ls1088a RDB board device tree source
+ *
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "fsl-ls1088a.dtsi"
+
+/ {
+	model = "NXP Layerscape 1088a RDB Board";
+	compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
+	aliases {
+		spi0 = &qspi;
+	};
+};
+
+&qspi {
+	bus-num = <0>;
+	status = "okay";
+
+	qflash0: s25fs512s at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <50000000>;
+		reg = <0>;
+	};
+
+	qflash1: s25fs512s at 1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <50000000>;
+		reg = <1>;
+	 };
+};

board/freescale/ls1088a/Kconfig new file +15 -0

new file mode 100644
index 0000000..a4d8223
@@ -0,0 +1,15 @@
+if TARGET_LS1088ARDB
+
+config SYS_BOARD
+	default "ls1088a"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1088ardb"
+
+endif

board/freescale/ls1088a/MAINTAINERS new file +9 -0

new file mode 100644
index 0000000..1abbf91
@@ -0,0 +1,9 @@
+LS1088ARDB BOARD
+M:	Prabhakar Kushwaha <[email protected]>
+M:	Ashish Kumar <[email protected]>
+S:	Maintained
+F:	board/freescale/ls1088a/
+F:	include/configs/ls1088ardb.h
+F:	configs/ls1088ardb_qspi_defconfig
+F:	configs/ls1088ardb_sdcard_defconfig
+F:	configs/ls1088ardb_sdcard_qspi_defconfig

board/freescale/ls1088a/Makefile new file +9 -0

new file mode 100644
index 0000000..e997cf1
@@ -0,0 +1,9 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += ls1088a.o
+obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o
+obj-y += ddr.o

board/freescale/ls1088a/ddr.c new file +106 -0

106 lines not on this page · raw message

board/freescale/ls1088a/ddr.h new file +44 -0

44 lines not on this page · raw message

board/freescale/ls1088a/eth_ls1088ardb.c new file +102 -0

102 lines not on this page · raw message

board/freescale/ls1088a/ls1088a.c new file +340 -0

340 lines not on this page · raw message

board/freescale/ls1088a/ls1088a_qixis.h new file +34 -0

new file mode 100644
index 0000000..9757d1b
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1088AQDS_QIXIS_H__
+#define __LS1088AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1088AQDS */
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66			0x0
+#define QIXIS_SYSCLK_83			0x1
+#define QIXIS_SYSCLK_100		0x2
+#define QIXIS_SYSCLK_125		0x3
+#define QIXIS_SYSCLK_133		0x4
+#define QIXIS_SYSCLK_150		0x5
+#define QIXIS_SYSCLK_160		0x6
+#define QIXIS_SYSCLK_166		0x7
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66			0x0
+#define QIXIS_DDRCLK_100		0x1
+#define QIXIS_DDRCLK_125		0x2
+#define QIXIS_DDRCLK_133		0x3
+
+/* BRDCFG2 - SD clock*/
+#define QIXIS_SDCLK1_100		0x0
+#define QIXIS_SDCLK1_125		0x1
+#define QIXIS_SDCLK1_165		0x2
+#define QIXIS_SDCLK1_100_SP		0x3
+
+#endif

configs/ls1088ardb_qspi_defconfig new file +35 -0

new file mode 100644
index 0000000..42e0203
@@ -0,0 +1,35 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1088ARDB=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
+CONFIG_BOOTDELAY=10
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_FSL_LS_PPA=y

include/configs/ls1088a_common.h new file +204 -0

204 lines not on this page · raw message

include/configs/ls1088ardb.h new file +335 -0

335 lines not on this page · raw message

Signature · 1 line

2.7.4

Prabhakar Kushwaha

2017-08-13 02:14 UTC #2 lore raw

PATCH v3 2/3 armv8: ls1088ardb: Add support for LS1088ARDB platform

Hi Ashish,

Quoted 42 lines

-----Original Message-----
From: Ashish Kumar [mailto:Ashish.Kumar at nxp.com]
Sent: Friday, August 11, 2017 12:54 PM
To: u-boot at lists.denx.de
Cc: York Sun <[email protected]>; Ashish Kumar <[email protected]>; Alison Wang <[email protected]>; Prabhakar Kushwaha <[email protected]>; Raghav Dogra <[email protected]>; Shaohui Xie <[email protected]>
Subject: [PATCH v3 2/3] armv8: ls1088ardb: Add support for LS1088ARDB platform
LS1088A is an ARMv8 implementation. The LS1088ARDB is an evaluatoin platform that supports the LS1088A family SoCs. This patch add basic support of the platform.
Signed-off-by Alison Wang <[email protected]>
Signed-off-by Prabhakar Kushwaha <[email protected]>
Signed-off-by Ashish Kumar <[email protected]>
Signed-off-by Raghav Dogra <[email protected]>
Signed-off-by Shaohui Xie <[email protected]>
---
v2:
Fix indentaion in commit msg
Separate RDB and Si specific file
v3:
1.Re-based on top of
commit d529124fdcf941c34074fd1ce600f4b1b4a7dd07
Merge: f0ca30f 6a5691e
Author: Tom Rini <[email protected]>
Date: Tue Aug 8 17:06:19 2017 -0400
    Merge git://git.denx.de/u-boot-x86
2.Incorporate review comments on v2
Remove EMU support
Remove RAW timings
Disable default enabled CONFIG_DISPLAY_BOARDINFO and enable
LATE_CONFIG_DISPLAY_BOARDINFO
3.Include PPA support

Quoted 7 lines

 arch/arm/Kconfig                          |  12 ++
 arch/arm/cpu/armv8/Kconfig                |   1 +
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig |   1 +
 arch/arm/dts/Makefile                     |   3 +-
 arch/arm/dts/fsl-ls1088a-rdb.dts          |  40 ++++
 board/freescale/ls1088a/Kconfig           |  15 ++
 board/freescale/ls1088a/MAINTAINERS       |   9 +

Please add REAdME file in ls1088a providing details of board (default switch settings, boot method + xqsgmii riser card (its port vs DPMAC mapping)

--prabhakar

York Sun

2017-08-11 17:27 UTC #3 lore raw

PATCH v3 1/3 armv8: ls1088a: Add NXP LS1088A SoC support

In reply to Ashish Kumar

Quoted 8 lines · Ashish Kumar

The QorIQ LS1088A processor is built on the Layerscape architecture combining eight ARM A53 processor cores with advanced, high-performance datapath acceleration and networks, peripheral interfaces required for networking, wireless infrastructure, and general-purpose embedded applications.
LS1088A is compliant to the Layerscape Chassis Generation 3.

s/compliant to/compliant with/

Quoted 109 lines

Features summary:
- Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs
- Cores are in 2 cluster of 4-cores each
- Cache coherent interconnect (CCI-400)
- One 64-bit DDR4 SDRAM memory controller with ECC
- Data path acceleration architecture 2.0 (DPAA2)
- Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs
- QSPI, IFC, 3 PCIe, 1 SATA, 2 USB, 1 SDXC, 2 DUARTs etc
Signed-off-by Alison Wang <[email protected]>
Signed-off-by Prabhakar Kushwaha <[email protected]>
Signed-off-by Ashish Kumar <[email protected]>
Signed-off-by Raghav Dogra <[email protected]>
Signed-off-by Shaohui Xie <[email protected]>
---
v2:
Fix indentaion in commit msg
Separate RDB and Si specific file
Move Macros to Kconfig
v3:
1.Re-based on top of
commit d529124fdcf941c34074fd1ce600f4b1b4a7dd07
Merge: f0ca30f 6a5691e
Author: Tom Rini <[email protected]>
Date: Tue Aug 8 17:06:19 2017 -0400
     Merge git://git.denx.de/u-boot-x86
2.Incorporate review comments on v2
Clean up done
3.Migrate changes from ls1088ardb_stream_id.h to stream_id_lsch3.h
  arch/arm/cpu/armv8/fsl-layerscape/Kconfig          |  39 ++++++-
  arch/arm/cpu/armv8/fsl-layerscape/Makefile         |   4 +
  .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c    |  10 ++
  arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S       |   6 +-
  arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 126 +++++++++++++++++++++
  arch/arm/cpu/armv8/fsl-layerscape/soc.c            |   5 +
  arch/arm/dts/fsl-ls1088a.dtsi                      |  78 +++++++++++++
  arch/arm/include/asm/arch-fsl-layerscape/config.h  |  62 +++++++++-
  arch/arm/include/asm/arch-fsl-layerscape/cpu.h     |   4 +
  .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |   3 +-
  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  11 ++
  arch/arm/include/asm/arch-fsl-layerscape/soc.h     |   4 +
  .../asm/arch-fsl-layerscape/stream_id_lsch3.h      |  14 +++
  drivers/ddr/fsl/util.c                             |   2 +-
  drivers/net/ldpaa_eth/Makefile                     |   1 +
  drivers/net/ldpaa_eth/ls1088a.c                    |  87 ++++++++++++++
  16 files changed, 447 insertions(+), 9 deletions(-)
create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c create mode 100644 arch/arm/dts/fsl-ls1088a.dtsi
create mode 100644 drivers/net/ldpaa_eth/ls1088a.c
arch/arm/cpu/armv8/fsl-layerscape/Kconfig +25 -1
index 1132969..a3c7490 100644
@@ -49,6 +49,29 @@ config ARCH_LS1046A
  	select BOARD_EARLY_INIT_F
  	imply SCSI
 
+config ARCH_LS1088A
+	bool
+	select ARMV8_SET_SMPEN
+	select FSL_LSCH3
+	select SYS_FSL_DDR
+	select SYS_FSL_DDR_LE
+	select SYS_FSL_DDR_VER_50
+	select SYS_FSL_ERRATUM_A009803
+	select SYS_FSL_ERRATUM_A009942
+	select SYS_FSL_ERRATUM_A010165
+	select SYS_FSL_ERRATUM_A008511
+	select SYS_FSL_ERRATUM_A008850
+	select SYS_FSL_HAS_CCI400
+	select SYS_FSL_HAS_DDR4
+	select SYS_FSL_HAS_SEC
+	select SYS_FSL_SEC_COMPAT_5
+	select SYS_FSL_SEC_LE
+	select SYS_FSL_SRDS_1
+	select SYS_FSL_SRDS_2
+	select FSL_TZASC_1
+	select ARCH_EARLY_INIT_R
+	select BOARD_EARLY_INIT_F
+
  config ARCH_LS2080A
  	bool
  	select ARMV8_SET_SMPEN
@@ -60,6 +83,7 @@ config ARCH_LS2080A
  	select SYS_FSL_DDR
  	select SYS_FSL_DDR_LE
  	select SYS_FSL_DDR_VER_50
+	select SYS_FSL_HAS_CCN504
  	select SYS_FSL_HAS_DP_DDR
  	select SYS_FSL_HAS_SEC
  	select SYS_FSL_HAS_DDR4
@@ -98,7 +122,7 @@ config FSL_LSCH3
 
  config FSL_MC_ENET
  	bool "Management Complex network"
-	depends on ARCH_LS2080A
+	depends on ARCH_LS2080A || ARCH_LS1088A
  	default y
  	select RESV_RAM
  	help

arch/arm/cpu/armv8/fsl-layerscape/Kconfig config FSL_PCIE_COMPAT · line 141

Quoted 4 lines

arch/arm/cpu/armv8/fsl-layerscape/Kconfig +1 -0

@@ -114,6 +138,7 @@ config FSL_PCIE_COMPAT
  	default "fsl,ls1043a-pcie" if ARCH_LS1043A
  	default "fsl,ls1046a-pcie" if ARCH_LS1046A
  	default "fsl,ls2080a-pcie" if ARCH_LS2080A
+	default "fsl,ls1080a-pcie" if ARCH_LS1088A

Did you intentionally use "ls1080a-pcie" here?

Quoted 40 lines

arch/arm/cpu/armv8/fsl-layerscape/Kconfig +7 -2

  	help
  	  This compatible is used to find pci controller node in Kernel DT
  	  to complete fixup.

@@ -228,6 +253,7 @@ config MAX_CPUS
  	default 4 if ARCH_LS1043A
  	default 4 if ARCH_LS1046A
  	default 16 if ARCH_LS2080A
+	default 8 if ARCH_LS1088A
  	default 1
  	help
  	  Set this number to the maximum number of possible CPUs in the SoC.

@@ -259,14 +285,17 @@ config SYS_CCI400_OFFSET
 
  config SYS_FSL_IFC_BANK_COUNT
  	int "Maximum banks of Integrated flash controller"
-	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
+	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
  	default 4 if ARCH_LS1043A
  	default 4 if ARCH_LS1046A
-	default 8 if ARCH_LS2080A
+	default 8 if ARCH_LS2080A || ARCH_LS1088A
 
  config SYS_FSL_HAS_CCI400
  	bool
 
+config SYS_FSL_HAS_CCN504
+	bool
+
  config SYS_FSL_HAS_DP_DDR
  	bool

@@ -308,6 +337,7 @@ config SYS_FSL_PCLK_DIV
  	int "Platform clock divider"
  	default 1 if ARCH_LS1043A
  	default 1 if ARCH_LS1046A
+	default 1 if ARCH_LS1088A
  	default 2
  	help
  	  This is the divider that is used to derive Platform clock from

arch/arm/cpu/armv8/fsl-layerscape/Kconfig config SYS_FSL_ERRATUM_A009929 · line 435

Quoted 6 lines

arch/arm/cpu/armv8/fsl-layerscape/Kconfig +2 -1

@@ -401,7 +431,8 @@ config SYS_FSL_ERRATUM_A009929
  config SYS_MC_RSV_MEM_ALIGN
  	hex "Management Complex reserved memory alignment"
  	depends on RESV_RAM
-	default 0x20000000
+	default 0x20000000 if ARCH_LS2080A
+	default 0x70000000 if ARCH_LS1088A

That's an odd alignment, isn't it? Are you sure about this?

Quoted 20 lines

arch/arm/cpu/armv8/fsl-layerscape/Kconfig +0 -0

  	help
  	  Reserved memory needs to be aligned for MC to use. Default value
  	  is 512MB.

arch/arm/cpu/armv8/fsl-layerscape/Makefile +4 -0

index e3ce018..115c3fc 100644
@@ -38,3 +38,7 @@ endif
  ifneq ($(CONFIG_ARCH_LS1046A),)
  obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
  endif
+
+ifneq ($(CONFIG_ARCH_LS1088A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o
+endif

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +0 -0

index ef97556..13def18 100644

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl) · line 35

Quoted 8 lines

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +5 -0

@@ -28,6 +28,11 @@ __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
  	return;
  }
 
+__weak int serdes_get_number(int serdes, int cfg)
+{
+	return cfg;
+}
+

What number does this function return? Can you put some comments here, especially you will override it somewhere later?

Quoted 27 lines

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +5 -0

  int is_serdes_configured(enum srds_prtcl device)
  {
  	int ret = 0;

@@ -73,6 +78,9 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
  		printf("invalid SerDes%d\n", sd);
  		break;
  	}
+
+	cfg = serdes_get_number(sd, cfg);
+
  	/* Is serdes enabled at all? */
  	if (cfg == 0)
  		return -ENODEV;

@@ -99,6 +107,8 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
 
  	cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
  	cfg >>= sd_prctl_shift;
+
+	cfg = serdes_get_number(sd, cfg);
  	printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
 
  	if (!is_serdes_prtcl_valid(sd, cfg))

arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +0 -0

index 3136e3f..d943f84 100644

arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S ENTRY(lowlevel_init) · line 79

Quoted 5 lines

arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +1 -1

@@ -76,7 +76,7 @@ ENTRY(lowlevel_init)
  	switch_el x1, 1f, 100f, 100f	/* skip if not in EL3 */
  1:
 
-#ifdef CONFIG_FSL_LSCH3
+#if defined(CONFIG_FSL_LSCH3) && defined (CONFIG_SYS_FSL_HAS_CCN504)

With the new CONFIG_SYS_FSL_HAS_CCN504, we don't need to check CONFIG_FSL_LSCH3. The code below is to deal with CCN504.

Quoted 14 lines

arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +2 -0

  	/* Set Wuo bit for RN-I 20 */
  #ifdef CONFIG_ARCH_LS2080A

@@ -338,7 +338,9 @@ get_svr:
  	ldr	x1, =FSL_LSCH3_SVR
  	ldr	w0, [x1]
  	ret
+#endif
 
+#ifdef CONFIG_SYS_FSL_HAS_CCN504
  hnf_pstate_poll:
  	/* x0 has the desired status, return 0 for success, 1 for timeout
  	 * clobber x1, x2, x3, x4, x6, x7

arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S ENTRY(__asm_flush_l3_dcache) · line 428

Quoted 8 lines

arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +1 -1

@@ -420,7 +422,7 @@ ENTRY(__asm_flush_l3_dcache)
  	mov	lr, x29
  	ret
  ENDPROC(__asm_flush_l3_dcache)
-#endif
+#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
 
  #ifdef CONFIG_MP
  	/* Keep literals not used by the secondary boot code outside it */

York

Prabhakar Kushwaha

2017-08-12 14:13 UTC #4 lore raw

PATCH v3 1/3 armv8: ls1088a: Add NXP LS1088A SoC support

In reply to Ashish Kumar

Quoted 64 lines

-----Original Message-----
From: Ashish Kumar [mailto:Ashish.Kumar at nxp.com]
Sent: Friday, August 11, 2017 12:54 PM
To: u-boot at lists.denx.de
Cc: York Sun <[email protected]>; Ashish Kumar <[email protected]>; Alison Wang <[email protected]>; Prabhakar Kushwaha <[email protected]>; Raghav Dogra <[email protected]>; Shaohui Xie <[email protected]>
Subject: [PATCH v3 1/3] armv8: ls1088a: Add NXP LS1088A SoC support
The QorIQ LS1088A processor is built on the Layerscape architecture combining eight ARM A53 processor cores with advanced, high-performance datapath acceleration and networks, peripheral interfaces required for networking, wireless infrastructure, and general-purpose embedded applications.
LS1088A is compliant to the Layerscape Chassis Generation 3.
Features summary:
- Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs
- Cores are in 2 cluster of 4-cores each
- Cache coherent interconnect (CCI-400)
- One 64-bit DDR4 SDRAM memory controller with ECC
- Data path acceleration architecture 2.0 (DPAA2)
- Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs
- QSPI, IFC, 3 PCIe, 1 SATA, 2 USB, 1 SDXC, 2 DUARTs etc
Signed-off-by Alison Wang <[email protected]>
Signed-off-by Prabhakar Kushwaha <[email protected]>
Signed-off-by Ashish Kumar <[email protected]>
Signed-off-by Raghav Dogra <[email protected]>
Signed-off-by Shaohui Xie <[email protected]>
---
v2:
Fix indentaion in commit msg
Separate RDB and Si specific file
Move Macros to Kconfig
v3:
1.Re-based on top of
commit d529124fdcf941c34074fd1ce600f4b1b4a7dd07
Merge: f0ca30f 6a5691e
Author: Tom Rini <[email protected]>
Date: Tue Aug 8 17:06:19 2017 -0400
    Merge git://git.denx.de/u-boot-x86
2.Incorporate review comments on v2
Clean up done
3.Migrate changes from ls1088ardb_stream_id.h to stream_id_lsch3.h
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig          |  39 ++++++-
 arch/arm/cpu/armv8/fsl-layerscape/Makefile         |   4 +
 .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c    |  10 ++
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S       |   6 +-
 arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 126
+++++++++++++++++++++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c            |   5 +
 arch/arm/dts/fsl-ls1088a.dtsi                      |  78 +++++++++++++
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |  62 +++++++++-

Quoted 8 lines

 arch/arm/include/asm/arch-fsl-layerscape/cpu.h     |   4 +
 .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |   3 +-
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  11 ++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h     |   4 +
 .../asm/arch-fsl-layerscape/stream_id_lsch3.h      |  14 +++
 drivers/ddr/fsl/util.c                             |   2 +-
 drivers/net/ldpaa_eth/Makefile                     |   1 +
 drivers/net/ldpaa_eth/ls1088a.c                    |  87 ++++++++++++++

Add SoC details in arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc

Quoted 170 lines

 16 files changed, 447 insertions(+), 9 deletions(-)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
 create mode 100644 arch/arm/dts/fsl-ls1088a.dtsi
 create mode 100644 drivers/net/ldpaa_eth/ls1088a.c

arch/arm/cpu/armv8/fsl-layerscape/Kconfig +28 -2

index 1132969..a3c7490 100644
@@ -49,6 +49,29 @@ config ARCH_LS1046A
 	select BOARD_EARLY_INIT_F
 	imply SCSI
 
+config ARCH_LS1088A
+	bool
+	select ARMV8_SET_SMPEN
+	select FSL_LSCH3
+	select SYS_FSL_DDR
+	select SYS_FSL_DDR_LE
+	select SYS_FSL_DDR_VER_50
+	select SYS_FSL_ERRATUM_A009803
+	select SYS_FSL_ERRATUM_A009942
+	select SYS_FSL_ERRATUM_A010165
+	select SYS_FSL_ERRATUM_A008511
+	select SYS_FSL_ERRATUM_A008850
+	select SYS_FSL_HAS_CCI400
+	select SYS_FSL_HAS_DDR4
+	select SYS_FSL_HAS_SEC
+	select SYS_FSL_SEC_COMPAT_5
+	select SYS_FSL_SEC_LE
+	select SYS_FSL_SRDS_1
+	select SYS_FSL_SRDS_2
+	select FSL_TZASC_1
+	select ARCH_EARLY_INIT_R
+	select BOARD_EARLY_INIT_F
+
 config ARCH_LS2080A
 	bool
 	select ARMV8_SET_SMPEN

@@ -60,6 +83,7 @@ config ARCH_LS2080A
 	select SYS_FSL_DDR
 	select SYS_FSL_DDR_LE
 	select SYS_FSL_DDR_VER_50
+	select SYS_FSL_HAS_CCN504
 	select SYS_FSL_HAS_DP_DDR
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_HAS_DDR4

@@ -98,7 +122,7 @@ config FSL_LSCH3
 
 config FSL_MC_ENET
 	bool "Management Complex network"
-	depends on ARCH_LS2080A
+	depends on ARCH_LS2080A || ARCH_LS1088A
 	default y
 	select RESV_RAM
 	help

@@ -114,6 +138,7 @@ config FSL_PCIE_COMPAT
 	default "fsl,ls1043a-pcie" if ARCH_LS1043A
 	default "fsl,ls1046a-pcie" if ARCH_LS1046A
 	default "fsl,ls2080a-pcie" if ARCH_LS2080A
+	default "fsl,ls1080a-pcie" if ARCH_LS1088A
 	help
 	  This compatible is used to find pci controller node in Kernel DT
 	  to complete fixup.

@@ -228,6 +253,7 @@ config MAX_CPUS
 	default 4 if ARCH_LS1043A
 	default 4 if ARCH_LS1046A
 	default 16 if ARCH_LS2080A
+	default 8 if ARCH_LS1088A
 	default 1
 	help
 	  Set this number to the maximum number of possible CPUs in the SoC.

@@ -259,14 +285,17 @@ config SYS_CCI400_OFFSET
 
 config SYS_FSL_IFC_BANK_COUNT
 	int "Maximum banks of Integrated flash controller"
-	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
+	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A ||

ARCH_LS1088A

arch/arm/cpu/armv8/fsl-layerscape/Kconfig +7 -2

 	default 4 if ARCH_LS1043A
 	default 4 if ARCH_LS1046A
-	default 8 if ARCH_LS2080A
+	default 8 if ARCH_LS2080A || ARCH_LS1088A
 
 config SYS_FSL_HAS_CCI400
 	bool
 
+config SYS_FSL_HAS_CCN504
+	bool
+
 config SYS_FSL_HAS_DP_DDR
 	bool

@@ -308,6 +337,7 @@ config SYS_FSL_PCLK_DIV
 	int "Platform clock divider"
 	default 1 if ARCH_LS1043A
 	default 1 if ARCH_LS1046A
+	default 1 if ARCH_LS1088A
 	default 2
 	help
 	  This is the divider that is used to derive Platform clock from

@@ -401,7 +431,8 @@ config SYS_FSL_ERRATUM_A009929
 config SYS_MC_RSV_MEM_ALIGN
 	hex "Management Complex reserved memory alignment"
 	depends on RESV_RAM
-	default 0x20000000
+	default 0x20000000 if ARCH_LS2080A
+	default 0x70000000 if ARCH_LS1088A
 	help
 	  Reserved memory needs to be aligned for MC to use. Default value
 	  is 512MB.

arch/arm/cpu/armv8/fsl-layerscape/Makefile +4 -0

index e3ce018..115c3fc 100644
@@ -38,3 +38,7 @@ endif
 ifneq ($(CONFIG_ARCH_LS1046A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
 endif
+
+ifneq ($(CONFIG_ARCH_LS1088A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o
+endif

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +5 -0

index ef97556..13def18 100644
@@ -28,6 +28,11 @@ __weak void wriop_init_dpmac_qsgmii(int sd, int
 lane_prtcl)
 	return;
 }
 
+__weak int serdes_get_number(int serdes, int cfg)
+{
+	return cfg;
+}
+
 int is_serdes_configured(enum srds_prtcl device)
 {

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +5 -0

 	int ret = 0;

@@ -73,6 +78,9 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 		printf("invalid SerDes%d\n", sd);
 		break;
 	}
+
+	cfg = serdes_get_number(sd, cfg);
+
 	/* Is serdes enabled at all? */
 	if (cfg == 0)
 		return -ENODEV;

@@ -99,6 +107,8 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32
 sd_prctl_mask,
 
 	cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
 	cfg >>= sd_prctl_shift;
+
+	cfg = serdes_get_number(sd, cfg);
 	printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +0 -0

 	if (!is_serdes_prtcl_valid(sd, cfg))

arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +0 -0

index 3136e3f..d943f84 100644

arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S ENTRY(lowlevel_init) · line 80

Quoted 6 lines

arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +1 -1

@@ -76,7 +76,7 @@ ENTRY(lowlevel_init)
 	switch_el x1, 1f, 100f, 100f	/* skip if not in EL3 */
 1:
 
-#ifdef CONFIG_FSL_LSCH3
+#if defined(CONFIG_FSL_LSCH3) && defined (CONFIG_SYS_FSL_HAS_CCN504)

Is it possible to put patch having CONFIG_SYS_FSL_HAS_CCN504 defined and then SoC patch

Quoted 183 lines

arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +3 -1

 	/* Set Wuo bit for RN-I 20 */
 #ifdef CONFIG_ARCH_LS2080A

@@ -338,7 +338,9 @@ get_svr:
 	ldr	x1, =FSL_LSCH3_SVR
 	ldr	w0, [x1]
 	ret
+#endif
 
+#ifdef CONFIG_SYS_FSL_HAS_CCN504
 hnf_pstate_poll:
 	/* x0 has the desired status, return 0 for success, 1 for timeout
 	 * clobber x1, x2, x3, x4, x6, x7

@@ -420,7 +422,7 @@ ENTRY(__asm_flush_l3_dcache)
 	mov	lr, x29
 	ret
 ENDPROC(__asm_flush_l3_dcache)
-#endif
+#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
 
 #ifdef CONFIG_MP
 	/* Keep literals not used by the secondary boot code outside it */

arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c new file +126 -0

new file mode 100644
index 0000000..9f5cdd5
@@ -0,0 +1,126 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+
+struct serdes_config {
+	u8 ip_protocol;
+	u8 lanes[SRDS_MAX_LANES];
+	u8 rcw_lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+	/* SerDes 1 */
+	{0x12, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 3, 3 }  },
+	{0x15, {SGMII3, SGMII7, XFI1, XFI2 }, {3, 3, 1, 1 } },
+	{0x16, {SGMII3, SGMII7, SGMII1, XFI2 }, {3, 3, 3, 1 } },
+	{0x17, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 3, 2 } },
+	{0x18, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 2, 2 } },
+	{0x19, {SGMII3, QSGMII_B, XFI1, XFI2}, {3, 4, 1, 1 } },
+	{0x1A, {SGMII3, QSGMII_B, SGMII1, XFI2 }, {3, 4, 3, 1 } },
+	{0x1B, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 3, 2 } },
+	{0x1C, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 2, 2 } },
+	{0x1D, {QSGMII_A, QSGMII_B, XFI1, XFI2 }, {4, 4, 1, 1 } },
+	{0x1E, {QSGMII_A, QSGMII_B, SGMII1, XFI2  }, {4, 4, 3, 1 } },
+	{0x1F, {QSGMII_A, QSGMII_B, SGMII1, SGMII2  }, {4, 4, 3, 2 } },
+	{0x20, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 2, 2 } },
+	{0x35, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 3, 3 } },
+	{0x36, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 3, 3 } },
+	{0x3A, {SGMII3, PCIE1, SGMII1, SGMII2 }, {3, 5, 3, 3 } },
+		{}
+};
+static struct serdes_config serdes2_cfg_tbl[] = {
+	/* SerDes 2 */
+	{0x0C, {PCIE1, PCIE1, PCIE1, PCIE1 }, {8, 8, 8, 8 } },
+	{0x0D, {PCIE1, PCIE2, PCIE3, SATA1 }, {5, 5, 5, 9 }  },
+	{0x0E, {PCIE1, PCIE1, PCIE2, SATA1 }, {7, 7, 6, 9 }  },
+	{0x13, {PCIE1, PCIE1, PCIE3, PCIE3 }, {7, 7, 7, 7 }  },
+	{0x14, {PCIE1, PCIE2, PCIE3, PCIE3 }, {5, 5, 7, 7 }  },
+	{0x3C, {NONE, PCIE2, NONE, PCIE3 }, {0, 5, 0, 6 }  },
+	{}
+};
+
+static struct serdes_config *serdes_cfg_tbl[] = {
+	serdes1_cfg_tbl,
+	serdes2_cfg_tbl,
+};
+
+int serdes_get_number(int serdes, int cfg)
+{
+	struct serdes_config *ptr;
+	int i, j, index, lnk;
+	int is_found, max_lane = SRDS_MAX_LANES;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+
+	while (ptr->ip_protocol) {
+		is_found = 1;
+		for (i = 0, j = max_lane - 1; i < max_lane; i++, j--) {
+			lnk = cfg & (0xf << 4 * i);
+			lnk = lnk >> (4 * i);
+
+			index = (serdes == FSL_SRDS_1) ? j : i;
+
+			if (ptr->rcw_lanes[index] == lnk && is_found)
+				is_found = 1;
+			else
+				is_found = 0;
+		}
+
+		if (is_found)
+			return ptr->ip_protocol;
+		ptr++;
+	}
+
+	return 0;
+}
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->ip_protocol) {
+		if (ptr->ip_protocol == cfg)
+			return ptr->lanes[lane];
+		ptr++;
+	}
+
+	return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+	int i;
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->ip_protocol) {
+		if (ptr->ip_protocol == prtcl)
+			break;
+		ptr++;
+	}
+
+	if (!ptr->ip_protocol)
+		return 0;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (ptr->lanes[i] != NONE)
+			return 1;
+	}
+
+	return 0;
+}

arch/arm/cpu/armv8/fsl-layerscape/soc.c +4 -0

index ddb7d82..18820f6 100644
@@ -24,6 +24,7 @@
 #ifdef CONFIG_CHAIN_OF_TRUST
 #include <fsl_validate.h>
 #endif
+#include <fsl_immap.h>
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -215,11 +216,14 @@ int sata_init(void)
 {
 	struct ccsr_ahci __iomem *ccsr_ahci;
 
+#ifdef CONFIG_SYS_SATA2
 	ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
 	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
 	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
 	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
+#endif
 
+#ifdef CONFIG_SYS_SATA1
 	ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
 	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
 	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);

arch/arm/cpu/armv8/fsl-layerscape/soc.c int sata_init(void) · line 235

Quoted 5 lines

arch/arm/cpu/armv8/fsl-layerscape/soc.c +1 -0

@@ -227,6 +231,7 @@ int sata_init(void)
 
 	ahci_init((void __iomem *)CONFIG_SYS_SATA1);
 	scsi_scan(false);
+#endif

CONFIG_SYS_SATA2, CONFIG_SYS_SATA1 should be separate patch. It should not part of SoC patch set.

Quoted 149 lines

arch/arm/cpu/armv8/fsl-layerscape/soc.c +0 -0

 	return 0;
 }

arch/arm/dts/fsl-ls1088a.dtsi new file +24 -0

new file mode 100644
index 0000000..421d2de
@@ -0,0 +1,78 @@
+/*
+ * NXP ls1088a SOC common device tree source
+ *
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/ {
+	compatible = "fsl,ls1088a";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	memory at 80000000 {
+		device_type = "memory";
+		reg = <0x00000000 0x80000000 0 0x80000000>;
+		      /* DRAM space - 1, size : 2 GB DRAM */
+	};
+
+	gic: interrupt-controller at 6000000 {
+		compatible = "arm,gic-v3";
+		reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
+		      <0x0 0x06100000 0 0x100000>; /* GICR (RD_base +

SGI_base) */

arch/arm/dts/fsl-ls1088a.dtsi new file +9 -0

+		#interrupt-cells = <3>;
+		interrupt-controller;
+		interrupts = <1 9 0x4>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
+			     <1 14 0x8>, /* Physical Non-Secure PPI, active-low

arch/arm/dts/fsl-ls1088a.dtsi new file +45 -0

+			     <1 11 0x8>, /* Virtual PPI, active-low */
+			     <1 10 0x8>; /* Hypervisor PPI, active-low */
+	};
+
+	serial0: serial at 21c0500 {
+		device_type = "serial";
+		compatible = "fsl,ns16550", "ns16550a";
+		reg = <0x0 0x21c0500 0x0 0x100>;
+		clock-frequency = <0>;	/* Updated by bootloader */
+		interrupts = <0 32 0x1>; /* edge triggered */
+	};
+
+	serial1: serial at 21c0600 {
+		device_type = "serial";
+		compatible = "fsl,ns16550", "ns16550a";
+		reg = <0x0 0x21c0600 0x0 0x100>;
+		clock-frequency = <0>; 	/* Updated by bootloader */
+		interrupts = <0 32 0x1>; /* edge triggered */
+	};
+
+	fsl_mc: fsl-mc at 80c000000 {
+		compatible = "fsl,qoriq-mc";
+		reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
+		      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
+	};
+
+	dspi: dspi at 2100000 {
+		compatible = "fsl,vf610-dspi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2100000 0x0 0x10000>;
+		interrupts = <0 26 0x4>; /* Level high type */
+		num-cs = <6>;
+	};
+
+	qspi: quadspi at 1550000 {
+		compatible = "fsl,vf610-qspi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x20c0000 0x0 0x10000>,
+			<0x0 0x20000000 0x0 0x10000000>;
+		reg-names = "QuadSPI", "QuadSPI-memory";
+		num-cs = <4>;
+	};
+};

arch/arm/include/asm/arch-fsl-layerscape/config.h +51 -0

index 79e94f9..a7098be 100644
@@ -116,6 +116,67 @@
 #define CONFIG_SYS_FSL_ERRATUM_A008751
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
+
+#elif defined(CONFIG_ARCH_LS1088A)
+#define CONFIG_SYS_FSL_NUM_CC_PLLS		3
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1 }
+#define CONFIG_GICV3
+#define CONFIG_FSL_TZPC_BP147
+#define CONFIG_FSL_TZASC_400
+#define CONFIG_SYS_PAGE_SIZE		0x10000
+
+#define	SRDS_MAX_LANES	4
+
+/* TZ Protection Controller Definitions */
+#define TZPC_BASE				0x02200000
+#define TZPCR0SIZE_BASE				(TZPC_BASE)
+#define TZPCDECPROT_0_STAT_BASE			(TZPC_BASE + 0x800)
+#define TZPCDECPROT_0_SET_BASE			(TZPC_BASE + 0x804)
+#define TZPCDECPROT_0_CLR_BASE			(TZPC_BASE + 0x808)
+#define TZPCDECPROT_1_STAT_BASE			(TZPC_BASE + 0x80C)
+#define TZPCDECPROT_1_SET_BASE			(TZPC_BASE + 0x810)
+#define TZPCDECPROT_1_CLR_BASE			(TZPC_BASE + 0x814)
+#define TZPCDECPROT_2_STAT_BASE			(TZPC_BASE + 0x818)
+#define TZPCDECPROT_2_SET_BASE			(TZPC_BASE + 0x81C)
+#define TZPCDECPROT_2_CLR_BASE			(TZPC_BASE + 0x820)
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE			0x06000000
+#define GICR_BASE			0x06100000
+
+/* SMMU Defintions */
+#define SMMU_BASE			0x05000000 /* GR0 Base */
+
+/* DDR */
+#define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED
 	CONFIG_SYS_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+#define CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define CONFIG_SYS_FSL_ESDHC_LE
+#define CONFIG_SYS_FSL_IFC_LE
+#define CONFIG_SYS_FSL_PEX_LUT_LE
+
+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+
+/* SFP */
+#define CONFIG_SYS_FSL_SFP_VER_3_4
+#define CONFIG_SYS_FSL_SFP_LE
+#define CONFIG_SYS_FSL_SRK_LE
+
+/* Security Monitor */
+#define CONFIG_SYS_FSL_SEC_MON_LE
+

arch/arm/include/asm/arch-fsl-layerscape/config.h line 180

Quoted 10 lines

arch/arm/include/asm/arch-fsl-layerscape/config.h +10 -0

+/* Secure Boot */
+#define CONFIG_ESBC_HDR_LS
+
+/* DCFG - GUR */
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	1
+#define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000 /* initial RAM */
+#define SYS_FSL_OCRAM_SPACE_SIZE	0x00200000 /* 2M space */
+#define CONFIG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */
+

Are these offset different than LS2080A, if not move these definition to common place to avoid repetition. .

--prabhakar