Skip to contentSkip to conversation

Terasic DE0 NANO-SoC: add support

PATCH Superseded Tim Sander 5 participants 12 messages Feb 1, 2016 – Feb 2, 2016

Subsystems (4)
Arm (32-bit) Arm sub-architectures Arm/actions semi architecture Arm/socfpga architecture

v1 of 7 Superseded Latest is v7 →

lore
Share & tools
lore

Tim Sander

author
#0 lore raw

PATCH 1/1 Terasic DE0 NANO-SoC: add support

Below is a Patch for supporting the Terasic DE0 NANO-SoC with barebox. The pretty similar Socrates Board was taken as a starting point with pulling in the memory timings/pinmux from
http://rocketboards.org/foswiki/view/Documentation/AtlasSoCCompileHardwareDesign
Its only tested at room temperatures and i am not 100% sure about the device tree:
One known problem is the fact that the board identifier is pretty generic but its the same in the linux kernel so i resorted to that.

Signed-off-by Tim Sander <[email protected]>
---
 arch/arm/boards/Makefile                           |   1 +
 arch/arm/boards/terasic-de0-nano-soc/Makefile      |   2 +
 arch/arm/boards/terasic-de0-nano-soc/board.c       |  37 ++
 arch/arm/boards/terasic-de0-nano-soc/config.h      |   1 +
 .../terasic-de0-nano-soc/iocsr_config_cyclone5.c   | 675 +++++++++++++++++++++
 arch/arm/boards/terasic-de0-nano-soc/lowlevel.c    | 102 ++++
 .../boards/terasic-de0-nano-soc/pinmux_config.c    | 240 ++++++++
 arch/arm/boards/terasic-de0-nano-soc/pll_config.h  | 107 ++++
 .../arm/boards/terasic-de0-nano-soc/sdram_config.h | 108 ++++
 .../boards/terasic-de0-nano-soc/sequencer_auto.h   | 228 +++++++
 .../terasic-de0-nano-soc/sequencer_auto_ac_init.c  |  69 +++
 .../sequencer_auto_inst_init.c                     | 161 +++++
 .../terasic-de0-nano-soc/sequencer_defines.h       | 160 +++++
 arch/arm/configs/socfpga-xload_defconfig           |   1 +
 arch/arm/configs/socfpga_defconfig                 |   1 +
 arch/arm/dts/Makefile                              |   1 +
 arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts     | 136 +++++
 arch/arm/mach-socfpga/Kconfig                      |   4 +
 images/Makefile.socfpga                            |   8 +
 19 files changed, 2042 insertions(+)
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/Makefile
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/board.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/config.h
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/lowlevel.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/pll_config.h
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sdram_config.h
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sequencer_auto.h
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_inst_init.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sequencer_defines.h
 create mode 100644 arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
arch/arm/boards/Makefile +1 -0
index 2e58f15f3533..1813d5f673fe 100644
@@ -106,6 +106,7 @@ obj-$(CONFIG_MACH_SAMA5D4EK)                        += sama5d4ek/
 obj-$(CONFIG_MACH_SCB9328)                     += scb9328/
 obj-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK)                += altera-socdk/
 obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES)                += ebv-socrates/
+obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC)        += terasic-de0-nano-soc/
 obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT)      += terasic-sockit/
 obj-$(CONFIG_MACH_SOLIDRUN_CUBOX)              += solidrun-cubox/
 obj-$(CONFIG_MACH_SOLIDRUN_MICROSOM)           += solidrun-microsom/
arch/arm/boards/terasic-de0-nano-soc/Makefile new file +2 -0
new file mode 100644
index 000000000000..8c927fe291a6
@@ -0,0 +1,2 @@
+obj-y += lowlevel.o board.o
+pbl-y += lowlevel.o
arch/arm/boards/terasic-de0-nano-soc/board.c new file +37 -0
new file mode 100644
index 000000000000..22f8291b3069
@@ -0,0 +1,37 @@
+#include <common.h>
+#include <types.h>
+#include <driver.h>
+#include <init.h>
+#include <asm/armlinux.h>
+#include <linux/micrel_phy.h>
+#include <linux/phy.h>
+#include <linux/sizes.h>
+#include <fcntl.h>
+#include <fs.h>
+#include <mach/socfpga-regs.h>
+
+static int phy_fixup(struct phy_device *dev)
+{
+       /* min rx data delay */
+       phy_write(dev, 0x0b, 0x8105);
+       phy_write(dev, 0x0c, 0x0000);
+
+       /* max rx/tx clock delay, min rx/tx control delay */
+       phy_write(dev, 0x0b, 0x8104);
+       phy_write(dev, 0x0c, 0xa0d0);
+       phy_write(dev, 0x0b, 0x104);
+
+       return 0;
+}
+
+static int socfpga_console_init(void)
+{
+       if (!of_machine_is_compatible("altr,socfpga-cyclone5"))
+               return 0;
+
+       if (IS_ENABLED(CONFIG_PHYLIB))
+               phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, phy_fixup);
+
+       return 0;
+}
+console_initcall(socfpga_console_init);
arch/arm/boards/terasic-de0-nano-soc/config.h new file +1 -0
new file mode 100644
index 000000000000..da84fa5f6b78
@@ -0,0 +1 @@
+/* nothing */
arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c new file +675 -0

675 lines not on this page · raw message

arch/arm/boards/terasic-de0-nano-soc/lowlevel.c new file +102 -0

102 lines not on this page · raw message

arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c new file +240 -0

240 lines not on this page · raw message

arch/arm/boards/terasic-de0-nano-soc/pll_config.h new file +107 -0

107 lines not on this page · raw message

arch/arm/boards/terasic-de0-nano-soc/sdram_config.h new file +108 -0

108 lines not on this page · raw message

arch/arm/boards/terasic-de0-nano-soc/sequencer_auto.h new file +228 -0

228 lines not on this page · raw message

arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c new file +69 -0

69 lines not on this page · raw message

arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_inst_init.c new file +161 -0

161 lines not on this page · raw message

arch/arm/boards/terasic-de0-nano-soc/sequencer_defines.h new file +160 -0

160 lines not on this page · raw message

arch/arm/configs/socfpga-xload_defconfig +1 -0
index 9f64adfd7438..1f4d74d95c42 100644
@@ -1,6 +1,7 @@
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_ARCH_SOCFPGA_XLOAD=y
 CONFIG_MACH_SOCFPGA_EBV_SOCRATES=y
+CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC=y
 CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT=y
 CONFIG_THUMB2_BAREBOX=y
 # CONFIG_CMD_ARM_CPUINFO is not set
arch/arm/configs/socfpga_defconfig +1 -0
index 0a31de518d64..cf019c93e1c0 100644
@@ -1,6 +1,7 @@
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_MACH_SOCFPGA_EBV_SOCRATES=y
 CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT=y
+CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC=y
 CONFIG_THUMB2_BAREBOX=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_ARM_UNWIND=y
arch/arm/dts/Makefile +1 -0
index 2da930eb9108..1a1a4197902b 100644
@@ -57,6 +57,7 @@ pbl-dtb-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o
 pbl-dtb-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += imx6sx-sdb.dtb.o
 pbl-dtb-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += socfpga_cyclone5_socdk.dtb.o
 pbl-dtb-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o
+pbl-dtb-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += socfpga_cyclone5_de0_nano_soc.dtb.o
 pbl-dtb-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o
 pbl-dtb-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox-bb.dtb.o
 pbl-dtb-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o imx6q-hummingboard.dtb.o
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +136 -0

136 lines not on this page · raw message

arch/arm/mach-socfpga/Kconfig +4 -0
index 73b26efd2031..94689e3ecd02 100644
@@ -20,6 +20,10 @@ config MACH_SOCFPGA_EBV_SOCRATES
        select HAVE_DEFAULT_ENVIRONMENT_NEW
        bool "EBV Socrates"
 
+config MACH_SOCFPGA_TERASIC_DE0_NANO_SOC
+       select HAVE_DEFAULT_ENVIRONMENT_NEW
+       bool "Terasic DE0-NANO-SoC aka Atlas"
+
 config MACH_SOCFPGA_TERASIC_SOCKIT
        select HAVE_DEFAULT_ENVIRONMENT_NEW
        bool "Terasic SoCKit"
images/Makefile.socfpga +8 -0
index f295c673ad02..3c7d850af5f9 100644
@@ -19,6 +19,14 @@ pblx-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += start_socfpga_socdk
 FILE_barebox-socfpga-socdk.img = start_socfpga_socdk.pblx
 socfpga-barebox-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += barebox-socfpga-socdk.img
 
+pblx-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += start_socfpga_de0_nano_soc_xload
+FILE_barebox-socfpga-de0_nano_soc-xload.img = start_socfpga_de0_nano_soc_xload.pblx.socfpgaimg
+socfpga-xload-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += barebox-socfpga-de0_nano_soc-xload.img
+
+pblx-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += start_socfpga_de0_nano_soc
+FILE_barebox-socfpga-de0_nano_soc.img = start_socfpga_de0_nano_soc.pblx
+socfpga-barebox-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += barebox-socfpga-de0_nano_soc.img
+
 pblx-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += start_socfpga_sockit_xload
 FILE_barebox-socfpga-sockit-xload.img = start_socfpga_sockit_xload.pblx.socfpgaimg
 socfpga-xload-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += barebox-socfpga-sockit-xload.img
Signature · 7 lines
1.9.1


_______________________________________________
barebox mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/barebox
#1 lore raw
Quoted 44 lines · Tim Sander

Below is a Patch for supporting the Terasic DE0 NANO-SoC with barebox. The pretty similar Socrates Board was taken as a starting point with pulling in the memory timings/pinmux from
http://rocketboards.org/foswiki/view/Documentation/AtlasSoCCompileHardwareDesign
Its only tested at room temperatures and i am not 100% sure about the device tree:
One known problem is the fact that the board identifier is pretty generic but its the same in the linux kernel so i resorted to that.

Signed-off-by Tim Sander <[email protected]>
---
 arch/arm/boards/Makefile                           |   1 +
 arch/arm/boards/terasic-de0-nano-soc/Makefile      |   2 +
 arch/arm/boards/terasic-de0-nano-soc/board.c       |  37 ++
 arch/arm/boards/terasic-de0-nano-soc/config.h      |   1 +
 .../terasic-de0-nano-soc/iocsr_config_cyclone5.c   | 675 +++++++++++++++++++++
 arch/arm/boards/terasic-de0-nano-soc/lowlevel.c    | 102 ++++
 .../boards/terasic-de0-nano-soc/pinmux_config.c    | 240 ++++++++
 arch/arm/boards/terasic-de0-nano-soc/pll_config.h  | 107 ++++
 .../arm/boards/terasic-de0-nano-soc/sdram_config.h | 108 ++++
 .../boards/terasic-de0-nano-soc/sequencer_auto.h   | 228 +++++++
 .../terasic-de0-nano-soc/sequencer_auto_ac_init.c  |  69 +++
 .../sequencer_auto_inst_init.c                     | 161 +++++
 .../terasic-de0-nano-soc/sequencer_defines.h       | 160 +++++
 arch/arm/configs/socfpga-xload_defconfig           |   1 +
 arch/arm/configs/socfpga_defconfig                 |   1 +
 arch/arm/dts/Makefile                              |   1 +
 arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts     | 136 +++++
 arch/arm/mach-socfpga/Kconfig                      |   4 +
 images/Makefile.socfpga                            |   8 +
 19 files changed, 2042 insertions(+)
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/Makefile
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/board.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/config.h
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/lowlevel.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/pll_config.h
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sdram_config.h
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sequencer_auto.h
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_inst_init.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sequencer_defines.h
 create mode 100644 arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts

(...)

Quoted 14 lines
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +8 -0
new file mode 100644
index 000000000000..5d1840451382
@@ -0,0 +1,136 @@
+/*
+ *  Copyright (C) 2013 Steffen Trumtrar <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *

arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts line 18

Quoted 10 lines
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +10 -0
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <arm/socfpga_cyclone5_sockit.dts>

This is the wrong DT.
What you AFAIK want is the socfgpa_cyclone5_de0_sockit.dts

The "Terasic DE0-Nano" is the same as the "Terasic DE-0" or isn't it? From the website it at least seems like it.

With the other dts you then should be able to remove

Quoted 15 lines
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +15 -0
+#include "socfpga.dtsi"
+
+/ {
+       model = "Terasic DE0-Nano(Atlas)";
+       compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+       chosen {
+               stdout-path = &uart0;
+       };
+
+       leds: gpio-leds {
+       };
+
+       buttons: gpio-keys {
+       };

arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts line 43

Quoted 10 lines
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +10 -0
+};
+
+&gpio1 {
+       status = "okay";
+};
+
+&gpio2 {
+       status = "okay";
+};
+

the gpio nodes. The leds phandle should go in the upstream linux DT, too, so it could be used here. As long as it isn't, this looks okay IMHO.

Quoted 64 lines
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +64 -0
+&leds {
+       compatible = "gpio-leds";
+
+       led@0 {
+               label = "0";
+               gpios = <&portb 24 0>;
+               linux,default-trigger = "heartbeat";
+       };
+
+       led@1 {
+               label = "1";
+               gpios = <&portb 25 0>;
+       };
+
+       led@2 {
+               label = "2";
+               gpios = <&portb 26 0>;
+       };
+
+       led@3 {
+               label = "3";
+               gpios = <&portb 27 0>;
+       };
+};
+
+&buttons {
+       compatible = "gpio-keys";
+
+        key@0 {
+               label = "F1";
+               gpios = <&portc 21 0>;
+               linux,code = <59>;
+       };
+
+        key@1 {
+               label = "F2";
+               gpios = <&portc 22 0>;
+               linux,code = <60>;
+       };
+
+        key@2 {
+               label = "F3";
+               gpios = <&portc 23 0>;
+               linux,code = <61>;
+       };
+
+        key@3 {
+               label = "F4";
+               gpios = <&portc 24 0>;
+               linux,code = <62>;
+       };
+};
+
+&i2c0 {
+       status = "disabled";
+
+       eeprom@51 {
+               compatible = "atmel,24c32";
+               reg = <0x51>;
+               pagesize = <0x20>;
+       };
+};
+
+&i2c1 {

arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts line 117

Quoted 10 lines
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +10 -0
+       status = "disabled";
+
+       adxl345@53 {
+               compatible = "adi,adxl34x";
+               reg = <0x53>;
+               interrupt-parent = <0x2>;
+               interrupts = <0x0 0xa6 0x4>;
+       };
+};
+

This looks to be correct in the upstream de0 dts and can also be removed here.

Quoted 9 lines
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +9 -0
+&qspi {
+       status = "okay";
+
+       flash: flash@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "n25q00";
+               reg = <0>;
+               spi-max-frequency = <108000000>;

arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts line 136

Quoted 10 lines
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +10 -0
+               m25p,fast-read;
+               cdns,page-size = <256>;
+               cdns,block-size = <16>;
+               cdns,read-delay = <4>;
+               cdns,tshsl-ns = <50>;
+               cdns,tsd2d-ns = <50>;
+               cdns,tchsh-ns = <4>;
+               cdns,tslch-ns = <4>;
+       };
+};

Regards,
Steffen

Signature · 9 lines
Pengutronix e.K.                           | Steffen Trumtrar            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
barebox mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/barebox
#2 lore raw
Quoted 81 lines · On Mon, 01 Feb 2016 13:06:22 +0100 Steffen Trumtrar…
Quoted 44 lines · Tim Sander

Below is a Patch for supporting the Terasic DE0 NANO-SoC with barebox. The pretty similar Socrates Board was taken as a starting point with pulling in the memory timings/pinmux from
http://rocketboards.org/foswiki/view/Documentation/AtlasSoCCompileHardwareDesign
Its only tested at room temperatures and i am not 100% sure about the device tree:
One known problem is the fact that the board identifier is pretty generic but its the same in the linux kernel so i resorted to that.

Signed-off-by Tim Sander <[email protected]>
---
 arch/arm/boards/Makefile                           |   1 +
 arch/arm/boards/terasic-de0-nano-soc/Makefile      |   2 +
 arch/arm/boards/terasic-de0-nano-soc/board.c       |  37 ++
 arch/arm/boards/terasic-de0-nano-soc/config.h      |   1 +
 .../terasic-de0-nano-soc/iocsr_config_cyclone5.c   | 675 +++++++++++++++++++++
 arch/arm/boards/terasic-de0-nano-soc/lowlevel.c    | 102 ++++
 .../boards/terasic-de0-nano-soc/pinmux_config.c    | 240 ++++++++
 arch/arm/boards/terasic-de0-nano-soc/pll_config.h  | 107 ++++
 .../arm/boards/terasic-de0-nano-soc/sdram_config.h | 108 ++++
 .../boards/terasic-de0-nano-soc/sequencer_auto.h   | 228 +++++++
 .../terasic-de0-nano-soc/sequencer_auto_ac_init.c  |  69 +++
 .../sequencer_auto_inst_init.c                     | 161 +++++
 .../terasic-de0-nano-soc/sequencer_defines.h       | 160 +++++
 arch/arm/configs/socfpga-xload_defconfig           |   1 +
 arch/arm/configs/socfpga_defconfig                 |   1 +
 arch/arm/dts/Makefile                              |   1 +
 arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts     | 136 +++++
 arch/arm/mach-socfpga/Kconfig                      |   4 +
 images/Makefile.socfpga                            |   8 +
 19 files changed, 2042 insertions(+)
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/Makefile
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/board.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/config.h
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/lowlevel.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/pll_config.h
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sdram_config.h
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sequencer_auto.h
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_inst_init.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sequencer_defines.h
 create mode 100644 arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts

(...)

Quoted 14 lines
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +8 -0
new file mode 100644
index 000000000000..5d1840451382
@@ -0,0 +1,136 @@
+/*
+ *  Copyright (C) 2013 Steffen Trumtrar <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *

arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts line 18

Quoted 10 lines
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +10 -0
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <arm/socfpga_cyclone5_sockit.dts>

This is the wrong DT.
What you AFAIK want is the socfgpa_cyclone5_de0_sockit.dts

The "Terasic DE0-Nano" is the same as the "Terasic DE-0" or isn't it? From the website it at least seems like it.

Quoted 6 lines

With the other dts you then should be able to remove

arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts line 22

Quoted 4 lines
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +4 -0
+#include "socfpga.dtsi"
+
+/ {
+       model = "Terasic DE0-Nano(Atlas)";

It looks like Steffen is right.

The board model name is wrong.

Here is the DE0-Nano-SoC (Atlas-SoC) board:
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=941
it is based on Cyclone V SE 5CSEMA4U23C6N.

And this is DE0-Nano
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593
it is based on Cyclone IV EP4CE22F17C6N.

--
Best regards,
  Antony Pavlov

_______________________________________________
barebox mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/barebox

author
#3 lore raw

Am Montag, 1. Februar 2016, 15:48:03 schrieb Antony Pavlov:

Quoted 87 lines

On Mon, 01 Feb 2016 13:06:22 +0100

Quoted 84 lines · Steffen Trumtrar
Quoted 49 lines · Tim Sander

Below is a Patch for supporting the Terasic DE0 NANO-SoC with barebox. The pretty similar Socrates Board was taken as a starting point with pulling in the memory timings/pinmux from
http://rocketboards.org/foswiki/view/Documentation/AtlasSoCCompileHardwa
reDesign> >
Its only tested at room temperatures and i am not 100% sure about the device tree:
One known problem is the fact that the board identifier is pretty generic but its the same in the linux kernel so i resorted to that.

Signed-off-by Tim Sander <[email protected]>

---

 arch/arm/boards/Makefile                           |   1 +
 arch/arm/boards/terasic-de0-nano-soc/Makefile      |   2 +
 arch/arm/boards/terasic-de0-nano-soc/board.c       |  37 ++
 arch/arm/boards/terasic-de0-nano-soc/config.h      |   1 +
 .../terasic-de0-nano-soc/iocsr_config_cyclone5.c   | 675
 +++++++++++++++++++++ arch/arm/boards/terasic-de0-nano-soc/lowlevel.c 
   | 102 ++++
 .../boards/terasic-de0-nano-soc/pinmux_config.c    | 240 ++++++++
 arch/arm/boards/terasic-de0-nano-soc/pll_config.h  | 107 ++++
 .../arm/boards/terasic-de0-nano-soc/sdram_config.h | 108 ++++
 .../boards/terasic-de0-nano-soc/sequencer_auto.h   | 228 +++++++
 .../terasic-de0-nano-soc/sequencer_auto_ac_init.c  |  69 +++
 .../sequencer_auto_inst_init.c                     | 161 +++++
 .../terasic-de0-nano-soc/sequencer_defines.h       | 160 +++++
 arch/arm/configs/socfpga-xload_defconfig           |   1 +
 arch/arm/configs/socfpga_defconfig                 |   1 +
 arch/arm/dts/Makefile                              |   1 +
 arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts     | 136 +++++
 arch/arm/mach-socfpga/Kconfig                      |   4 +
 images/Makefile.socfpga                            |   8 +
 19 files changed, 2042 insertions(+)
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/Makefile
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/board.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/config.h
 create mode 100644
 arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c create
 mode 100644 arch/arm/boards/terasic-de0-nano-soc/lowlevel.c create
 mode 100644 arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/pll_config.h
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sdram_config.h
 create mode 100644
 arch/arm/boards/terasic-de0-nano-soc/sequencer_auto.h create mode
 100644 arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c
 create mode 100644
 arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_inst_init.c create
 mode 100644 arch/arm/boards/terasic-de0-nano-soc/sequencer_defines.h
 create mode 100644 arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts

(...)

Quoted 23 lines
(quoted diff) +0 -0

b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file mode 100644 index 000000000000..5d1840451382

arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +15 -0
@@ -0,0 +1,136 @@
+/*
+ *  Copyright (C) 2013 Steffen Trumtrar <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see

<http://www.gnu.org/licenses/>.
+ */

arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts line 18

Quoted 2 lines
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +2 -0
+
+#include <arm/socfpga_cyclone5_sockit.dts>

This is the wrong DT.
What you AFAIK want is the socfgpa_cyclone5_de0_sockit.dts

The "Terasic DE0-Nano" is the same as the "Terasic DE-0" or isn't it? From the website it at least seems like it.

According to the DE0-Nano-SoC_QSG.pdf document:
"Whats the difference between the DE0-Nano-SoC kit and the Atlas-SoC kit?

The hardware is the same for the DE0-Nano-SoC kit and the Atlas-SoC kit. The only difference is the getting-started process for the two kits. Users can freely use the DE0-Nano-SoC kit resources on the Atlas-SoC kit and vice versa."

Quoted 6 lines
Quoted 6 lines

With the other dts you then should be able to remove

arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts line 22

Quoted 4 lines
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +4 -0
+#include "socfpga.dtsi"
+
+/ {
+       model = "Terasic DE0-Nano(Atlas)";

So with that it would be more precise to name it DE0-Nano-SoC (Atlas)?
It would be than different to that in the linux kernel?
But then was up till now not aware that there is a DE0-Nano, a DE0-CV and a DE0 board.
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=56&No=364
But the only one with a processor is AFAIK the DE0-Nano-SoC.

Quoted 7 lines

It looks like Steffen is right.

The board model name is wrong.

Here is the DE0-Nano-SoC (Atlas-SoC) board:
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=941
it is based on Cyclone V SE 5CSEMA4U23C6N.

Its this board i am talking of.

Quoted 4 lines

And this is DE0-Nano
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryN
o=139&No=593 it is based on Cyclone IV EP4CE22F17C6N.

There is no processor in here, so you have a hard time booting this with barebox (at least without a softcore processor).

Will do the other suggested dts changes suggested by Steffen.

Best regards
Tim

_______________________________________________
barebox mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/barebox

#4 lore raw
Quoted 98 lines · Tim Sander

Am Montag, 1. Februar 2016, 15:48:03 schrieb Antony Pavlov:

Quoted 87 lines

On Mon, 01 Feb 2016 13:06:22 +0100

Quoted 84 lines · Steffen Trumtrar
Quoted 49 lines · Tim Sander

Below is a Patch for supporting the Terasic DE0 NANO-SoC with barebox. The pretty similar Socrates Board was taken as a starting point with pulling in the memory timings/pinmux from
http://rocketboards.org/foswiki/view/Documentation/AtlasSoCCompileHardwa
reDesign> >
Its only tested at room temperatures and i am not 100% sure about the device tree:
One known problem is the fact that the board identifier is pretty generic but its the same in the linux kernel so i resorted to that.

Signed-off-by Tim Sander <[email protected]>

---

 arch/arm/boards/Makefile                           |   1 +
 arch/arm/boards/terasic-de0-nano-soc/Makefile      |   2 +
 arch/arm/boards/terasic-de0-nano-soc/board.c       |  37 ++
 arch/arm/boards/terasic-de0-nano-soc/config.h      |   1 +
 .../terasic-de0-nano-soc/iocsr_config_cyclone5.c   | 675
 +++++++++++++++++++++ arch/arm/boards/terasic-de0-nano-soc/lowlevel.c 
   | 102 ++++
 .../boards/terasic-de0-nano-soc/pinmux_config.c    | 240 ++++++++
 arch/arm/boards/terasic-de0-nano-soc/pll_config.h  | 107 ++++
 .../arm/boards/terasic-de0-nano-soc/sdram_config.h | 108 ++++
 .../boards/terasic-de0-nano-soc/sequencer_auto.h   | 228 +++++++
 .../terasic-de0-nano-soc/sequencer_auto_ac_init.c  |  69 +++
 .../sequencer_auto_inst_init.c                     | 161 +++++
 .../terasic-de0-nano-soc/sequencer_defines.h       | 160 +++++
 arch/arm/configs/socfpga-xload_defconfig           |   1 +
 arch/arm/configs/socfpga_defconfig                 |   1 +
 arch/arm/dts/Makefile                              |   1 +
 arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts     | 136 +++++
 arch/arm/mach-socfpga/Kconfig                      |   4 +
 images/Makefile.socfpga                            |   8 +
 19 files changed, 2042 insertions(+)
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/Makefile
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/board.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/config.h
 create mode 100644
 arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c create
 mode 100644 arch/arm/boards/terasic-de0-nano-soc/lowlevel.c create
 mode 100644 arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/pll_config.h
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sdram_config.h
 create mode 100644
 arch/arm/boards/terasic-de0-nano-soc/sequencer_auto.h create mode
 100644 arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c
 create mode 100644
 arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_inst_init.c create
 mode 100644 arch/arm/boards/terasic-de0-nano-soc/sequencer_defines.h
 create mode 100644 arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts

(...)

Quoted 23 lines
(quoted diff) +0 -0

b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file mode 100644 index 000000000000..5d1840451382

arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +15 -0
@@ -0,0 +1,136 @@
+/*
+ *  Copyright (C) 2013 Steffen Trumtrar <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see

<http://www.gnu.org/licenses/>.
+ */

arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts line 18

Quoted 2 lines
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +2 -0
+
+#include <arm/socfpga_cyclone5_sockit.dts>

This is the wrong DT.
What you AFAIK want is the socfgpa_cyclone5_de0_sockit.dts

The "Terasic DE0-Nano" is the same as the "Terasic DE-0" or isn't it? From the website it at least seems like it.

According to the DE0-Nano-SoC_QSG.pdf document:
"Whats the difference between the DE0-Nano-SoC kit and the Atlas-SoC kit?

The hardware is the same for the DE0-Nano-SoC kit and the Atlas-SoC kit. The only difference is the getting-started process for the two kits. Users can freely use the DE0-Nano-SoC kit resources on the Atlas-SoC kit and vice versa."

Quoted 2 lines
Quoted 2 lines

With the other dts you then should be able to remove

Quoted 7 lines
Quoted 4 lines
Quoted 4 lines

arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts line 22

Quoted 4 lines
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +4 -0
+#include "socfpga.dtsi"
+
+/ {
+       model = "Terasic DE0-Nano(Atlas)";

So with that it would be more precise to name it DE0-Nano-SoC (Atlas)? It would be than different to that in the linux kernel?

IIRC Dinh, who did the dts, initially started with an even more confusing naming and ended with this.
It seems reasonable to me, to fix the model name in linux to match the dts name, i.e. "DE0-Nano-SoC". I don't know how the "Atlas" fits in there though.

Regards,
Steffen

Signature · 9 lines
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
barebox mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/barebox
author
#5 lore raw

Hi Steffen

Am Montag, 1. Februar 2016, 14:03:39 schrieb Steffen Trumtrar:
(...)

Quoted 26 lines
Quoted 26 lines
Quoted 26 lines
Quoted 26 lines
Quoted 26 lines
(quoted diff) +0 -0

b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file mode 100644
index 000000000000..5d1840451382

arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +4 -0
@@ -0,0 +1,136 @@
+/*
+ *  Copyright (C) 2013 Steffen Trumtrar <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or

modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License

Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines

arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts line 18

Quoted 5 lines

+ * along with this program. If not, see
<http://www.gnu.org/licenses/>.
+ */

arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +2 -0
+
+#include <arm/socfpga_cyclone5_sockit.dts>

This is the wrong DT.
What you AFAIK want is the socfgpa_cyclone5_de0_sockit.dts

This one is not beeing found. Did you mean socfpga_cyclone5_de0_nano_soc.dts. Which is also not there. I do *think* that the Sockit board has a similar layout. So i deliberately choose this file. Should i copy and adapt this file?

Quoted 21 lines
Quoted 13 lines
Quoted 2 lines
Quoted 2 lines

The "Terasic DE0-Nano" is the same as the "Terasic DE-0" or isn't it? From the website it at least seems like it.

According to the DE0-Nano-SoC_QSG.pdf document:
"Whats the difference between the DE0-Nano-SoC kit and the Atlas-SoC kit?

The hardware is the same for the DE0-Nano-SoC kit and the Atlas-SoC kit. The only difference is the getting-started process for the two kits. Users can freely use the DE0-Nano-SoC kit resources on the Atlas-SoC kit and vice versa."

Quoted 2 lines
Quoted 2 lines

With the other dts you then should be able to remove

Quoted 7 lines
Quoted 4 lines
Quoted 4 lines

arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts line 22

Quoted 4 lines
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +4 -0
+#include "socfpga.dtsi"
+
+/ {
+       model = "Terasic DE0-Nano(Atlas)";

So with that it would be more precise to name it DE0-Nano-SoC (Atlas)? It would be than different to that in the linux kernel?

Quoted 5 lines

IIRC Dinh, who did the dts, initially started with an even more confusing naming and ended with this.
It seems reasonable to me, to fix the model name in linux to match the dts name, i.e. "DE0-Nano-SoC". I don't know how the "Atlas" fits in there though.

The Atlas part is just plain weird. But if someone is grepping for Atlas support its at least nice to have it in there.

Best regards
Tim

_______________________________________________
barebox mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/barebox

#6 lore raw
Quoted 38 lines · Tim Sander

Hi Steffen

Am Montag, 1. Februar 2016, 14:03:39 schrieb Steffen Trumtrar:
(...)

Quoted 26 lines
Quoted 26 lines
Quoted 26 lines
Quoted 26 lines
Quoted 26 lines
(quoted diff) +0 -0

b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file mode 100644
index 000000000000..5d1840451382

arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +4 -0
@@ -0,0 +1,136 @@
+/*
+ *  Copyright (C) 2013 Steffen Trumtrar <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or

modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License

Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines

arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts line 18

Quoted 5 lines

+ * along with this program. If not, see
<http://www.gnu.org/licenses/>.
+ */

arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +2 -0
+
+#include <arm/socfpga_cyclone5_sockit.dts>

This is the wrong DT.
What you AFAIK want is the socfgpa_cyclone5_de0_sockit.dts

Quoted 3 lines

This one is not beeing found. Did you mean socfpga_cyclone5_de0_nano_soc.dts. Which is also not there. I do *think* that the Sockit board has a similar layout. So i deliberately choose this file. Should i copy and adapt this file?

Current master: dts/src/arm/socfpga_cyclone5_de0_sockit.dts

Quoted 5 lines
Quoted 5 lines

IIRC Dinh, who did the dts, initially started with an even more confusing naming and ended with this.
It seems reasonable to me, to fix the model name in linux to match the dts name, i.e. "DE0-Nano-SoC". I don't know how the "Atlas" fits in there though.

Seems I got confused with all the names. So, the dts is called socfpga_cyclone5_de0_sockit.dts and the model name is "Terasic DE-0(Atlas)" and Terasic calls it "DE0-Nano-SoC Kit/Atlas-SoC Kit".

I think it should then be

	model = "Terasic DE0-Nano-SoC Kit/Atlas-SoC Kit";

I didn't insist on that when I reviewed the dts for linux, maybe I should have.

Steffen

Signature · 9 lines
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
barebox mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/barebox
author
#7 lore raw

PATCH v2 1/1 Terasic DE0-Nano-SoC: add support

A Patch for supporting the Terasic DE0 NANO-SoC with barebox.
The pretty similar Socrates Board was taken as a starting point with pulling in the memory timings/pinmux from
http://rocketboards.org/foswiki/view/Documentation/AtlasSoCCompileHardwareDesign
Its only tested at room temperatures and i am not 100% sure about the device tree:
One known problem is the fact that the board identifier is pretty generic but its the same in the linux kernel so i resorted to that.

Signed-off-by Tim Sander <[email protected]>
---
 arch/arm/boards/Makefile                           |   1 +
 arch/arm/boards/terasic-de0-nano-soc/Makefile      |   2 +
 arch/arm/boards/terasic-de0-nano-soc/board.c       |  37 ++
 arch/arm/boards/terasic-de0-nano-soc/config.h      |   1 +
 .../terasic-de0-nano-soc/iocsr_config_cyclone5.c   | 675 +++++++++++++++++++++
 arch/arm/boards/terasic-de0-nano-soc/lowlevel.c    | 102 ++++
 .../boards/terasic-de0-nano-soc/pinmux_config.c    | 240 ++++++++
 arch/arm/boards/terasic-de0-nano-soc/pll_config.h  | 107 ++++
 .../arm/boards/terasic-de0-nano-soc/sdram_config.h | 108 ++++
 .../boards/terasic-de0-nano-soc/sequencer_auto.h   | 228 +++++++
 .../terasic-de0-nano-soc/sequencer_auto_ac_init.c  |  69 +++
 .../sequencer_auto_inst_init.c                     | 161 +++++
 .../terasic-de0-nano-soc/sequencer_defines.h       | 160 +++++
 arch/arm/configs/socfpga-xload_defconfig           |   1 +
 arch/arm/configs/socfpga_defconfig                 |   1 +
 arch/arm/dts/Makefile                              |   1 +
 arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts     | 136 +++++
 arch/arm/mach-socfpga/Kconfig                      |   4 +
 images/Makefile.socfpga                            |   8 +
 19 files changed, 2042 insertions(+)
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/Makefile
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/board.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/config.h
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/lowlevel.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/pll_config.h
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sdram_config.h
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sequencer_auto.h
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_inst_init.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sequencer_defines.h
 create mode 100644 arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
arch/arm/boards/Makefile +1 -0
index 1029e8f..4d572a6 100644
@@ -106,6 +106,7 @@ obj-$(CONFIG_MACH_SAMA5D4EK)                        += sama5d4ek/
 obj-$(CONFIG_MACH_SCB9328)                     += scb9328/
 obj-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK)                += altera-socdk/
 obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES)                += ebv-socrates/
+obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC)        += terasic-de0-nano-soc/
 obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT)      += terasic-sockit/
 obj-$(CONFIG_MACH_SOLIDRUN_CUBOX)              += solidrun-cubox/
 obj-$(CONFIG_MACH_SOLIDRUN_MICROSOM)           += solidrun-microsom/
arch/arm/boards/terasic-de0-nano-soc/Makefile new file +2 -0
new file mode 100644
index 0000000..8c927fe
@@ -0,0 +1,2 @@
+obj-y += lowlevel.o board.o
+pbl-y += lowlevel.o
arch/arm/boards/terasic-de0-nano-soc/board.c new file +37 -0
new file mode 100644
index 0000000..22f8291
@@ -0,0 +1,37 @@
+#include <common.h>
+#include <types.h>
+#include <driver.h>
+#include <init.h>
+#include <asm/armlinux.h>
+#include <linux/micrel_phy.h>
+#include <linux/phy.h>
+#include <linux/sizes.h>
+#include <fcntl.h>
+#include <fs.h>
+#include <mach/socfpga-regs.h>
+
+static int phy_fixup(struct phy_device *dev)
+{
+       /* min rx data delay */
+       phy_write(dev, 0x0b, 0x8105);
+       phy_write(dev, 0x0c, 0x0000);
+
+       /* max rx/tx clock delay, min rx/tx control delay */
+       phy_write(dev, 0x0b, 0x8104);
+       phy_write(dev, 0x0c, 0xa0d0);
+       phy_write(dev, 0x0b, 0x104);
+
+       return 0;
+}
+
+static int socfpga_console_init(void)
+{
+       if (!of_machine_is_compatible("altr,socfpga-cyclone5"))
+               return 0;
+
+       if (IS_ENABLED(CONFIG_PHYLIB))
+               phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, phy_fixup);
+
+       return 0;
+}
+console_initcall(socfpga_console_init);
arch/arm/boards/terasic-de0-nano-soc/config.h new file +1 -0
new file mode 100644
index 0000000..da84fa5
@@ -0,0 +1 @@
+/* nothing */
arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c new file +675 -0

675 lines not on this page · raw message

arch/arm/boards/terasic-de0-nano-soc/lowlevel.c new file +102 -0

102 lines not on this page · raw message

arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c new file +240 -0

240 lines not on this page · raw message

arch/arm/boards/terasic-de0-nano-soc/pll_config.h new file +107 -0

107 lines not on this page · raw message

arch/arm/boards/terasic-de0-nano-soc/sdram_config.h new file +108 -0

108 lines not on this page · raw message

arch/arm/boards/terasic-de0-nano-soc/sequencer_auto.h new file +228 -0

228 lines not on this page · raw message

arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c new file +69 -0

69 lines not on this page · raw message

arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_inst_init.c new file +161 -0

161 lines not on this page · raw message

arch/arm/boards/terasic-de0-nano-soc/sequencer_defines.h new file +160 -0

160 lines not on this page · raw message

arch/arm/configs/socfpga-xload_defconfig +1 -0
index 9f64adf..1f4d74d 100644
@@ -1,6 +1,7 @@
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_ARCH_SOCFPGA_XLOAD=y
 CONFIG_MACH_SOCFPGA_EBV_SOCRATES=y
+CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC=y
 CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT=y
 CONFIG_THUMB2_BAREBOX=y
 # CONFIG_CMD_ARM_CPUINFO is not set
arch/arm/configs/socfpga_defconfig +1 -0
index 7fbe045..6cbc28e 100644
@@ -1,6 +1,7 @@
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_MACH_SOCFPGA_EBV_SOCRATES=y
 CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT=y
+CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC=y
 CONFIG_THUMB2_BAREBOX=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_ARM_UNWIND=y
arch/arm/dts/Makefile +1 -0
index 2da930e..1a1a419 100644
@@ -57,6 +57,7 @@ pbl-dtb-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o
 pbl-dtb-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += imx6sx-sdb.dtb.o
 pbl-dtb-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += socfpga_cyclone5_socdk.dtb.o
 pbl-dtb-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o
+pbl-dtb-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += socfpga_cyclone5_de0_nano_soc.dtb.o
 pbl-dtb-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o
 pbl-dtb-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox-bb.dtb.o
 pbl-dtb-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o imx6q-hummingboard.dtb.o
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +136 -0

136 lines not on this page · raw message

arch/arm/mach-socfpga/Kconfig +4 -0
index 73b26ef..94689e3 100644
@@ -20,6 +20,10 @@ config MACH_SOCFPGA_EBV_SOCRATES
        select HAVE_DEFAULT_ENVIRONMENT_NEW
        bool "EBV Socrates"
 
+config MACH_SOCFPGA_TERASIC_DE0_NANO_SOC
+       select HAVE_DEFAULT_ENVIRONMENT_NEW
+       bool "Terasic DE0-NANO-SoC aka Atlas"
+
 config MACH_SOCFPGA_TERASIC_SOCKIT
        select HAVE_DEFAULT_ENVIRONMENT_NEW
        bool "Terasic SoCKit"
images/Makefile.socfpga +8 -0
index f295c67..3c7d850 100644
@@ -19,6 +19,14 @@ pblx-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += start_socfpga_socdk
 FILE_barebox-socfpga-socdk.img = start_socfpga_socdk.pblx
 socfpga-barebox-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += barebox-socfpga-socdk.img
 
+pblx-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += start_socfpga_de0_nano_soc_xload
+FILE_barebox-socfpga-de0_nano_soc-xload.img = start_socfpga_de0_nano_soc_xload.pblx.socfpgaimg
+socfpga-xload-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += barebox-socfpga-de0_nano_soc-xload.img
+
+pblx-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += start_socfpga_de0_nano_soc
+FILE_barebox-socfpga-de0_nano_soc.img = start_socfpga_de0_nano_soc.pblx
+socfpga-barebox-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += barebox-socfpga-de0_nano_soc.img
+
 pblx-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += start_socfpga_sockit_xload
 FILE_barebox-socfpga-sockit-xload.img = start_socfpga_sockit_xload.pblx.socfpgaimg
 socfpga-xload-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += barebox-socfpga-sockit-xload.img
Signature · 6 lines
1.9.1

_______________________________________________
barebox mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/barebox
author
#8 lore raw

PATCH v3 1/1 Terasic DE0-Nano-SoC: add support

v3: forgot to amend my changes in v2.

A Patch for supporting the Terasic DE0 NANO-SoC with barebox.
The pretty similar Socrates Board was taken as a starting point with pulling in the memory timings/pinmux from
http://rocketboards.org/foswiki/view/Documentation/AtlasSoCCompileHardwareDesign
Its only tested at room temperatures and i am not 100% sure about the device tree:
One known problem is the fact that the board identifier is pretty generic but its the same in the linux kernel so i resorted to that.

Signed-off-by Tim Sander <[email protected]>
---
 arch/arm/boards/Makefile                           |   1 +
 arch/arm/boards/terasic-de0-nano-soc/Makefile      |   2 +
 arch/arm/boards/terasic-de0-nano-soc/board.c       |  37 ++
 arch/arm/boards/terasic-de0-nano-soc/config.h      |   1 +
 .../terasic-de0-nano-soc/iocsr_config_cyclone5.c   | 675 +++++++++++++++++++++
 arch/arm/boards/terasic-de0-nano-soc/lowlevel.c    | 102 ++++
 .../boards/terasic-de0-nano-soc/pinmux_config.c    | 240 ++++++++
 arch/arm/boards/terasic-de0-nano-soc/pll_config.h  | 107 ++++
 .../arm/boards/terasic-de0-nano-soc/sdram_config.h | 108 ++++
 .../boards/terasic-de0-nano-soc/sequencer_auto.h   | 228 +++++++
 .../terasic-de0-nano-soc/sequencer_auto_ac_init.c  |  69 +++
 .../sequencer_auto_inst_init.c                     | 161 +++++
 .../terasic-de0-nano-soc/sequencer_defines.h       | 160 +++++
 arch/arm/configs/socfpga-xload_defconfig           |   1 +
 arch/arm/configs/socfpga_defconfig                 |   1 +
 arch/arm/dts/Makefile                              |   1 +
 arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts     | 136 +++++
 arch/arm/mach-socfpga/Kconfig                      |   4 +
 images/Makefile.socfpga                            |   8 +
 19 files changed, 2042 insertions(+)
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/Makefile
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/board.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/config.h
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/lowlevel.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/pll_config.h
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sdram_config.h
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sequencer_auto.h
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_inst_init.c
 create mode 100644 arch/arm/boards/terasic-de0-nano-soc/sequencer_defines.h
 create mode 100644 arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
arch/arm/boards/Makefile +1 -0
index 1029e8f..4d572a6 100644
@@ -106,6 +106,7 @@ obj-$(CONFIG_MACH_SAMA5D4EK)                        += sama5d4ek/
 obj-$(CONFIG_MACH_SCB9328)                     += scb9328/
 obj-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK)                += altera-socdk/
 obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES)                += ebv-socrates/
+obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC)        += terasic-de0-nano-soc/
 obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT)      += terasic-sockit/
 obj-$(CONFIG_MACH_SOLIDRUN_CUBOX)              += solidrun-cubox/
 obj-$(CONFIG_MACH_SOLIDRUN_MICROSOM)           += solidrun-microsom/
arch/arm/boards/terasic-de0-nano-soc/Makefile new file +2 -0
new file mode 100644
index 0000000..8c927fe
@@ -0,0 +1,2 @@
+obj-y += lowlevel.o board.o
+pbl-y += lowlevel.o
arch/arm/boards/terasic-de0-nano-soc/board.c new file +37 -0
new file mode 100644
index 0000000..22f8291
@@ -0,0 +1,37 @@
+#include <common.h>
+#include <types.h>
+#include <driver.h>
+#include <init.h>
+#include <asm/armlinux.h>
+#include <linux/micrel_phy.h>
+#include <linux/phy.h>
+#include <linux/sizes.h>
+#include <fcntl.h>
+#include <fs.h>
+#include <mach/socfpga-regs.h>
+
+static int phy_fixup(struct phy_device *dev)
+{
+       /* min rx data delay */
+       phy_write(dev, 0x0b, 0x8105);
+       phy_write(dev, 0x0c, 0x0000);
+
+       /* max rx/tx clock delay, min rx/tx control delay */
+       phy_write(dev, 0x0b, 0x8104);
+       phy_write(dev, 0x0c, 0xa0d0);
+       phy_write(dev, 0x0b, 0x104);
+
+       return 0;
+}
+
+static int socfpga_console_init(void)
+{
+       if (!of_machine_is_compatible("altr,socfpga-cyclone5"))
+               return 0;
+
+       if (IS_ENABLED(CONFIG_PHYLIB))
+               phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, phy_fixup);
+
+       return 0;
+}
+console_initcall(socfpga_console_init);
arch/arm/boards/terasic-de0-nano-soc/config.h new file +1 -0
new file mode 100644
index 0000000..da84fa5
@@ -0,0 +1 @@
+/* nothing */
arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c new file +675 -0

675 lines not on this page · raw message

arch/arm/boards/terasic-de0-nano-soc/lowlevel.c new file +102 -0

102 lines not on this page · raw message

arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c new file +240 -0

240 lines not on this page · raw message

arch/arm/boards/terasic-de0-nano-soc/pll_config.h new file +107 -0

107 lines not on this page · raw message

arch/arm/boards/terasic-de0-nano-soc/sdram_config.h new file +108 -0

108 lines not on this page · raw message

arch/arm/boards/terasic-de0-nano-soc/sequencer_auto.h new file +228 -0

228 lines not on this page · raw message

arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c new file +69 -0

69 lines not on this page · raw message

arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_inst_init.c new file +161 -0

161 lines not on this page · raw message

arch/arm/boards/terasic-de0-nano-soc/sequencer_defines.h new file +160 -0

160 lines not on this page · raw message

arch/arm/configs/socfpga-xload_defconfig +1 -0
index 9f64adf..1f4d74d 100644
@@ -1,6 +1,7 @@
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_ARCH_SOCFPGA_XLOAD=y
 CONFIG_MACH_SOCFPGA_EBV_SOCRATES=y
+CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC=y
 CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT=y
 CONFIG_THUMB2_BAREBOX=y
 # CONFIG_CMD_ARM_CPUINFO is not set
arch/arm/configs/socfpga_defconfig +1 -0
index 7fbe045..6cbc28e 100644
@@ -1,6 +1,7 @@
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_MACH_SOCFPGA_EBV_SOCRATES=y
 CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT=y
+CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC=y
 CONFIG_THUMB2_BAREBOX=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_ARM_UNWIND=y
arch/arm/dts/Makefile +1 -0
index 2da930e..1a1a419 100644
@@ -57,6 +57,7 @@ pbl-dtb-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o
 pbl-dtb-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += imx6sx-sdb.dtb.o
 pbl-dtb-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += socfpga_cyclone5_socdk.dtb.o
 pbl-dtb-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o
+pbl-dtb-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += socfpga_cyclone5_de0_nano_soc.dtb.o
 pbl-dtb-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o
 pbl-dtb-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox-bb.dtb.o
 pbl-dtb-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o imx6q-hummingboard.dtb.o
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +136 -0

136 lines not on this page · raw message

arch/arm/mach-socfpga/Kconfig +4 -0
index 73b26ef..94689e3 100644
@@ -20,6 +20,10 @@ config MACH_SOCFPGA_EBV_SOCRATES
        select HAVE_DEFAULT_ENVIRONMENT_NEW
        bool "EBV Socrates"
 
+config MACH_SOCFPGA_TERASIC_DE0_NANO_SOC
+       select HAVE_DEFAULT_ENVIRONMENT_NEW
+       bool "Terasic DE0-NANO-SoC aka Atlas"
+
 config MACH_SOCFPGA_TERASIC_SOCKIT
        select HAVE_DEFAULT_ENVIRONMENT_NEW
        bool "Terasic SoCKit"
images/Makefile.socfpga +8 -0
index f295c67..3c7d850 100644
@@ -19,6 +19,14 @@ pblx-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += start_socfpga_socdk
 FILE_barebox-socfpga-socdk.img = start_socfpga_socdk.pblx
 socfpga-barebox-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += barebox-socfpga-socdk.img
 
+pblx-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += start_socfpga_de0_nano_soc_xload
+FILE_barebox-socfpga-de0_nano_soc-xload.img = start_socfpga_de0_nano_soc_xload.pblx.socfpgaimg
+socfpga-xload-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += barebox-socfpga-de0_nano_soc-xload.img
+
+pblx-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += start_socfpga_de0_nano_soc
+FILE_barebox-socfpga-de0_nano_soc.img = start_socfpga_de0_nano_soc.pblx
+socfpga-barebox-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += barebox-socfpga-de0_nano_soc.img
+
 pblx-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += start_socfpga_sockit_xload
 FILE_barebox-socfpga-sockit-xload.img = start_socfpga_sockit_xload.pblx.socfpgaimg
 socfpga-xload-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += barebox-socfpga-sockit-xload.img
Signature · 6 lines
1.9.1

_______________________________________________
barebox mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/barebox
#9 lore raw

Re: [PATCH v3] Terasic DE0-Nano-SoC: add support

arch/arm/boards/terasic-de0-nano-soc/board.c line 30

Quoted 7 lines · Tim Sander

v3: forgot to amend my changes in v2.

arch/arm/boards/terasic-de0-nano-soc/board.c new file +5 -0
+
+static int socfpga_console_init(void)
+{
+       if (!of_machine_is_compatible("altr,socfpga-cyclone5"))
+               return 0;

Seems like this should be a board specific check instead of a generic one, since it's programming board specific phy timing values to a board specific PHY.

Quoted 5 lines
arch/arm/boards/terasic-de0-nano-soc/lowlevel.c new file +5 -0
+
+       if (IS_ENABLED(CONFIG_PHYLIB))
+               phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, phy_fixup);
+
+       return 0;

arch/arm/boards/terasic-de0-nano-soc/lowlevel.c line 27

Quoted 10 lines
arch/arm/boards/terasic-de0-nano-soc/lowlevel.c new file +9 -0
+}
 
+
+static inline void ledon(int led)
+{
+       u32 val;
+
+       val = readl(0xFF709000);
+       val |= 1 << (led + 24);
+       writel(val, 0xFF709000);

There a macro CYCLONE5_GPIO1_BASE that could be used instead of 0xFF709000.

Quoted 16 lines
arch/arm/boards/terasic-de0-nano-soc/lowlevel.c new file +16 -0
+
+       val = readl(0xFF709004);
+       val |= 1 << (led + 24);
+       writel(val, 0xFF709004);
+}
+
+static inline void ledoff(int led)
+{
+       u32 val;
+
+       val = readl(0xFF709000);
+       val &= ~(1 << (led + 24));
+       writel(val, 0xFF709000);
+
+       val = readl(0xFF709004);
+       val &= ~(1 << (led + 24));

arch/arm/boards/terasic-de0-nano-soc/lowlevel.c

Quoted 10 lines
arch/arm/boards/terasic-de0-nano-soc/lowlevel.c new file +8 -0
+       writel(val, 0xFF709004);
+}
 
 
+#include <arm/socfpga_cyclone5_de0_nano_soc.dts>
+#include "socfpga.dtsi"
+
+/ {
+       model = "Terasic DE0-Nano-SoC (Atlas)";
+       compatible = "altr,socfpga-cyclone5", "altr,socfpga";

Wouldn't the right thing to do here be to have a compatible entry for this board type? Like the existing "terasic,sockit" or something more specific.
_______________________________________________
barebox mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/barebox

author
#10 lore raw

Re: [PATCH v3] Terasic DE0-Nano-SoC: add support

Quoted 4 lines · On Monday 01 February 2016 19:31:53 Trent Piepho wrote:
Quoted 2 lines · Tim Sander

v3: forgot to amend my changes in v2.

Quoted 10 lines

arch/arm/boards/terasic-de0-nano-soc/board.c line 30

Quoted 5 lines
arch/arm/boards/terasic-de0-nano-soc/board.c new file +5 -0
+
+static int socfpga_console_init(void)
+{
+       if (!of_machine_is_compatible("altr,socfpga-cyclone5"))
+               return 0;

Seems like this should be a board specific check instead of a generic one, since it's programming board specific phy timing values to a board specific PHY.

I am not sure, but as outlined below i think this is also due to the compatible string of the coresponding dts within the linux kernel. At least i first tried a more specific dts compatible string and that failed to boot.

Quoted 5 lines
Quoted 5 lines
arch/arm/boards/terasic-de0-nano-soc/board.c new file +3 -0
+
+       if (IS_ENABLED(CONFIG_PHYLIB))
+               phy_register_fixup_for_uid(PHY_ID_KSZ9021,

MICREL_PHY_ID_MASK, phy_fixup);

+

Quoted 41 lines

arch/arm/boards/terasic-de0-nano-soc/lowlevel.c line 27

Quoted 13 lines
arch/arm/boards/terasic-de0-nano-soc/lowlevel.c new file +10 -0
+       return 0;
+}
 
 
 
+
+static inline void ledon(int led)
+{
+       u32 val;
+
+       val = readl(0xFF709000);
+       val |= 1 << (led + 24);
+       writel(val, 0xFF709000);

There a macro CYCLONE5_GPIO1_BASE that could be used instead of 0xFF709000.

Quoted 18 lines
arch/arm/boards/terasic-de0-nano-soc/lowlevel.c new file +18 -0
+
+       val = readl(0xFF709004);
+       val |= 1 << (led + 24);
+       writel(val, 0xFF709004);
+}
+
+static inline void ledoff(int led)
+{
+       u32 val;
+
+       val = readl(0xFF709000);
+       val &= ~(1 << (led + 24));
+       writel(val, 0xFF709000);
+
+       val = readl(0xFF709004);
+       val &= ~(1 << (led + 24));
+       writel(val, 0xFF709004);
+}
Quoted 11 lines

arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts line 23

Quoted 6 lines
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +6 -0
+#include <arm/socfpga_cyclone5_de0_nano_soc.dts>
+#include "socfpga.dtsi"
+
+/ {
+       model = "Terasic DE0-Nano-SoC (Atlas)";
+       compatible = "altr,socfpga-cyclone5", "altr,socfpga";

Wouldn't the right thing to do here be to have a compatible entry for this board type? Like the existing "terasic,sockit" or something more specific.

Well the problem at this point is that due to the boardspecs the compatible string has to be AFAIK the same as the one used in the linux kernel. Unfortunatly the coresponding dts file also has no more specific compatible string.

Best regards
Tim

_______________________________________________
barebox mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/barebox

#11 lore raw

Re: [PATCH v3] Terasic DE0-Nano-SoC: add support

Hi Tim,

Quoted 15 lines · Tim Sander
Quoted 4 lines · On Monday 01 February 2016 19:31:53 Trent Piepho wrote:
Quoted 2 lines · Tim Sander

v3: forgot to amend my changes in v2.

Quoted 10 lines

arch/arm/boards/terasic-de0-nano-soc/board.c line 30

Quoted 5 lines
arch/arm/boards/terasic-de0-nano-soc/board.c new file +5 -0
+
+static int socfpga_console_init(void)
+{
+       if (!of_machine_is_compatible("altr,socfpga-cyclone5"))
+               return 0;

Seems like this should be a board specific check instead of a generic one, since it's programming board specific phy timing values to a board specific PHY.

Quoted 4 lines

I am not sure, but as outlined below i think this is also due to the compatible string of the coresponding dts within the linux kernel. At least i first tried a more specific dts compatible string and that failed to boot.

You need to match for a board specific compatible here because this function shall be executed for this board only, not for other boards. This means you have to add a board specific compatible to the device tree.

Quoted 11 lines
Quoted 11 lines

arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts line 23

Quoted 6 lines
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file +6 -0
+#include <arm/socfpga_cyclone5_de0_nano_soc.dts>
+#include "socfpga.dtsi"
+
+/ {
+       model = "Terasic DE0-Nano-SoC (Atlas)";
+       compatible = "altr,socfpga-cyclone5", "altr,socfpga";

Wouldn't the right thing to do here be to have a compatible entry for this board type? Like the existing "terasic,sockit" or something more specific.

Quoted 4 lines

Well the problem at this point is that due to the boardspecs the compatible string has to be AFAIK the same as the one used in the linux kernel. Unfortunatly the coresponding dts file also has no more specific compatible string.

The kernel matches for "altr,socfpga". You can add as many compatibles before that as you like, just like the "altr,socfpga-cyclone5" string which is present already and ignored by the kernel.

Sascha

Signature · 9 lines
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
barebox mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/barebox