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Lattice MachXO2 Slave SPI FPGA Manager support

PATCH Superseded Paolo Pisati 3 participants 7 messages Mar 16, 2018 – Mar 19, 2018

Subsystems (2)
Device tree bindings FPGA manager framework

v6 of 10 Superseded Latest is v10 →

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Paolo Pisati

author
#0 lore raw

v6 cover Lattice MachXO2 Slave SPI FPGA Manager support

Hi all,
this series adds support for the Lattice MachXO2 FPGA chip, programmed over Slave SPI.

Tested on a raspberry pi3, beaglebone black (little endian mode) and imx6 hummingboard (big endian mode) + bugblat's pif2 fpga hat (machxo2 7000HC) or tinyfpga A1/A2 (machxo2 256HC / 1200HC), in SPI slave mode with varying bus speed.

Changes since v5:
* fixed all the endianess issues
* introduced a cleanup() path invoked in case of flash failure
* moved back machxo2_write() to use a spi_sync() transaction per line write (in v5 i queued all the spi_write()s and executed a single spi_sync() at the end, but that, sometimes, resulted in the REFRESH command to fail with a CMD_ERR, depending on the SPI bus speed)

Paolo Pisati (2):
dt: bindings: fpga: add lattice machxo2 slave spi binding description
fpga: lattice machxo2: Add Lattice MachXO2 support

 .../bindings/fpga/lattice-machxo2-spi.txt          |  29 ++
 drivers/fpga/Kconfig                               |   8 +
 drivers/fpga/Makefile                              |   1 +
 drivers/fpga/machxo2-spi.c                         | 410 +++++++++++++++++++++
 4 files changed, 448 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt
 create mode 100644 drivers/fpga/machxo2-spi.c
Signature · 1 line
2.7.4
author
#1 lore raw

PATCH v6 1/2 dt: bindings: fpga: add lattice machxo2 slave spi binding description

Add dt binding documentation details for Lattice MachXO2 FPGA configuration over Slave SPI interface.

Signed-off-by Paolo Pisati <[email protected]>
Acked-by Rob Herring <[email protected]>
---
 .../bindings/fpga/lattice-machxo2-spi.txt          | 29 ++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt
Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt new file +29 -0
new file mode 100644
index 0000000..a8c362e
@@ -0,0 +1,29 @@
+Lattice MachXO2 Slave SPI FPGA Manager
+
+Lattice MachXO2 FPGAs support a method of loading the bitstream over
+'slave SPI' interface.
+
+See 'MachXO2ProgrammingandConfigurationUsageGuide.pdf' on www.latticesemi.com
+
+Required properties:
+- compatible: should contain "lattice,machxo2-slave-spi"
+- reg: spi chip select of the FPGA
+
+Example for full FPGA configuration:
+
+	fpga-region0 {
+		compatible = "fpga-region";
+		fpga-mgr = <&fpga_mgr_spi>;
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+	};
+
+	spi1: spi@2000 {
+        ...
+
+		fpga_mgr_spi: fpga-mgr@0 {
+			compatible = "lattice,machxo2-slave-spi";
+			spi-max-frequency = <8000000>;
+			reg = <0>;
+		};
+	};
Signature · 1 line
2.7.4
maintainer Acked-by on v6 1/2
#2 lore raw

Re: [PATCH 1/2] dt: bindings: fpga: add lattice machxo2 slave spi binding description

Quoted 5 lines · Paolo Pisati

Add dt binding documentation details for Lattice MachXO2 FPGA configuration over Slave SPI interface.

Signed-off-by Paolo Pisati <[email protected]>
Acked-by Rob Herring <[email protected]>
Acked-by Moritz Fischer <[email protected]>
Quoted 11 lines
---
 .../bindings/fpga/lattice-machxo2-spi.txt          | 29 ++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt
Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt new file +0 -0
new file mode 100644
index 0000000..a8c362e

Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt line 4

Quoted 4 lines
Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt new file +4 -0
@@ -0,0 +1,29 @@
+Lattice MachXO2 Slave SPI FPGA Manager
+
+Lattice MachXO2 FPGAs support a method of loading the bitstream over
+'slave SPI' interface.

Nit: a 'slave SPI'

Quoted 28 lines
Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt new file +25 -0
+
+See 'MachXO2ProgrammingandConfigurationUsageGuide.pdf' on www.latticesemi.com
+
+Required properties:
+- compatible: should contain "lattice,machxo2-slave-spi"
+- reg: spi chip select of the FPGA
+
+Example for full FPGA configuration:
+
+	fpga-region0 {
+		compatible = "fpga-region";
+		fpga-mgr = <&fpga_mgr_spi>;
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+	};
+
+	spi1: spi@2000 {
+        ...
+
+		fpga_mgr_spi: fpga-mgr@0 {
+			compatible = "lattice,machxo2-slave-spi";
+			spi-max-frequency = <8000000>;
+			reg = <0>;
+		};
+	};
Signature · 1 line
2.7.4

Thanks,

Moritz

Acked-by
#3 lore raw

Re: [PATCH 1/2] dt: bindings: fpga: add lattice machxo2 slave spi binding description

Quoted 7 lines · Moritz Fischer
Quoted 5 lines · Paolo Pisati

Add dt binding documentation details for Lattice MachXO2 FPGA configuration over Slave SPI interface.

Signed-off-by Paolo Pisati <[email protected]>
Acked-by Rob Herring <[email protected]>
Acked-by Moritz Fischer <[email protected]>
Acked-by Alan Tull <[email protected]>

Thanks,
Alan

Quoted 48 lines
Quoted 11 lines
---
 .../bindings/fpga/lattice-machxo2-spi.txt          | 29 ++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt
Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt new file +0 -0
new file mode 100644
index 0000000..a8c362e

Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt line 4

Quoted 4 lines
Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt new file +4 -0
@@ -0,0 +1,29 @@
+Lattice MachXO2 Slave SPI FPGA Manager
+
+Lattice MachXO2 FPGAs support a method of loading the bitstream over
+'slave SPI' interface.

Nit: a 'slave SPI'

Quoted 26 lines
Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt new file +25 -1
+
+See 'MachXO2ProgrammingandConfigurationUsageGuide.pdf' on www.latticesemi.com
+
+Required properties:
+- compatible: should contain "lattice,machxo2-slave-spi"
+- reg: spi chip select of the FPGA
+
+Example for full FPGA configuration:
+
+     fpga-region0 {
+             compatible = "fpga-region";
+             fpga-mgr = <&fpga_mgr_spi>;
+             #address-cells = <0x1>;
+             #size-cells = <0x1>;
+     };
+
+     spi1: spi@2000 {
+        ...
+
+             fpga_mgr_spi: fpga-mgr@0 {
+                     compatible = "lattice,machxo2-slave-spi";
+                     spi-max-frequency = <8000000>;
+                     reg = <0>;
+             };
+     };
--
Quoted 2 lines

2.7.4

Thanks,

Moritz

author
#4 lore raw

PATCH v6 2/2 fpga: lattice machxo2: Add Lattice MachXO2 support

In reply to Paolo Pisati

This patch adds support to the FPGA manager for programming MachXO2 device’s internal flash memory, via slave SPI.

Signed-off-by Paolo Pisati <[email protected]>
---
 drivers/fpga/Kconfig       |   8 +
 drivers/fpga/Makefile      |   1 +
 drivers/fpga/machxo2-spi.c | 410 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 419 insertions(+)
 create mode 100644 drivers/fpga/machxo2-spi.c
drivers/fpga/Kconfig +8 -0
index ad5448f..65ccbc5 100644
@@ -38,6 +38,14 @@ config FPGA_MGR_ALTERA_PS_SPI
 	  FPGA manager driver support for Altera Arria/Cyclone/Stratix
 	  using the passive serial interface over SPI.
 
+config FPGA_MGR_MACHXO2_SPI
+	tristate "Lattice MachXO2 SPI"
+	depends on SPI
+	help
+	  FPGA manager driver support for Lattice MachXO2 configuration
+	  over slave SPI interface.
+
+
 config FPGA_MGR_SOCFPGA
 	tristate "Altera SOCFPGA FPGA Manager"
 	depends on ARCH_SOCFPGA || COMPILE_TEST
drivers/fpga/Makefile +1 -0
index f98dcf1..38abb08 100644
@@ -10,6 +10,7 @@ obj-$(CONFIG_FPGA)			+= fpga-mgr.o
 obj-$(CONFIG_FPGA_MGR_ALTERA_CVP)	+= altera-cvp.o
 obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI)	+= altera-ps-spi.o
 obj-$(CONFIG_FPGA_MGR_ICE40_SPI)	+= ice40-spi.o
+obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI)	+= machxo2-spi.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA)		+= socfpga.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)	+= socfpga-a10.o
 obj-$(CONFIG_FPGA_MGR_TS73XX)		+= ts73xx-fpga.o
drivers/fpga/machxo2-spi.c new file +410 -0

410 lines not on this page · raw message

Signature · 1 line
2.7.4
maintainer
#5 lore raw

Re: [PATCH 2/2] fpga: lattice machxo2: Add Lattice MachXO2 support

Quoted 48 lines · Paolo Pisati

This patch adds support to the FPGA manager for programming MachXO2 device’s internal flash memory, via slave SPI.

Signed-off-by Paolo Pisati <[email protected]>
---
 drivers/fpga/Kconfig       |   8 +
 drivers/fpga/Makefile      |   1 +
 drivers/fpga/machxo2-spi.c | 410 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 419 insertions(+)
 create mode 100644 drivers/fpga/machxo2-spi.c
drivers/fpga/Kconfig +8 -0
index ad5448f..65ccbc5 100644
@@ -38,6 +38,14 @@ config FPGA_MGR_ALTERA_PS_SPI
 	  FPGA manager driver support for Altera Arria/Cyclone/Stratix
 	  using the passive serial interface over SPI.
 
+config FPGA_MGR_MACHXO2_SPI
+	tristate "Lattice MachXO2 SPI"
+	depends on SPI
+	help
+	  FPGA manager driver support for Lattice MachXO2 configuration
+	  over slave SPI interface.
+
+
 config FPGA_MGR_SOCFPGA
 	tristate "Altera SOCFPGA FPGA Manager"
 	depends on ARCH_SOCFPGA || COMPILE_TEST
drivers/fpga/Makefile +1 -0
index f98dcf1..38abb08 100644
@@ -10,6 +10,7 @@ obj-$(CONFIG_FPGA)			+= fpga-mgr.o
 obj-$(CONFIG_FPGA_MGR_ALTERA_CVP)	+= altera-cvp.o
 obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI)	+= altera-ps-spi.o
 obj-$(CONFIG_FPGA_MGR_ICE40_SPI)	+= ice40-spi.o
+obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI)	+= machxo2-spi.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA)		+= socfpga.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)	+= socfpga-a10.o
 obj-$(CONFIG_FPGA_MGR_TS73XX)		+= ts73xx-fpga.o
drivers/fpga/machxo2-spi.c new file +0 -0
new file mode 100644
index 0000000..3c7fc3e

drivers/fpga/machxo2-spi.c line 8

Quoted 8 lines
drivers/fpga/machxo2-spi.c new file +8 -0
@@ -0,0 +1,410 @@
+/**
+ * Lattice MachXO2 Slave SPI Driver
+ *
+ * Copyright (C) 2018 Paolo Pisati <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.

SPDX please.

Quoted 4 lines
drivers/fpga/machxo2-spi.c new file +3 -0
+ *
+ * Manage Lattice FPGA firmware that is loaded over SPI using
+ * the slave serial configuration interface.

drivers/fpga/machxo2-spi.c line 21

Quoted 10 lines
drivers/fpga/machxo2-spi.c new file +10 -0
+ */
+
+#include <linux/delay.h>
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/spi/spi.h>
+
+//#define MACHXO2_DEBUG

?! No ;-)

Quoted 64 lines
drivers/fpga/machxo2-spi.c new file +64 -0
+
+/* MachXO2 Programming Guide - sysCONFIG Programming Commands */
+#define IDCODE_PUB			{0xe0, 0x00, 0x00, 0x00}
+#define ISC_ENABLE			{0xc6, 0x08, 0x00, 0x00}
+#define ISC_ERASE			{0x0e, 0x04, 0x00, 0x00}
+#define ISC_PROGRAMDONE		{0x5e, 0x00, 0x00, 0x00}
+#define LSC_INITADDRESS		{0x46, 0x00, 0x00, 0x00}
+#define LSC_PROGINCRNV		{0x70, 0x00, 0x00, 0x01}
+#define LSC_READ_STATUS		{0x3c, 0x00, 0x00, 0x00}
+#define LSC_REFRESH			{0x79, 0x00, 0x00, 0x00}
+
+/*
+ * Max CCLK in Slave SPI mode according to 'MachXO2 Family Data
+ * Sheet' sysCONFIG Port Timing Specifications (3-36)
+ */
+#define MACHXO2_MAX_SPEED			66000000
+
+#define MACHXO2_LOW_DELAY			5		/* us */
+#define MACHXO2_HIGH_DELAY			200		/* us */
+#define MACHXO2_REFRESH				4800	/* us */
+#define MACHXO2_MAX_BUSY_LOOP		128
+#define MACHXO2_MAX_REFRESH_LOOP	16
+
+#define MACHXO2_PAGE_SIZE			16
+#define MACHXO2_BUF_SIZE			(MACHXO2_PAGE_SIZE + 4)
+
+/* Status register bits, errors and error mask */
+#define BUSY	12
+#define DONE	8
+#define DVER	27
+#define ENAB	9
+#define ERRBITS	23
+#define ERRMASK	7
+#define FAIL	13
+
+#define ENOERR	0 /* no error */
+#define EID		1
+#define ECMD	2
+#define	ECRC	3
+#define EPREAM	4 /* preamble error */
+#define EABRT	5 /* abort error */
+#define EOVERFL 6 /* overflow error */
+#define ESDMEOF 7 /* SDM EOF */
+
+static inline u8 get_err(unsigned long *status)
+{
+	return (*status >> ERRBITS) & ERRMASK;
+}
+
+static int get_status(struct spi_device *spi, unsigned long *status)
+{
+	struct spi_message msg;
+	struct spi_transfer rx, tx;
+	u8 cmd[] = LSC_READ_STATUS;
+	int ret;
+
+	memset(&rx, 0, sizeof(rx));
+	memset(&tx, 0, sizeof(tx));
+	tx.tx_buf = cmd;
+	tx.len = sizeof(cmd);
+	rx.rx_buf = status;
+	rx.len = 4;
+	spi_message_init(&msg);
+	spi_message_add_tail(&tx, &msg);

drivers/fpga/machxo2-spi.c line 95

Quoted 10 lines
drivers/fpga/machxo2-spi.c new file +10 -0
+	spi_message_add_tail(&rx, &msg);
+	ret = spi_sync(spi, &msg);
+	if (ret)
+		return ret;
+
+	*status = be32_to_cpu(*status);
+	return 0;
+}
+
+#ifdef MACHXO2_DEBUG

Not a fan of this ...

Quoted 26 lines
drivers/fpga/machxo2-spi.c new file +26 -0
+static void dump_status_reg(unsigned long *status)
+{
+	char *ferr;
+
+	switch (get_err(status)) {
+	case ENOERR:
+		ferr = "No Error";
+		break;
+	case EID:
+		ferr = "ID ERR";
+		break;
+	case ECMD:
+		ferr = "CMD ERR";
+		break;
+	case ECRC:
+		ferr = "CRC ERR";
+		break;
+	case EPREAM:
+		ferr = "Preamble ERR";
+		break;
+	case EABRT:
+		ferr = "Abort ERR";
+		break;
+	case EOVERFL:
+		ferr = "Overflow ERR";
+		break;

drivers/fpga/machxo2-spi.c line 131

Quoted 10 lines
drivers/fpga/machxo2-spi.c new file +10 -0
+	case ESDMEOF:
+		ferr = "SDM EOF";
+		break;
+	default:
+		ferr = "Default switch case";
+	}
+	printk(KERN_DEBUG "machxo2 status: 0x%08lX - done=%d, cfgena=%d, busy=%d, fail=%d, devver=%d, err=%s\n",
+	       *status, test_bit(DONE, status), test_bit(ENAB, status),
+	       test_bit(BUSY, status), test_bit(FAIL, status),
+		   test_bit(DVER, status), ferr);

Not sure we need this function in the first place, if you really think you need it at least use pr_dbg() or pr_err() here.

Quoted 54 lines
drivers/fpga/machxo2-spi.c new file +54 -0
+}
+#else
+static void dump_status_reg(unsigned long *status) {}
+#endif
+
+static int wait_until_not_busy(struct spi_device *spi)
+{
+	unsigned long status;
+	int ret, loop = 0;
+
+	do {
+		ret = get_status(spi, &status);
+		if (ret)
+			break;
+		if (++loop >= MACHXO2_MAX_BUSY_LOOP) {
+			ret = -EBUSY;
+			break;
+		}
+	} while (test_bit(BUSY, &status));
+
+	return ret;
+}
+
+static int machxo2_cleanup(struct fpga_manager *mgr)
+{
+	struct spi_device *spi = mgr->priv;
+	struct spi_message msg;
+	struct spi_transfer tx[2];
+	u8 erase[] = ISC_ERASE;
+	u8 refresh[] = LSC_REFRESH;
+	int ret;
+
+	memset(tx, 0, sizeof(tx));
+	spi_message_init(&msg);
+	tx[0].tx_buf = &erase;
+	tx[0].len = sizeof(erase);
+	spi_message_add_tail(&tx[0], &msg);
+	ret = spi_sync(spi, &msg);
+	if (ret)
+		goto fail;
+
+	ret = wait_until_not_busy(spi);
+	if (ret)
+		goto fail;
+
+	spi_message_init(&msg);
+	tx[1].tx_buf = &refresh;
+	tx[1].len = sizeof(refresh);
+	tx[1].delay_usecs = MACHXO2_REFRESH;
+	spi_message_add_tail(&tx[1], &msg);
+	ret = spi_sync(spi, &msg);
+	if (ret)
+		goto fail;
+

drivers/fpga/machxo2-spi.c line 195

Quoted 10 lines
drivers/fpga/machxo2-spi.c new file +10 -0
+	return 0;
+fail:
+	dev_err(&mgr->dev, "Cleanup failed\n");
+	return ret;
+}
+
+static enum fpga_mgr_states machxo2_spi_state(struct fpga_manager *mgr)
+{
+	return FPGA_MGR_STATE_UNKNOWN;
+}

To understand this correctly: Further up you have a way to determine the state you're in, but then you only use that for debug printout, while here where you should provide the status you say FPGA_MGR_STATE_UNKNOWN?

Am I missing something here?

Quoted 218 lines
drivers/fpga/machxo2-spi.c new file +215 -0
+
+static int machxo2_write_init(struct fpga_manager *mgr,
+			      struct fpga_image_info *info,
+			      const char *buf, size_t count)
+{
+	struct spi_device *spi = mgr->priv;
+	struct spi_message msg;
+	struct spi_transfer tx[3];
+	u8 enable[] = ISC_ENABLE;
+	u8 erase[] = ISC_ERASE;
+	u8 initaddr[] = LSC_INITADDRESS;
+	unsigned long status;
+	int ret;
+
+	if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
+		dev_err(&mgr->dev,
+			"Partial reconfiguration is not supported\n");
+		return -ENOTSUPP;
+	}
+
+	get_status(spi, &status);
+	dump_status_reg(&status);
+	memset(tx, 0, sizeof(tx));
+	spi_message_init(&msg);
+	tx[0].tx_buf = &enable;
+	tx[0].len = sizeof(enable);
+	tx[0].delay_usecs = MACHXO2_LOW_DELAY;
+	spi_message_add_tail(&tx[0], &msg);
+
+	tx[1].tx_buf = &erase;
+	tx[1].len = sizeof(erase);
+	spi_message_add_tail(&tx[1], &msg);
+	ret = spi_sync(spi, &msg);
+	if (ret)
+		goto fail;
+
+	ret = wait_until_not_busy(spi);
+	if (ret)
+		goto fail;
+
+	get_status(spi, &status);
+	if (test_bit(FAIL, &status))
+		goto fail;
+	dump_status_reg(&status);
+
+	spi_message_init(&msg);
+	tx[2].tx_buf = &initaddr;
+	tx[2].len = sizeof(initaddr);
+	spi_message_add_tail(&tx[2], &msg);
+	ret = spi_sync(spi, &msg);
+	if (ret)
+		goto fail;
+
+	get_status(spi, &status);
+	dump_status_reg(&status);
+	return 0;
+fail:
+	dev_err(&mgr->dev, "Error during FPGA init.\n");
+	return ret;
+}
+
+static int machxo2_write(struct fpga_manager *mgr, const char *buf,
+			 size_t count)
+{
+	struct spi_device *spi = mgr->priv;
+	struct spi_message msg;
+	struct spi_transfer tx;
+	u8 progincr[] = LSC_PROGINCRNV;
+	u8 payload[MACHXO2_BUF_SIZE];
+	unsigned long status;
+	int i, ret;
+
+	if (count % MACHXO2_PAGE_SIZE != 0) {
+		dev_err(&mgr->dev, "Malformed payload.\n");
+		return -EINVAL;
+	}
+	get_status(spi, &status);
+	dump_status_reg(&status);
+	memcpy(payload, &progincr, sizeof(progincr));
+	for (i = 0; i < count; i += MACHXO2_PAGE_SIZE) {
+		memcpy(&payload[sizeof(progincr)], &buf[i], MACHXO2_PAGE_SIZE);
+		memset(&tx, 0, sizeof(tx));
+		spi_message_init(&msg);
+		tx.tx_buf = payload;
+		tx.len = MACHXO2_BUF_SIZE;
+		tx.delay_usecs = MACHXO2_HIGH_DELAY;
+		spi_message_add_tail(&tx, &msg);
+		ret = spi_sync(spi, &msg);
+		if (ret) {
+			dev_err(&mgr->dev, "Error loading the bitstream.\n");
+			return ret;
+		}
+	}
+	get_status(spi, &status);
+	dump_status_reg(&status);
+
+	return 0;
+}
+
+static int machxo2_write_complete(struct fpga_manager *mgr,
+				  struct fpga_image_info *info)
+{
+	struct spi_device *spi = mgr->priv;
+	struct spi_message msg;
+	struct spi_transfer tx[2];
+	u8 progdone[] = ISC_PROGRAMDONE;
+	u8 refresh[] = LSC_REFRESH;
+	unsigned long status;
+	int ret, refreshloop = 0;
+
+	memset(tx, 0, sizeof(tx));
+	spi_message_init(&msg);
+	tx[0].tx_buf = &progdone;
+	tx[0].len = sizeof(progdone);
+	spi_message_add_tail(&tx[0], &msg);
+	ret = spi_sync(spi, &msg);
+	if (ret)
+		goto fail;
+	ret = wait_until_not_busy(spi);
+	if (ret)
+		goto fail;
+
+	get_status(spi, &status);
+	dump_status_reg(&status);
+	if (!test_bit(DONE, &status)) {
+		machxo2_cleanup(mgr);
+		goto fail;
+	}
+
+	do {
+		spi_message_init(&msg);
+		tx[1].tx_buf = &refresh;
+		tx[1].len = sizeof(refresh);
+		tx[1].delay_usecs = MACHXO2_REFRESH;
+		spi_message_add_tail(&tx[1], &msg);
+		ret = spi_sync(spi, &msg);
+		if (ret)
+			goto fail;
+
+		/* check refresh status */
+		get_status(spi, &status);
+		dump_status_reg(&status);
+		if (!test_bit(BUSY, &status) && test_bit(DONE, &status) &&
+			get_err(&status) == ENOERR)
+				break;
+		if (++refreshloop == MACHXO2_MAX_REFRESH_LOOP) {
+			machxo2_cleanup(mgr);
+			goto fail;
+		}
+	} while (1);
+
+	get_status(spi, &status);
+	dump_status_reg(&status);
+	return 0;
+fail:
+	dev_err(&mgr->dev, "Refresh failed.\n");
+	return ret;
+}
+
+static const struct fpga_manager_ops machxo2_ops = {
+	.state = machxo2_spi_state,
+	.write_init = machxo2_write_init,
+	.write = machxo2_write,
+	.write_complete = machxo2_write_complete,
+};
+
+static int machxo2_spi_probe(struct spi_device *spi)
+{
+	struct device *dev = &spi->dev;
+
+	if (spi->max_speed_hz > MACHXO2_MAX_SPEED) {
+		dev_err(dev, "Speed is too high\n");
+		return -EINVAL;
+	}
+
+	return fpga_mgr_register(dev, "Lattice MachXO2 SPI FPGA Manager",
+				 &machxo2_ops, spi);
+}
+
+static int machxo2_spi_remove(struct spi_device *spi)
+{
+	struct device *dev = &spi->dev;
+
+	fpga_mgr_unregister(dev);
+
+	return 0;
+}
+
+static const struct of_device_id of_match[] = {
+	{ .compatible = "lattice,machxo2-slave-spi", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, of_match);
+
+static const struct spi_device_id lattice_ids[] = {
+	{ "machxo2-slave-spi", 0 },
+	{ },
+};
+MODULE_DEVICE_TABLE(spi, lattice_ids);
+
+static struct spi_driver machxo2_spi_driver = {
+	.driver = {
+		.name = "machxo2-slave-spi",
+		.of_match_table = of_match_ptr(of_match),
+	},
+	.probe = machxo2_spi_probe,
+	.remove = machxo2_spi_remove,
+	.id_table = lattice_ids,
+};
+
+module_spi_driver(machxo2_spi_driver)
+
+MODULE_AUTHOR("Paolo Pisati <[email protected]>");
+MODULE_DESCRIPTION("Load Lattice FPGA firmware over SPI");
+MODULE_LICENSE("GPL v2");
Signature · 1 line
2.7.4
author
#6 lore raw

Re: [PATCH 2/2] fpga: lattice machxo2: Add Lattice MachXO2 support

Quoted 11 lines · Moritz Fischer

drivers/fpga/machxo2-spi.c line 195

Quoted 5 lines
drivers/fpga/machxo2-spi.c new file +4 -0
+static enum fpga_mgr_states machxo2_spi_state(struct fpga_manager *mgr)
+{
+	return FPGA_MGR_STATE_UNKNOWN;
+}

To understand this correctly: Further up you have a way to determine the state you're in, but then you only use that for debug printout, while here where you should provide the status you say FPGA_MGR_STATE_UNKNOWN?

Am I missing something here?

This is more of a generic function ('What's the state of the FPGA now?') while dump_status_reg() is invoked after a specific SPI command is sent to the FPGA to keep track of the status of the chip and check that it adhere to the state machine.

I'll send a v7.

Signature · 2 lines
bye,
p.