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ARM: dts: tegra: Add 256 MB Colibri-T20 and cleanups

PATCH Superseded Krzysztof Kozlowski 2 participants 6 messages May 15, 2018 – May 17, 2018

Subsystems (2)
Device tree bindings Tegra architecture support

v4 of 5 Superseded Latest is v5 →

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Krzysztof Kozlowski

author
#0 lore raw

v4 cover ARM: dts: tegra: Add 256 MB Colibri-T20 and cleanups

Hi,

Changes since v3:
1. Patch 3/3: Just reduce the memory of existing DTSI (suggested by Marcel).

Best regards,
Krzysztof

Krzysztof Kozlowski (3):
ARM: dts: tegra: Remove skeleton.dtsi and fix DTC warnings for /memory
ARM: dts: tegra: Fix unit_address_vs_reg and
avoid_unnecessary_addr_size DTC warnings
ARM: dts: tegra: Work safely with 256 MB Colibri-T20 modules

 arch/arm/boot/dts/tegra114-dalmore.dts      |  3 ++-
 arch/arm/boot/dts/tegra114-roth.dts         |  3 ++-
 arch/arm/boot/dts/tegra114-tn7.dts          |  3 ++-
 arch/arm/boot/dts/tegra114.dtsi             |  4 ++--
 arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi |  3 ++-
 arch/arm/boot/dts/tegra124-apalis.dtsi      |  3 ++-
 arch/arm/boot/dts/tegra124-jetson-tk1.dts   |  3 ++-
 arch/arm/boot/dts/tegra124-nyan.dtsi        |  3 ++-
 arch/arm/boot/dts/tegra124-venice2.dts      |  3 ++-
 arch/arm/boot/dts/tegra124.dtsi             |  2 --
 arch/arm/boot/dts/tegra20-colibri-512.dtsi  | 12 +++++++++---
 arch/arm/boot/dts/tegra20-harmony.dts       |  3 ++-
 arch/arm/boot/dts/tegra20-iris-512.dts      |  2 +-
 arch/arm/boot/dts/tegra20-paz00.dts         |  3 ++-
 arch/arm/boot/dts/tegra20-seaboard.dts      |  3 ++-
 arch/arm/boot/dts/tegra20-tamonten.dtsi     |  3 ++-
 arch/arm/boot/dts/tegra20-trimslice.dts     |  3 ++-
 arch/arm/boot/dts/tegra20-ventana.dts       |  3 ++-
 arch/arm/boot/dts/tegra20.dtsi              |  7 +++++--
 arch/arm/boot/dts/tegra30-apalis.dtsi       |  9 ++++++---
 arch/arm/boot/dts/tegra30-beaver.dts        |  6 ++----
 arch/arm/boot/dts/tegra30-cardhu.dtsi       |  3 ++-
 arch/arm/boot/dts/tegra30-colibri.dtsi      |  5 ++---
 arch/arm/boot/dts/tegra30.dtsi              |  7 +++++--
 24 files changed, 62 insertions(+), 37 deletions(-)
Signature · 1 line
2.7.4
author
#1 lore raw

PATCH v4 1/3 ARM: dts: tegra: Remove skeleton.dtsi and fix DTC warnings for /memory

Remove the usage of skeleton.dtsi and add necessary properties to /memory node to fix the DTC warnings:

arch/arm/boot/dts/tegra20-harmony.dtb: Warning (unit_address_vs_reg):
/memory: node has a reg or ranges property, but no unit name

The DTB after the change is the same as before except adding unit-address to /memory node.

Signed-off-by Krzysztof Kozlowski <[email protected]>
---
 arch/arm/boot/dts/tegra114-dalmore.dts      | 3 ++-
 arch/arm/boot/dts/tegra114-roth.dts         | 3 ++-
 arch/arm/boot/dts/tegra114-tn7.dts          | 3 ++-
 arch/arm/boot/dts/tegra114.dtsi             | 4 ++--
 arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 3 ++-
 arch/arm/boot/dts/tegra124-apalis.dtsi      | 3 ++-
 arch/arm/boot/dts/tegra124-jetson-tk1.dts   | 3 ++-
 arch/arm/boot/dts/tegra124-nyan.dtsi        | 3 ++-
 arch/arm/boot/dts/tegra124-venice2.dts      | 3 ++-
 arch/arm/boot/dts/tegra124.dtsi             | 2 --
 arch/arm/boot/dts/tegra20-colibri-512.dtsi  | 3 ++-
 arch/arm/boot/dts/tegra20-harmony.dts       | 3 ++-
 arch/arm/boot/dts/tegra20-paz00.dts         | 3 ++-
 arch/arm/boot/dts/tegra20-seaboard.dts      | 3 ++-
 arch/arm/boot/dts/tegra20-tamonten.dtsi     | 3 ++-
 arch/arm/boot/dts/tegra20-trimslice.dts     | 3 ++-
 arch/arm/boot/dts/tegra20-ventana.dts       | 3 ++-
 arch/arm/boot/dts/tegra20.dtsi              | 7 +++++--
 arch/arm/boot/dts/tegra30-apalis.dtsi       | 5 +++++
 arch/arm/boot/dts/tegra30-beaver.dts        | 3 ++-
 arch/arm/boot/dts/tegra30-cardhu.dtsi       | 3 ++-
 arch/arm/boot/dts/tegra30-colibri.dtsi      | 3 ++-
 arch/arm/boot/dts/tegra30.dtsi              | 7 +++++--
 23 files changed, 53 insertions(+), 26 deletions(-)
arch/arm/boot/dts/tegra114-dalmore.dts +2 -1
index eafff16765b4..5cdcedfc19cb 100644
@@ -23,7 +23,8 @@
 		stdout-path = "serial0:115200n8";
 	};
 
-	memory {
+	memory@80000000 {
+		device_type = "memory";
 		reg = <0x80000000 0x40000000>;
 	};
arch/arm/boot/dts/tegra114-roth.dts +2 -1
index 7ed7370ee67a..b4f329a07c60 100644
@@ -28,7 +28,8 @@
 		};
 	};
 
-	memory {
+	memory@80000000 {
+		device_type = "memory";
 		/* memory >= 0x79600000 is reserved for firmware usage */
 		reg = <0x80000000 0x79600000>;
 	};
arch/arm/boot/dts/tegra114-tn7.dts +2 -1
index 7fc4a8b31e45..12092d344ce8 100644
@@ -28,7 +28,8 @@
 		};
 	};
 
-	memory {
+	memory@80000000 {
+		device_type = "memory";
 		/* memory >= 0x37e00000 is reserved for firmware usage */
 		reg = <0x80000000 0x37e00000>;
 	};
arch/arm/boot/dts/tegra114.dtsi +2 -2
index 0e4a13295d8a..b917784d3f97 100644
@@ -5,11 +5,11 @@
 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
-#include "skeleton.dtsi"
-
 / {
 	compatible = "nvidia,tegra114";
 	interrupt-parent = <&lic>;
+	#address-cells = <1>;
+	#size-cells = <1>;
 
 	host1x@50000000 {
 		compatible = "nvidia,tegra114-host1x", "simple-bus";
arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +2 -1
index bb67edb016c5..80b52c612891 100644
@@ -15,7 +15,8 @@
 	compatible = "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1",
 		     "nvidia,tegra124";
 
-	memory {
+	memory@0 {
+		device_type = "memory";
 		reg = <0x0 0x80000000 0x0 0x80000000>;
 	};
arch/arm/boot/dts/tegra124-apalis.dtsi +2 -1
index 65a2161b9b8e..3ca7601cafe9 100644
@@ -50,7 +50,8 @@
 	model = "Toradex Apalis TK1";
 	compatible = "toradex,apalis-tk1", "nvidia,tegra124";
 
-	memory {
+	memory@0 {
+		device_type = "memory";
 		reg = <0x0 0x80000000 0x0 0x80000000>;
 	};
arch/arm/boot/dts/tegra124-jetson-tk1.dts +2 -1
index 6dbcf84dafbc..8d9e6ee6c6a7 100644
@@ -24,7 +24,8 @@
 		stdout-path = "serial0:115200n8";
 	};
 
-	memory {
+	memory@0 {
+		device_type = "memory";
 		reg = <0x0 0x80000000 0x0 0x80000000>;
 	};
arch/arm/boot/dts/tegra124-nyan.dtsi +2 -1
index 3609367037a6..15a2b0e3237e 100644
@@ -13,7 +13,8 @@
 		stdout-path = "serial0:115200n8";
 	};
 
-	memory {
+	memory@0 {
+		device_type = "memory";
 		reg = <0x0 0x80000000 0x0 0x80000000>;
 	};
arch/arm/boot/dts/tegra124-venice2.dts +2 -1
index 89bcc178994d..241cdc4b6600 100644
@@ -18,7 +18,8 @@
 		stdout-path = "serial0:115200n8";
 	};
 
-	memory {
+	memory@0 {
+		device_type = "memory";
 		reg = <0x0 0x80000000 0x0 0x80000000>;
 	};
arch/arm/boot/dts/tegra124.dtsi +0 -2
index 174092bfac90..df1642876a4c 100644
@@ -7,8 +7,6 @@
 #include <dt-bindings/reset/tegra124-car.h>
 #include <dt-bindings/thermal/tegra124-soctherm.h>
 
-#include "skeleton.dtsi"
-
 / {
 	compatible = "nvidia,tegra124";
 	interrupt-parent = <&lic>;
arch/arm/boot/dts/tegra20-colibri-512.dtsi +2 -1
index 5c202b3e3bb1..305efb275b48 100644
@@ -10,7 +10,8 @@
 		rtc1 = "/rtc@7000e000";
 	};
 
-	memory {
+	memory@0 {
+		device_type = "memory";
 		reg = <0x00000000 0x20000000>;
 	};
arch/arm/boot/dts/tegra20-harmony.dts +2 -1
index 628a55a9318b..5009a55ae15c 100644
@@ -18,7 +18,8 @@
 		stdout-path = "serial0:115200n8";
 	};
 
-	memory {
+	memory@0 {
+		device_type = "memory";
 		reg = <0x00000000 0x40000000>;
 	};
arch/arm/boot/dts/tegra20-paz00.dts +2 -1
index 30436969adc0..e794ac5442ef 100644
@@ -19,7 +19,8 @@
 		stdout-path = "serial0:115200n8";
 	};
 
-	memory {
+	memory@0 {
+		device_type = "memory";
 		reg = <0x00000000 0x20000000>;
 	};
arch/arm/boot/dts/tegra20-seaboard.dts +2 -1
index 284aae351ff2..6cb832cfa4f3 100644
@@ -18,7 +18,8 @@
 		stdout-path = "serial0:115200n8";
 	};
 
-	memory {
+	memory@0 {
+		device_type = "memory";
 		reg = <0x00000000 0x40000000>;
 	};
arch/arm/boot/dts/tegra20-tamonten.dtsi +2 -1
index 872046d48709..6ceb1228fed3 100644
@@ -15,7 +15,8 @@
 		stdout-path = "serial0:115200n8";
 	};
 
-	memory {
+	memory@0 {
+		device_type = "memory";
 		reg = <0x00000000 0x20000000>;
 	};
arch/arm/boot/dts/tegra20-trimslice.dts +2 -1
index d55c6b240a30..3f94be3da9e5 100644
@@ -18,7 +18,8 @@
 		stdout-path = "serial0:115200n8";
 	};
 
-	memory {
+	memory@0 {
+		device_type = "memory";
 		reg = <0x00000000 0x40000000>;
 	};
arch/arm/boot/dts/tegra20-ventana.dts +2 -1
index ee3fbf941e79..c897a90289bc 100644
@@ -18,7 +18,8 @@
 		stdout-path = "serial0:115200n8";
 	};
 
-	memory {
+	memory@0 {
+		device_type = "memory";
 		reg = <0x00000000 0x40000000>;
 	};
arch/arm/boot/dts/tegra20.dtsi +5 -2
index 0a7136462a1a..290ebbeb210f 100644
@@ -4,11 +4,14 @@
 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
-#include "skeleton.dtsi"
-
 / {
 	compatible = "nvidia,tegra20";
 	interrupt-parent = <&lic>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen { };
+	aliases { };
 
 	iram@40000000 {
 		compatible = "mmio-sram";
arch/arm/boot/dts/tegra30-apalis.dtsi +5 -0
index d1d21ec2a844..184f60c720fa 100644
@@ -10,6 +10,11 @@
 	model = "Toradex Apalis T30";
 	compatible = "toradex,apalis_t30", "nvidia,tegra30";
 
+	memory@0 {
+		device_type = "memory";
+		reg = <0 0>;
+	};
+
 	pcie@3000 {
 		avdd-pexa-supply = <&vdd2_reg>;
 		vdd-pexa-supply = <&vdd2_reg>;
arch/arm/boot/dts/tegra30-beaver.dts +2 -1
index ae52a5039506..72369877d284 100644
@@ -17,7 +17,8 @@
 		stdout-path = "serial0:115200n8";
 	};
 
-	memory {
+	memory@80000000 {
+		device_type = "memory";
 		reg = <0x80000000 0x7ff00000>;
 	};
arch/arm/boot/dts/tegra30-cardhu.dtsi +2 -1
index 92a9740c533f..24c04d4c335d 100644
@@ -40,7 +40,8 @@
 		stdout-path = "serial0:115200n8";
 	};
 
-	memory {
+	memory@80000000 {
+		device_type = "memory";
 		reg = <0x80000000 0x40000000>;
 	};
arch/arm/boot/dts/tegra30-colibri.dtsi +2 -1
index c44d8c40c410..cc46cedf80b9 100644
@@ -10,7 +10,8 @@
 	model = "Toradex Colibri T30";
 	compatible = "toradex,colibri_t30", "nvidia,tegra30";
 
-	memory {
+	memory@80000000 {
+		device_type = "memory";
 		reg = <0x80000000 0x40000000>;
 	};
arch/arm/boot/dts/tegra30.dtsi +5 -2
index a110cf84d85f..4383f0fd789d 100644
@@ -5,11 +5,14 @@
 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
-#include "skeleton.dtsi"
-
 / {
 	compatible = "nvidia,tegra30";
 	interrupt-parent = <&lic>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen { };
+	aliases { };
 
 	pcie@3000 {
 		compatible = "nvidia,tegra30-pcie";
Signature · 1 line
2.7.4
author
#2 lore raw

PATCH v4 2/3 ARM: dts: tegra: Fix unit_address_vs_reg and avoid_unnecessary_addr_size DTC warnings

In reply to Krzysztof Kozlowski

Remove unneeded address/size cells properties and unit addresses to fix DTC warnings like:

arch/arm/boot/dts/tegra30-apalis-eval.dtb: Warning (unit_address_vs_reg):
/i2c@7000d000/stmpe811@41/stmpe_touchscreen@0: node has a unit name, but no reg property
arch/arm/boot/dts/tegra30-apalis-eval.dtb: Warning (avoid_unnecessary_addr_size):
/i2c@7000d000/stmpe811@41: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property

Signed-off-by Krzysztof Kozlowski <[email protected]>
---
 arch/arm/boot/dts/tegra30-apalis.dtsi  | 4 +---
 arch/arm/boot/dts/tegra30-beaver.dts   | 3 ---
 arch/arm/boot/dts/tegra30-colibri.dtsi | 2 --
 3 files changed, 1 insertion(+), 8 deletions(-)
arch/arm/boot/dts/tegra30-apalis.dtsi +1 -3
index 184f60c720fa..5038ca7b68af 100644
@@ -590,8 +590,6 @@
 		/* STMPE811 touch screen controller */
 		stmpe811@41 {
 			compatible = "st,stmpe811";
-			#address-cells = <1>;
-			#size-cells = <0>;
 			reg = <0x41>;
 			interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
 			interrupt-parent = <&gpio>;

@@ -600,7 +598,7 @@
 			blocks = <0x5>;
 			irq-trigger = <0x1>;
 
-			stmpe_touchscreen@0 {
+			stmpe_touchscreen {
 				compatible = "st,stmpe-ts";
 				/* 3.25 MHz ADC clock speed */
 				st,adc-freq = <1>;
arch/arm/boot/dts/tegra30-beaver.dts +0 -3
index 72369877d284..961934f70639 100644
@@ -1791,9 +1791,6 @@
 			vccio-supply = <&vdd_5v_in_reg>;
 
 			regulators {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
 				vdd1_reg: vdd1 {
 					regulator-name = "vddio_ddr_1v2";
 					regulator-min-microvolt = <1200000>;
arch/arm/boot/dts/tegra30-colibri.dtsi +0 -2
index cc46cedf80b9..a593dc8be47f 100644
@@ -352,8 +352,6 @@
 		/* STMPE811 touch screen controller */
 		stmpe811@41 {
 			compatible = "st,stmpe811";
-			#address-cells = <1>;
-			#size-cells = <0>;
 			reg = <0x41>;
 			interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
 			interrupt-parent = <&gpio>;
Signature · 1 line
2.7.4
author
#3 lore raw

PATCH v4 3/3 ARM: dts: tegra: Work safely with 256 MB Colibri-T20 modules

In reply to Krzysztof Kozlowski

Colibri-T20 can come in 256 MB RAM (with 512 MB NAND) or 512 MB RAM (with 1024 MB NAND) flavors. Both of them will use the same DTSI expecting the bootloader to do the fixup of /memory node. However in case it does not happen, let's stay on safe side by limiting the memory to 256 MB for both versions of Colibri-T20.

Signed-off-by Krzysztof Kozlowski <[email protected]>

---

RFT:
Not tested on 512 MB module as I have only the 256 MB one.

Changes since v3:
1. Reduce the memory in existing DTSI instead of creating a new one (suggested by Marcel).

Changes since v2:
1. Do not add new compatible but use everywhere existing "toradex,colibri_t20-512" (suggested by Rob).

Changes since v1:
1. Fix memory size in tegra20-colibri-256.dtsi (was working fine because my bootloader uses mem= argument).

---
 arch/arm/boot/dts/tegra20-colibri-512.dtsi | 9 +++++++--
 arch/arm/boot/dts/tegra20-iris-512.dts     | 2 +-
 2 files changed, 8 insertions(+), 3 deletions(-)
arch/arm/boot/dts/tegra20-colibri-512.dtsi +7 -2
index 305efb275b48..b9387c540450 100644
@@ -2,7 +2,7 @@
 #include "tegra20.dtsi"
 
 / {
-	model = "Toradex Colibri T20 512MB";
+	model = "Toradex Colibri T20 256/512 MB";
 	compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
 
 	aliases {

@@ -12,7 +12,12 @@
 
 	memory@0 {
 		device_type = "memory";
-		reg = <0x00000000 0x20000000>;
+		/*
+		 * Set memory to 256 MB to be safe as this could be used on
+		 * 256 or 512 MB module. It is expected from bootloader
+		 * to fix this up for 512 MB version.
+		 */
+		reg = <0x00000000 0x10000000>;
 	};
 
 	host1x@50000000 {
arch/arm/boot/dts/tegra20-iris-512.dts +1 -1
index 40126388946d..efaa96228722 100644
@@ -4,7 +4,7 @@
 #include "tegra20-colibri-512.dtsi"
 
 / {
-	model = "Toradex Colibri T20 512MB on Iris";
+	model = "Toradex Colibri T20 256/512 MB on Iris";
 	compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
 
 	aliases {
Signature · 1 line
2.7.4
#4 lore raw

Re: [PATCH v4 3/3] ARM: dts: tegra: Work safely with 256 MB Colibri-T20 modules

Quoted 21 lines · Krzysztof Kozlowski

Colibri-T20 can come in 256 MB RAM (with 512 MB NAND) or 512 MB RAM (with 1024 MB NAND) flavors. Both of them will use the same DTSI expecting the bootloader to do the fixup of /memory node. However in case it does not happen, let's stay on safe side by limiting the memory to 256 MB for both versions of Colibri-T20.

Signed-off-by Krzysztof Kozlowski <[email protected]>

---

RFT:
Not tested on 512 MB module as I have only the 256 MB one.

Changes since v3:
1. Reduce the memory in existing DTSI instead of creating a new one (suggested by Marcel).

Changes since v2:
1. Do not add new compatible but use everywhere existing "toradex,colibri_t20-512" (suggested by Rob).

Quoted 6 lines

Changes since v1:
1. Fix memory size in tegra20-colibri-256.dtsi (was working fine because my bootloader uses mem= argument).

---
 arch/arm/boot/dts/tegra20-colibri-512.dtsi | 9 +++++++--
 arch/arm/boot/dts/tegra20-iris-512.dts     | 2 +-

I don't like this variant too much.

Can we not just drop the 512? And while at it, I would prefer to see the usual $soc-$module-$carrier schema, as we use with all the other modules of the Colibri and Apalis family.

e.g.
tegra20-colibri-512.dtsi -> tegra20-colibri.dtsi
tegra20-iris-512.dts -> tegra20-colibri-iris.dts

Yes, it is somewhat churn, but I would prefer it for the sake of clarity and consistency...

--
Stefan

Quoted 44 lines
 2 files changed, 8 insertions(+), 3 deletions(-)
arch/arm/boot/dts/tegra20-colibri-512.dtsi +7 -2
index 305efb275b48..b9387c540450 100644
@@ -2,7 +2,7 @@
 #include "tegra20.dtsi"
 
 / {
-	model = "Toradex Colibri T20 512MB";
+	model = "Toradex Colibri T20 256/512 MB";
 	compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
 
 	aliases {

@@ -12,7 +12,12 @@
 
 	memory@0 {
 		device_type = "memory";
-		reg = <0x00000000 0x20000000>;
+		/*
+		 * Set memory to 256 MB to be safe as this could be used on
+		 * 256 or 512 MB module. It is expected from bootloader
+		 * to fix this up for 512 MB version.
+		 */
+		reg = <0x00000000 0x10000000>;
 	};
 
 	host1x@50000000 {
arch/arm/boot/dts/tegra20-iris-512.dts +1 -1
index 40126388946d..efaa96228722 100644
@@ -4,7 +4,7 @@
 #include "tegra20-colibri-512.dtsi"
 
 / {
-	model = "Toradex Colibri T20 512MB on Iris";
+	model = "Toradex Colibri T20 256/512 MB on Iris";
 	compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
 
 	aliases {
author
#5 lore raw

Re: [PATCH v4 3/3] ARM: dts: tegra: Work safely with 256 MB Colibri-T20 modules

Quoted 31 lines · Stefan Agner
Quoted 21 lines · Krzysztof Kozlowski

Colibri-T20 can come in 256 MB RAM (with 512 MB NAND) or 512 MB RAM (with 1024 MB NAND) flavors. Both of them will use the same DTSI expecting the bootloader to do the fixup of /memory node. However in case it does not happen, let's stay on safe side by limiting the memory to 256 MB for both versions of Colibri-T20.

Signed-off-by Krzysztof Kozlowski <[email protected]>

---

RFT:
Not tested on 512 MB module as I have only the 256 MB one.

Changes since v3:
1. Reduce the memory in existing DTSI instead of creating a new one (suggested by Marcel).

Changes since v2:
1. Do not add new compatible but use everywhere existing "toradex,colibri_t20-512" (suggested by Rob).

Quoted 6 lines

Changes since v1:
1. Fix memory size in tegra20-colibri-256.dtsi (was working fine because my bootloader uses mem= argument).

---
 arch/arm/boot/dts/tegra20-colibri-512.dtsi | 9 +++++++--
 arch/arm/boot/dts/tegra20-iris-512.dts     | 2 +-

I don't like this variant too much.

Quoted 7 lines

Can we not just drop the 512? And while at it, I would prefer to see the usual $soc-$module-$carrier schema, as we use with all the other modules of the Colibri and Apalis family.

e.g.
tegra20-colibri-512.dtsi -> tegra20-colibri.dtsi
tegra20-iris-512.dts -> tegra20-colibri-iris.dts

Sure, let me resend it.

BR,
Krzysztof