Add display clock controller driver for SDM845

Frequency table macro is used by multiple clock drivers, move frequency table macro to common header file.

Signed-off-by Taniya Das <[email protected]>

---

Add device tree bindings for display clock controller for Qualcomm Technology Inc's SDM845 SoCs.

Signed-off-by Taniya Das <[email protected]>

Reviewed-by Rob Herring <[email protected]>

---

drivers/clk/qcom/dispcc-sdm845.c new file +1 -0

new file mode 100644
index 0000000..af437e0
@@ -0,0 +1,674 @@
+// SPDX-License-Identifier: GPL-2.0

drivers/clk/qcom/dispcc-sdm845.c new file +13 -0

+static struct clk_alpha_pll disp_cc_pll0 = {
+       .offset = 0x0,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+       .clkr = {
+               .hw.init = &(struct clk_init_data){
+                       .name = "disp_cc_pll0",
+                       .parent_names = (const char *[]){ "bi_tcxo" },
+                       .num_parents = 1,
+                       .ops = &clk_alpha_pll_fabia_ops,
+               },
+       },
+};
+

drivers/clk/qcom/dispcc-sdm845.c new file +51 -0

+               .ops = &clk_byte2_ops,
+       },
+};
+
+static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
+       .cmd_rcgr = 0x20ec,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_0,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_byte1_clk_src",
+               .parent_names = disp_cc_parent_names_0,
+               .num_parents = 4,
+               .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+               .ops = &clk_byte2_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
+       F(19200000, P_BI_TCXO, 1, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
+       .cmd_rcgr = 0x2108,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_0,
+       .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_esc0_clk_src",
+               .parent_names = disp_cc_parent_names_0,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
+       .cmd_rcgr = 0x2120,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_0,
+       .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_esc1_clk_src",
+               .parent_names = disp_cc_parent_names_0,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+

Quoting Taniya Das (2018-06-23 07:19:27)

Quoted 7 lines

drivers/clk/qcom/dispcc-sdm845.c new file +1 -0

new file mode 100644
index 0000000..af437e0
@@ -0,0 +1,674 @@
+// SPDX-License-Identifier: GPL-2.0

[...]

Quoted 19 lines

drivers/clk/qcom/dispcc-sdm845.c new file +19 -0

+static struct clk_alpha_pll disp_cc_pll0 = {
+       .offset = 0x0,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+       .clkr = {
+               .hw.init = &(struct clk_init_data){
+                       .name = "disp_cc_pll0",
+                       .parent_names = (const char *[]){ "bi_tcxo" },
+                       .num_parents = 1,
+                       .ops = &clk_alpha_pll_fabia_ops,
+               },
+       },
+};
+
+static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
+       .cmd_rcgr = 0x20d0,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_0,
+       .clkr.hw.init = &(struct clk_init_data){

drivers/clk/qcom/dispcc-sdm845.c line 110

Quoted 4 lines

drivers/clk/qcom/dispcc-sdm845.c new file +4 -0

+               .name = "disp_cc_mdss_byte0_clk_src",
+               .parent_names = disp_cc_parent_names_0,
+               .num_parents = 4,
+               .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,

Why is there the no cache flag? Last time I asked I don't think I got any answer, and there isn't a comment here so please at least add a comment to the code so we don't forget.

Why is the nocache flag needed? Applies to all clks in this file.

Quoted 51 lines

drivers/clk/qcom/dispcc-sdm845.c new file +51 -0

+               .ops = &clk_byte2_ops,
+       },
+};
+
+static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
+       .cmd_rcgr = 0x20ec,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_0,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_byte1_clk_src",
+               .parent_names = disp_cc_parent_names_0,
+               .num_parents = 4,
+               .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+               .ops = &clk_byte2_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
+       F(19200000, P_BI_TCXO, 1, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
+       .cmd_rcgr = 0x2108,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_0,
+       .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_esc0_clk_src",
+               .parent_names = disp_cc_parent_names_0,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
+       .cmd_rcgr = 0x2120,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_0,
+       .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_esc1_clk_src",
+               .parent_names = disp_cc_parent_names_0,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+

[...]

drivers/clk/qcom/dispcc-sdm845.c line 674

Quoted 2 lines

drivers/clk/qcom/dispcc-sdm845.c new file +2 -0

+
+MODULE_LICENSE("GPL v2");

MODULE_DESCRIPTION?

Hello Stephen,

Thanks for your review comments.

Quoted 28 lines · Stephen Boyd

Quoting Taniya Das (2018-06-23 07:19:27)

Quoted 7 lines

drivers/clk/qcom/dispcc-sdm845.c new file +1 -0

new file mode 100644
index 0000000..af437e0
@@ -0,0 +1,674 @@
+// SPDX-License-Identifier: GPL-2.0

[...]

Quoted 19 lines

drivers/clk/qcom/dispcc-sdm845.c new file +19 -0

+static struct clk_alpha_pll disp_cc_pll0 = {
+       .offset = 0x0,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+       .clkr = {
+               .hw.init = &(struct clk_init_data){
+                       .name = "disp_cc_pll0",
+                       .parent_names = (const char *[]){ "bi_tcxo" },
+                       .num_parents = 1,
+                       .ops = &clk_alpha_pll_fabia_ops,
+               },
+       },
+};
+
+static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
+       .cmd_rcgr = 0x20d0,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_0,
+       .clkr.hw.init = &(struct clk_init_data){

Quoted 9 lines

drivers/clk/qcom/dispcc-sdm845.c line 110

Quoted 4 lines

drivers/clk/qcom/dispcc-sdm845.c new file +4 -0

+               .name = "disp_cc_mdss_byte0_clk_src",
+               .parent_names = disp_cc_parent_names_0,
+               .num_parents = 4,
+               .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,

Why is there the no cache flag? Last time I asked I don't think I got any answer, and there isn't a comment here so please at least add a comment to the code so we don't forget.

I think you missed my comment from the earlier email. I would add the comment and submit again.

Quoted 3 lines

Why is the nocache flag needed? Applies to all clks in this file.

This flag is required for all RCGs whose PLLs are controlled outside the clock controller. The display code would require the recalculated rate always.

Quoting Taniya Das (2018-07-08 20:38:03)

Quoted 43 lines

Hello Stephen,

Thanks for your review comments.

Quoted 28 lines · Stephen Boyd

Quoting Taniya Das (2018-06-23 07:19:27)

Quoted 7 lines

drivers/clk/qcom/dispcc-sdm845.c new file +1 -0

new file mode 100644
index 0000000..af437e0
@@ -0,0 +1,674 @@
+// SPDX-License-Identifier: GPL-2.0

[...]

Quoted 19 lines

drivers/clk/qcom/dispcc-sdm845.c new file +19 -0

+static struct clk_alpha_pll disp_cc_pll0 = {
+       .offset = 0x0,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+       .clkr = {
+               .hw.init = &(struct clk_init_data){
+                       .name = "disp_cc_pll0",
+                       .parent_names = (const char *[]){ "bi_tcxo" },
+                       .num_parents = 1,
+                       .ops = &clk_alpha_pll_fabia_ops,
+               },
+       },
+};
+
+static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
+       .cmd_rcgr = 0x20d0,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_0,
+       .clkr.hw.init = &(struct clk_init_data){

Quoted 9 lines

drivers/clk/qcom/dispcc-sdm845.c line 110

Quoted 4 lines

drivers/clk/qcom/dispcc-sdm845.c new file +4 -0

+               .name = "disp_cc_mdss_byte0_clk_src",
+               .parent_names = disp_cc_parent_names_0,
+               .num_parents = 4,
+               .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,

Why is there the no cache flag? Last time I asked I don't think I got any answer, and there isn't a comment here so please at least add a comment to the code so we don't forget.

Quoted 2 lines

I think you missed my comment from the earlier email. I would add the comment and submit again.

Hmm.. ok.

Quoted 4 lines

Quoted 3 lines

Why is the nocache flag needed? Applies to all clks in this file.

Quoted 3 lines

This flag is required for all RCGs whose PLLs are controlled outside the clock controller. The display code would require the recalculated rate always.

Right. Why is the PLL controlled outside of the clock controller? The rate should propagate upward to the PLL from here, so who's going outside of that?

Quoted 8 lines

Quoted 7 lines

Quoted 3 lines

Why is the nocache flag needed? Applies to all clks in this file.

This flag is required for all RCGs whose PLLs are controlled outside the clock controller. The display code would require the recalculated rate always.

Quoted 4 lines

Right. Why is the PLL controlled outside of the clock controller? The rate should propagate upward to the PLL from here, so who's going outside of that?

The DSI0/1 PLL are not part of the display clock controller, but in the display subsystem which are managed by the DRM drivers. When DRM drivers query for the rate clock driver should always return the non cached rates.

Quoting Taniya Das (2018-07-09 00:07:21)

Quoted 15 lines · Stephen Boyd

Quoted 12 lines

Quoted 7 lines

Quoted 3 lines

Why is the nocache flag needed? Applies to all clks in this file.

This flag is required for all RCGs whose PLLs are controlled outside the clock controller. The display code would require the recalculated rate always.

Right. Why is the PLL controlled outside of the clock controller? The rate should propagate upward to the PLL from here, so who's going outside of that?

Quoted 3 lines

The DSI0/1 PLL are not part of the display clock controller, but in the display subsystem which are managed by the DRM drivers. When DRM drivers query for the rate clock driver should always return the non cached rates.

Why? Is the DSI PLL changing rate all the time, randomly, without going through the clk APIs to do so?

--
To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to [email protected]
More majordomo info at http://vger.kernel.org/majordomo-info.html

Quoted 20 lines

Quoting Taniya Das (2018-07-09 00:07:21)

Quoted 18 lines · Stephen Boyd

Quoted 4 lines

Quoted 4 lines

Quoted 3 lines

Why is the nocache flag needed? Applies to all clks in this file.

Quoted 8 lines

Quoted 3 lines

This flag is required for all RCGs whose PLLs are controlled outside the clock controller. The display code would require the recalculated rate always.

Right. Why is the PLL controlled outside of the clock controller? The rate should propagate upward to the PLL from here, so who's going outside of that?

The DSI0/1 PLL are not part of the display clock controller, but in the display subsystem which are managed by the DRM drivers. When DRM drivers query for the rate clock driver should always return the non cached rates.

Quoted 3 lines

Why? Is the DSI PLL changing rate all the time, randomly, without going through the clk APIs to do so?

Hmm, I am afraid I do not have an answer for this, but this was the requirement to always return the non cached rates from the clock driver.

Quoting Taniya Das (2018-07-09 02:34:07)

Quoted 27 lines · Stephen Boyd

Quoted 23 lines

Quoting Taniya Das (2018-07-09 00:07:21)

Quoted 11 lines · Stephen Boyd

Quoted 8 lines

Quoted 7 lines

Quoted 3 lines

Why is the nocache flag needed? Applies to all clks in this file.

This flag is required for all RCGs whose PLLs are controlled outside the clock controller. The display code would require the recalculated rate always.

Quoted 7 lines

Quoted 4 lines

Right. Why is the PLL controlled outside of the clock controller? The rate should propagate upward to the PLL from here, so who's going outside of that?

The DSI0/1 PLL are not part of the display clock controller, but in the display subsystem which are managed by the DRM drivers. When DRM drivers query for the rate clock driver should always return the non cached rates.

Why? Is the DSI PLL changing rate all the time, randomly, without going through the clk APIs to do so?

Quoted 3 lines

Hmm, I am afraid I do not have an answer for this, but this was the requirement to always return the non cached rates from the clock driver.

Ok. Who knows about this requirement? Can we add someone from the display driver to understand more?

++ Display driver team,

Quoted 28 lines · Stephen Boyd

Quoting Taniya Das (2018-07-09 02:34:07)

Quoted 27 lines · Stephen Boyd

Quoted 23 lines

Quoting Taniya Das (2018-07-09 00:07:21)

Quoted 11 lines · Stephen Boyd

Quoted 8 lines

Quoted 7 lines

Quoted 3 lines

Why is the nocache flag needed? Applies to all clks in this file.

This flag is required for all RCGs whose PLLs are controlled outside the clock controller. The display code would require the recalculated rate always.

Quoted 7 lines

Quoted 4 lines

Right. Why is the PLL controlled outside of the clock controller? The rate should propagate upward to the PLL from here, so who's going outside of that?

The DSI0/1 PLL are not part of the display clock controller, but in the display subsystem which are managed by the DRM drivers. When DRM drivers query for the rate clock driver should always return the non cached rates.

Why? Is the DSI PLL changing rate all the time, randomly, without going through the clk APIs to do so?

Quoted 7 lines

Quoted 3 lines

Hmm, I am afraid I do not have an answer for this, but this was the requirement to always return the non cached rates from the clock driver.

Ok. Who knows about this requirement? Can we add someone from the display driver to understand more?

As per my discussions offline with the display teams,

There is a use-case where the clock framework is unaware of the PLL VCO frequency change and thus the drivers would query to get the actual HW frequency rather than the cached one.

Do you think keeping these flags would have any impact other than always getting the non-cached rates?

Quoting Taniya Das (2018-07-12 10:21:33)

Quoted 38 lines

++ Display driver team,

Quoted 28 lines · Stephen Boyd

Quoting Taniya Das (2018-07-09 02:34:07)

Quoted 27 lines · Stephen Boyd

Quoted 23 lines

Quoting Taniya Das (2018-07-09 00:07:21)

Quoted 11 lines · Stephen Boyd

Quoted 8 lines

Quoted 7 lines

Quoted 3 lines

Why is the nocache flag needed? Applies to all clks in this file.

This flag is required for all RCGs whose PLLs are controlled outside the clock controller. The display code would require the recalculated rate always.

Quoted 7 lines

Quoted 4 lines

Right. Why is the PLL controlled outside of the clock controller? The rate should propagate upward to the PLL from here, so who's going outside of that?

The DSI0/1 PLL are not part of the display clock controller, but in the display subsystem which are managed by the DRM drivers. When DRM drivers query for the rate clock driver should always return the non cached rates.

Why? Is the DSI PLL changing rate all the time, randomly, without going through the clk APIs to do so?

Quoted 7 lines

Quoted 3 lines

Hmm, I am afraid I do not have an answer for this, but this was the requirement to always return the non cached rates from the clock driver.

Ok. Who knows about this requirement? Can we add someone from the display driver to understand more?

Quoted 9 lines

As per my discussions offline with the display teams,

There is a use-case where the clock framework is unaware of the PLL VCO frequency change and thus the drivers would query to get the actual HW frequency rather than the cached one.

Do you think keeping these flags would have any impact other than always getting the non-cached rates?

The flag will make it so clk_get_rate() works in spite of something changing the frequency behind the framework's back, but I want to understand what and why it's changing without framework involvement. We shouldn't need the flag here, because this flag is typically for clks that are controlled by some other entity that the kernel doesn't have control over. In this case, it seems like we have full control of the clk tree for the display PLL down to this clk, so it should be perfectly fine to not have this flag. The presence of the flag means that the display driver is doing something wrong.

Quoted 58 lines · Stephen Boyd

Quoting Taniya Das (2018-07-12 10:21:33)

Quoted 47 lines

++ Display driver team,

Quoted 10 lines · Stephen Boyd

Quoting Taniya Das (2018-07-09 02:34:07)

Quoted 9 lines · Stephen Boyd

Quoted 6 lines

Quoting Taniya Das (2018-07-09 00:07:21)

Quoted 5 lines · Stephen Boyd

Quoted 2 lines

Quoted 2 lines

     > Why is the nocache flag needed? Applies to all clks in

this file.

Quoted 3 lines

Quoted 3 lines

Quoted 3 lines

Quoted 3 lines

Quoted 3 lines

Quoted 3 lines

     >

This flag is required for all RCGs whose PLLs are controlled

outside the

Quoted 1 line

Quoted 1 line

Quoted 1 line

Quoted 1 line

Quoted 1 line

Quoted 1 line

clock controller. The display code would require the

recalculated rate

Quoted 3 lines

Quoted 3 lines

Quoted 3 lines

Quoted 3 lines

Quoted 3 lines

Quoted 1 line

always.

Right. Why is the PLL controlled outside of the clock

controller? The

Quoted 4 lines

Quoted 4 lines

Quoted 4 lines

Quoted 4 lines

Quoted 3 lines

rate should propagate upward to the PLL from here, so who's going outside of that?

The DSI0/1 PLL are not part of the display clock controller, but

in the

Quoted 1 line

Quoted 1 line

Quoted 1 line

Quoted 1 line

display subsystem which are managed by the DRM drivers. When DRM

drivers

Quoted 1 line

Quoted 1 line

Quoted 1 line

Quoted 1 line

query for the rate clock driver should always return the non

cached rates.

Quoted 2 lines

Quoted 2 lines

Quoted 2 lines

Why? Is the DSI PLL changing rate all the time, randomly, without

going

Quoted 5 lines

Quoted 5 lines

Quoted 2 lines

through the clk APIs to do so?

Hmm, I am afraid I do not have an answer for this, but this was the requirement to always return the non cached rates from the clock

driver.

Quoted 5 lines

Quoted 1 line

Ok. Who knows about this requirement? Can we add someone from the display driver to understand more?

Quoted 9 lines

As per my discussions offline with the display teams,

There is a use-case where the clock framework is unaware of the PLL VCO frequency change and thus the drivers would query to get the actual HW frequency rather than the cached one.

Do you think keeping these flags would have any impact other than always getting the non-cached rates?

Quoted 9 lines

The flag will make it so clk_get_rate() works in spite of something changing the frequency behind the framework's back, but I want to understand what and why it's changing without framework involvement. We shouldn't need the flag here, because this flag is typically for clks that are controlled by some other entity that the kernel doesn't have control over. In this case, it seems like we have full control of the clk tree for the display PLL down to this clk, so it should be perfectly fine to not have this flag. The presence of the flag means that the display driver is doing something wrong.

These clocks are sourced from DSI PLL. In dsi command mode there is an idle use case when there is no activity on display, we switch of the source DSI PLL to save power by calling clk_disable_unprepare(). In this scenario if some client queries the clk_get_rate(), then if NO_CACHE flag is used the clk driver will return the cached rate which is some non-zero value set when we last called clk_set_rate(), before enabling the clock, whereas actually in HW this clk is disabled. So we used the NO_CACHE flag for the call to land in clk_recalc_rate and we return zero if the PLL is disabled.
I remember some customer had scripts that runs through all the clocks during idle screen scenario and call clk_get_rate(), where they complained display clk_get_rate returns none zero value.

Signature · 3 lines

To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
the body of a message to [email protected]
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Quoted 51 lines

Quoting Taniya Das (2018-07-12 10:21:33)

Quoted 40 lines

++ Display driver team,

Quoted 28 lines · Stephen Boyd

Quoting Taniya Das (2018-07-09 02:34:07)

Quoted 27 lines · Stephen Boyd

Quoted 23 lines

Quoting Taniya Das (2018-07-09 00:07:21)

Quoted 11 lines · Stephen Boyd

Quoted 8 lines

Quoted 7 lines

Quoted 3 lines

Why is the nocache flag needed? Applies to all clks in this file.

This flag is required for all RCGs whose PLLs are controlled outside the clock controller. The display code would require the recalculated rate always.

Quoted 7 lines

Quoted 4 lines

Right. Why is the PLL controlled outside of the clock controller? The rate should propagate upward to the PLL from here, so who's going outside of that?

The DSI0/1 PLL are not part of the display clock controller, but in the display subsystem which are managed by the DRM drivers. When DRM drivers query for the rate clock driver should always return the non cached rates.

Why? Is the DSI PLL changing rate all the time, randomly, without going through the clk APIs to do so?

Quoted 7 lines

Quoted 3 lines

Hmm, I am afraid I do not have an answer for this, but this was the requirement to always return the non cached rates from the clock driver.

Ok. Who knows about this requirement? Can we add someone from the display driver to understand more?

As per my discussions offline with the display teams,

Quoted 9 lines

There is a use-case where the clock framework is unaware of the PLL VCO
frequency change and thus the drivers would query to get the actual HW frequency rather than the cached one.

Do you think keeping these flags would have any impact other than always
getting the non-cached rates?

Quoted 10 lines

The flag will make it so clk_get_rate() works in spite of something changing the frequency behind the framework's back, but I want to understand what and why it's changing without framework involvement. We shouldn't need the flag here, because this flag is typically for clks that are controlled by some other entity that the kernel doesn't have control over. In this case, it seems like we have full control of the clk tree for the display PLL down to this clk, so it should be perfectly
fine to not have this flag. The presence of the flag means that the display driver is doing something wrong.

These clocks are sourced from DSI PLL. In dsi command mode there is an idle use case when there
is no activity on display, we switch of the source DSI PLL to save power by calling clk_disable_unprepare().
In this scenario if some client queries the clk_get_rate(), then if NO_CACHE flag is used the clk
driver will return the cached rate which is some non-zero value set when we last called clk_set_rate(),
before enabling the clock, whereas actually in HW this clk is disabled.

So we used the NO_CACHE flag
for the call to land in clk_recalc_rate and we return zero if the PLL is disabled.