Add support for LPASS clock controller for SDM845
v4 cover Add support for LPASS clock controller for SDM845
[v4]
* Update the description in GCC Documentation binding for 'qcom,lpass-protected'.
* Remove 'qcom,lpass-protected' from LPASS Documentation binding.
* Update KConfig to use Low Power Audio Subsystem.
* Add module_exit() and also update return value for devm_ioremap_resource failure.
[v3]
* Add a device tree property to identify lpass protected GCC clocks.
* Update the GCC driver code to register the lpass clocks when the flag is defined.
* Add comment for clocks using the BRANCH_HALT_SKIP flag.
* Use platform APIs instead of of_address_to_resource.
* Replace devm_ioremap with devm_ioremap_resource.
* Use fixed index for 'lpass_cc' & 'lpass_qdsp6ss' in probe.
[v2]
* Make gcc_lpass_sway_clk static.
* Remove using child nodes and use reg-names to differentiate various domains of LPASS CC.
Add support for the lpass clock controller found on SDM845 based devices. This would allow lpass peripheral loader drivers to control the clocks to bring the subsystem out of reset.
Taniya Das (2):
dt-bindings: clock: Introduce QCOM LPASS clock bindings
clk: qcom: Add lpass clock controller driver for SDM845
.../devicetree/bindings/clock/qcom,gcc.txt | 2 + .../devicetree/bindings/clock/qcom,lpasscc.txt | 31 ++++ drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-sdm845.c | 35 ++++ drivers/clk/qcom/lpasscc-sdm845.c | 195 +++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sdm845.h | 2 + include/dt-bindings/clock/qcom,lpass-sdm845.h | 16 ++ 8 files changed, 291 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,lpasscc.txt create mode 100644 drivers/clk/qcom/lpasscc-sdm845.c create mode 100644 include/dt-bindings/clock/qcom,lpass-sdm845.h
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Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
PATCH v4 1/2 dt-bindings: clock: Introduce QCOM LPASS clock bindings
Add device tree bindings for Low Power Audio subsystem clock controller for Qualcomm Technology Inc's SDM845 SoCs.
--- .../devicetree/bindings/clock/qcom,gcc.txt | 2 ++ .../devicetree/bindings/clock/qcom,lpasscc.txt | 31 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sdm845.h | 2 ++ include/dt-bindings/clock/qcom,lpass-sdm845.h | 16 +++++++++++ 4 files changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,lpasscc.txt create mode 100644 include/dt-bindings/clock/qcom,lpass-sdm845.h
Documentation/devicetree/bindings/clock/qcom,gcc.txt +2 -0
@@ -32,6 +32,8 @@ be part of GCC and hence the TSENS properties can also be part of the GCC/clock-controller node. For more details on the TSENS properties please refer Documentation/devicetree/bindings/thermal/qcom-tsens.txt +- qcom,lpass-protected : Indicate that the LPASS clock branches within GCC are + unusable due to firmware access control restrictions. Example: clock-controller@900000 {
Documentation/devicetree/bindings/clock/qcom,lpasscc.txt new file +31 -0
@@ -0,0 +1,31 @@ +Qualcomm LPASS Clock Controller Binding +----------------------------------------------- + +Required properties : +- compatible : shall contain "qcom,sdm845-lpasscc" +- #clock-cells : from common clock binding, shall contain 1. +- reg : shall contain base register address and size, + in the order + Index-0 maps to LPASS_CC register region + Index-1 maps to LPASS_QDSP6SS register region + +Optional properties : +- reg-names : register names of LPASS domain + "lpass_cc", "lpass_qdsp6ss". + +Example: + +The below node has to be defined in the cases where the LPASS peripheral loader +would bring the subsystem out of reset. + + lpasscc: clock-controller { + compatible = "qcom,sdm845-lpasscc"; + reg = <0x17014000 0x1f004>, <0x17300000 0x200>; + reg-names = "lpass_cc", "lpass_qdsp6ss"; + #clock-cells = <1>; + }; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sdm845"; + qcom,lpass-protected; + };
include/dt-bindings/clock/qcom,gcc-sdm845.h +2 -0
@@ -197,6 +197,8 @@#define GCC_QSPI_CORE_CLK_SRC 187#define GCC_QSPI_CORE_CLK 188#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189 +#define GCC_LPASS_Q6_AXI_CLK 190 +#define GCC_LPASS_SWAY_CLK 191/* GCC Resets */ #define GCC_MMSS_BCR 0
include/dt-bindings/clock/qcom,lpass-sdm845.h new file +16 -0
@@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright (c) 2018, The Linux Foundation. All rights reserved. +*/ + +#ifndef _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H +#define _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H + +#define LPASS_AUDIO_WRAPPER_AON_CLK 0 +#define LPASS_Q6SS_AHBM_AON_CLK 1 +#define LPASS_Q6SS_AHBS_AON_CLK 2 +#define LPASS_QDSP6SS_XO_CLK 3 +#define LPASS_QDSP6SS_SLEEP_CLK 4 +#define LPASS_QDSP6SS_CORE_CLK 5 + +#endif
Signature · 2 lines
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
Rob Herring
maintainerRe: [PATCH 1/2] dt-bindings: clock: Introduce QCOM LPASS clock bindings
Quoted 36 lines · Taniya Das
Add device tree bindings for Low Power Audio subsystem clock controller for Qualcomm Technology Inc's SDM845 SoCs.
Signed-off-by Taniya Das <[email protected]>--- .../devicetree/bindings/clock/qcom,gcc.txt | 2 ++ .../devicetree/bindings/clock/qcom,lpasscc.txt | 31 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sdm845.h | 2 ++ include/dt-bindings/clock/qcom,lpass-sdm845.h | 16 +++++++++++ 4 files changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,lpasscc.txt create mode 100644 include/dt-bindings/clock/qcom,lpass-sdm845.hDocumentation/devicetree/bindings/clock/qcom,gcc.txt +2
-0@@ -32,6 +32,8 @@ be part of GCC and hence the TSENS properties can also be part of the GCC/clock-controller node. For more details on the TSENS properties please refer Documentation/devicetree/bindings/thermal/qcom-tsens.txt +- qcom,lpass-protected : Indicate that the LPASS clock branches within GCC are + unusable due to firmware access control restrictions. Example: clock-controller@900000 {Documentation/devicetree/bindings/clock/qcom,lpasscc.txt new file +4
-0@@ -0,0 +1,31 @@ +Qualcomm LPASS Clock Controller Binding +----------------------------------------------- + +Required properties :
Documentation/devicetree/bindings/clock/qcom,lpasscc.txt line 14
Quoted 10 lines
Documentation/devicetree/bindings/clock/qcom,lpasscc.txt new file +10
-0+- compatible : shall contain "qcom,sdm845-lpasscc" +- #clock-cells : from common clock binding, shall contain 1. +- reg : shall contain base register address and size, + in the order + Index-0 maps to LPASS_CC register region + Index-1 maps to LPASS_QDSP6SS register region + +Optional properties : +- reg-names : register names of LPASS domain + "lpass_cc", "lpass_qdsp6ss".
"cc" and "qdsp6ss" is sufficient.
Documentation/devicetree/bindings/clock/qcom,lpasscc.txt line 21
Quoted 7 lines
Documentation/devicetree/bindings/clock/qcom,lpasscc.txt new file +7
-0+ +Example: + +The below node has to be defined in the cases where the LPASS peripheral loader +would bring the subsystem out of reset. + + lpasscc: clock-controller {
Needs a unit-address.
Documentation/devicetree/bindings/clock/qcom,lpasscc.txt line 28
Quoted 7 lines
Documentation/devicetree/bindings/clock/qcom,lpasscc.txt new file +7
-0+ compatible = "qcom,sdm845-lpasscc"; + reg = <0x17014000 0x1f004>, <0x17300000 0x200>; + reg-names = "lpass_cc", "lpass_qdsp6ss"; + #clock-cells = <1>; + }; + + gcc: clock-controller@100000 {
This needs a reg property.
Quoted 43 lines
Documentation/devicetree/bindings/clock/qcom,lpasscc.txt new file +3
-0+ compatible = "qcom,gcc-sdm845"; + qcom,lpass-protected; + };include/dt-bindings/clock/qcom,gcc-sdm845.h +2
-0@@ -197,6 +197,8 @@#define GCC_QSPI_CORE_CLK_SRC 187#define GCC_QSPI_CORE_CLK 188#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189 +#define GCC_LPASS_Q6_AXI_CLK 190 +#define GCC_LPASS_SWAY_CLK 191/* GCC Resets */ #define GCC_MMSS_BCR 0include/dt-bindings/clock/qcom,lpass-sdm845.h new file +16
-0@@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright (c) 2018, The Linux Foundation. All rights reserved. +*/ + +#ifndef _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H +#define _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H + +#define LPASS_AUDIO_WRAPPER_AON_CLK 0 +#define LPASS_Q6SS_AHBM_AON_CLK 1 +#define LPASS_Q6SS_AHBS_AON_CLK 2 +#define LPASS_QDSP6SS_XO_CLK 3 +#define LPASS_QDSP6SS_SLEEP_CLK 4 +#define LPASS_QDSP6SS_CORE_CLK 5 + +#endif Signature · 2 lines
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
Re: [PATCH 1/2] dt-bindings: clock: Introduce QCOM LPASS clock bindings
Hello Rob,
Thanks for the review comments.
Quoted 41 lines · Rob Herring
Quoted 40 lines · Taniya Das
Add device tree bindings for Low Power Audio subsystem clock controller for Qualcomm Technology Inc's SDM845 SoCs.
Signed-off-by Taniya Das <[email protected]>--- .../devicetree/bindings/clock/qcom,gcc.txt | 2 ++ .../devicetree/bindings/clock/qcom,lpasscc.txt | 31 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sdm845.h | 2 ++ include/dt-bindings/clock/qcom,lpass-sdm845.h | 16 +++++++++++ 4 files changed, 51 insertions(+)create mode 100644
Documentation/devicetree/bindings/clock/qcom,lpasscc.txtcreate mode 100644include/dt-bindings/clock/qcom,lpass-sdm845.hDocumentation/devicetree/bindings/clock/qcom,gcc.txt +2
-0@@ -32,6 +32,8 @@ be part of GCC and hence the TSENS properties can also be part of the GCC/clock-controller node. For more details on the TSENS properties please refer Documentation/devicetree/bindings/thermal/qcom-tsens.txt +- qcom,lpass-protected : Indicate that the LPASS clock branches within GCC are + unusable due to firmware access control restrictions. Example: clock-controller@900000 {Documentation/devicetree/bindings/clock/qcom,lpasscc.txt new file +8
-0@@ -0,0 +1,31 @@ +Qualcomm LPASS Clock Controller Binding +----------------------------------------------- + +Required properties : +- compatible : shall contain "qcom,sdm845-lpasscc" +- #clock-cells : from common clock binding, shall contain 1. +- reg : shall contain base register address and size, + in the order
Quoted 9 lines
Documentation/devicetree/bindings/clock/qcom,lpasscc.txt line 14
Quoted 6 lines
Documentation/devicetree/bindings/clock/qcom,lpasscc.txt new file +6
-0+ Index-0 maps to LPASS_CC register region + Index-1 maps to LPASS_QDSP6SS register region + +Optional properties : +- reg-names : register names of LPASS domain + "lpass_cc", "lpass_qdsp6ss"."cc" and "qdsp6ss" is sufficient.
Sure will update in the next patch series.
Quoted 10 lines
Documentation/devicetree/bindings/clock/qcom,lpasscc.txt line 21
Quoted 7 lines
Documentation/devicetree/bindings/clock/qcom,lpasscc.txt new file +7
-0+ +Example: + +The below node has to be defined in the cases where the LPASS peripheral loader +would bring the subsystem out of reset. + + lpasscc: clock-controller {Needs a unit-address.
Yes, my mistake. Missed adding it.
Quoted 10 lines
Documentation/devicetree/bindings/clock/qcom,lpasscc.txt line 28
Quoted 7 lines
Documentation/devicetree/bindings/clock/qcom,lpasscc.txt new file +7
-0+ compatible = "qcom,sdm845-lpasscc"; + reg = <0x17014000 0x1f004>, <0x17300000 0x200>; + reg-names = "lpass_cc", "lpass_qdsp6ss"; + #clock-cells = <1>; + }; + + gcc: clock-controller@100000 {This needs a reg property.
Sure, will update the same.
Quoted 44 lines
Quoted 43 lines
Documentation/devicetree/bindings/clock/qcom,lpasscc.txt new file +3
-0+ compatible = "qcom,gcc-sdm845"; + qcom,lpass-protected; + };include/dt-bindings/clock/qcom,gcc-sdm845.h +2
-0@@ -197,6 +197,8 @@#define GCC_QSPI_CORE_CLK_SRC 187#define GCC_QSPI_CORE_CLK 188#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189 +#define GCC_LPASS_Q6_AXI_CLK 190 +#define GCC_LPASS_SWAY_CLK 191/* GCC Resets */ #define GCC_MMSS_BCR 0include/dt-bindings/clock/qcom,lpass-sdm845.h new file +16
-0@@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright (c) 2018, The Linux Foundation. All rights reserved. +*/ + +#ifndef _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H +#define _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H + +#define LPASS_AUDIO_WRAPPER_AON_CLK 0 +#define LPASS_Q6SS_AHBM_AON_CLK 1 +#define LPASS_Q6SS_AHBS_AON_CLK 2 +#define LPASS_QDSP6SS_XO_CLK 3 +#define LPASS_QDSP6SS_SLEEP_CLK 4 +#define LPASS_QDSP6SS_CORE_CLK 5 + +#endif Signature · 2 lines
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
Signature · 4 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation. --
PATCH v4 2/2 clk: qcom: Add lpass clock controller driver for SDM845
In reply to Taniya DasAdd support for the lpass clock controller found on SDM845 based devices. This would allow lpass peripheral loader drivers to control the clocks to bring the subsystem out of reset.
LPASS clocks present on the global clock controller would be registered with the clock framework based on the device tree flag.
--- drivers/clk/qcom/Kconfig | 9 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-sdm845.c | 35 +++++++ drivers/clk/qcom/lpasscc-sdm845.c | 195 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 240 insertions(+) create mode 100644 drivers/clk/qcom/lpasscc-sdm845.c
drivers/clk/qcom/Kconfig +9 -0
@@ -272,6 +272,15 @@ config SDM_DISPCC_845 Say Y if you want to support display devices and functionality such as splash screen. +config SDM_LPASSCC_845 + tristate "SDM845 Low Power Audio Subsystem (LPAAS) Clock Controller" + depends on COMMON_CLK_QCOM + select SDM_GCC_845 + help + Support for the LPASS clock controller on SDM845 devices. + Say Y if you want to use the LPASS branch clocks of the LPASS clock + controller to reset the LPASS subsystem. + config SPMI_PMIC_CLKDIV tristate "SPMI PMIC clkdiv Support" depends on (COMMON_CLK_QCOM && SPMI) || COMPILE_TEST
drivers/clk/qcom/Makefile +1 -0
@@ -42,5 +42,6 @@ obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o +obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
drivers/clk/qcom/gcc-sdm845.c +35 -0
@@ -3169,6 +3169,32 @@ enum { }, }; +static struct clk_branch gcc_lpass_q6_axi_clk = { + .halt_reg =0x47000 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x47000 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_lpass_q6_axi_clk" , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_lpass_sway_clk = { + .halt_reg =0x47008 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x47008 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_lpass_sway_clk" , + .ops = &clk_branch2_ops, + }, + }, +}; +static struct gdsc pcie_0_gdsc = { .gdscr =0x6b004 , .pd = {
@@ -3469,6 +3495,8 @@ enum { [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, + [GCC_LPASS_Q6_AXI_CLK] = NULL, + [GCC_LPASS_SWAY_CLK] = NULL, };static const struct qcom_reset_map gcc_sdm845_resets[] = {
@@ -3583,6 +3611,13 @@ static int gcc_sdm845_probe(struct platform_device *pdev)if (ret)return ret; +if (of_property_read_bool (pdev->dev.of_node,"qcom,lpass-protected" )) { + gcc_sdm845_clocks[GCC_LPASS_Q6_AXI_CLK ] = + &gcc_lpass_q6_axi_clk.clkr; + gcc_sdm845_clocks[GCC_LPASS_SWAY_CLK ] = + &gcc_lpass_sway_clk.clkr; + } +return qcom_cc_really_probe (pdev, &gcc_sdm845_desc, regmap); }
drivers/clk/qcom/lpasscc-sdm845.c new file +195 -0
195 lines not on this page · raw message
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