Guest LBR Enabling

arch/x86/events/intel/lbr.c +13 -0

index c88ed39..c81f160 100644
@@ -1277,3 +1277,26 @@ void intel_pmu_lbr_init_knl(void)
 	if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_LIP)
 		x86_pmu.intel_cap.lbr_format = LBR_FORMAT_EIP_FLAGS;
 }
+
+/**
+ * perf_get_lbr_stack - get the lbr stack related MSRs
+ *
+ * @stack: the caller's memory to get the lbr stack
+ *
+ * Returns: 0 indicates that the lbr stack has been successfully obtained.
+ */
+int perf_get_lbr_stack(struct perf_lbr_stack *stack)
+{
+	stack->nr = x86_pmu.lbr_nr;
+	stack->tos = x86_pmu.lbr_tos;
+	stack->from = x86_pmu.lbr_from;

The LBR stack MSRs are architecturally specific. The perf subsystem has already assigned the abstracted MSR values based on the CPU architecture.

This patch enables a caller outside the perf subsystem to get the LBR stack info. This is useful for hyperviosrs to prepare the lbr feature for the guest.

Signed-off-by Like Xu <[email protected]>

Signed-off-by Wei Wang <[email protected]>

Bits [0, 5] of MSR_IA32_PERF_CAPABILITIES tell about the format of the addresses stored in the LBR stack. Expose those bits to the guest when the guest lbr feature is enabled.

Signed-off-by Like Xu <[email protected]>

Signed-off-by Wei Wang <[email protected]>

Cc Paolo Bonzini <[email protected]>

Cc Andi Kleen <[email protected]>

---
  arch/x86/include/asm/perf_event.h | 2 ++
  arch/x86/kvm/cpuid.c              | 2 +-
  arch/x86/kvm/vmx.c                | 7 +++++++
  3 files changed, 10 insertions(+), 1 deletion(-)

arch/x86/include/asm/perf_event.h +2 -0

index 84cc8cb..e893a69 100644
@@ -79,6 +79,8 @@
  #define ARCH_PERFMON_BRANCH_MISSES_RETIRED		6
  #define ARCH_PERFMON_EVENTS_COUNT			7
 
+#define PERF_CAP_MASK_LBR_FMT				0x3f
+
  /*
   * Intel "Architectural Performance Monitoring" CPUID
   * detection/enumeration details:

arch/x86/kvm/cpuid.c +1 -1

index 7bcfa61..3b8a57b 100644
@@ -365,7 +365,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
  		F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
  		0 /* DS-CPL, VMX, SMX, EST */ |
  		0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
-		F(FMA) | F(CX16) | 0 /* xTPR Update, PDCM */ |
+		F(FMA) | F(CX16) | 0 /* xTPR Update*/ | F(PDCM) |
  		F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) |
  		F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
  		0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |

arch/x86/kvm/vmx.c +0 -0

index 533a327..92705b5 100644

arch/x86/kvm/pmu_intel.c +0 -0

index 5ab4a36..97a29d7 100644

arch/x86/kvm/pmu_intel.c +14 -0

+
+	if (pmu->guest_lbr_event)
+		return 0;
+
+	event = perf_event_create_kernel_counter(&attr, -1, current, NULL,
+						 NULL);
+	if (IS_ERR(event)) {
+		pr_err("%s: failed %ld\n", __func__, PTR_ERR(event));
+		return -ENOENT;
+	}
+	pmu->guest_lbr_event = event;
+
+	return 0;
+}

On Thu, Sep 20, 2018 at 06:05:58PM +0800, Wei Wang wrote:
How do you deal with that situation, where the LBR is in use by a host event?

Quoted 7 lines

arch/x86/kvm/pmu_intel.c +7 -0

+int intel_pmu_enable_save_guest_lbr(struct kvm_vcpu *vcpu)
+{
+	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
+	struct perf_event *event;
+	struct perf_event_attr attr = {
+		.type = PERF_TYPE_RAW,
+		.size = sizeof(attr),

arch/x86/kvm/pmu_intel.c static void intel_pmu_reset(struct kvm_vcpu *vcpu) · line 357

Quoted 6 lines

arch/x86/kvm/pmu_intel.c +6 -0

+		.pinned = true,
+		.exclude_host = true,
+		.sample_type = PERF_SAMPLE_BRANCH_STACK,
+		.branch_sample_type = PERF_SAMPLE_BRANCH_CALL_STACK |
+				      PERF_SAMPLE_BRANCH_USER |
+				      PERF_SAMPLE_BRANCH_KERNEL,

I think that will allocate an extra perfmon counter, right?

Quoted 10 lines · Andi Kleen

arch/x86/kvm/pmu_intel.c static void intel_pmu_reset(struct kvm_vcpu *vcpu)

Quoted 10 lines

arch/x86/kvm/pmu_intel.c +10 -0

+int intel_pmu_enable_save_guest_lbr(struct kvm_vcpu *vcpu) {
+	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
+	struct perf_event *event;
+	struct perf_event_attr attr = {
+		.type = PERF_TYPE_RAW,
+		.size = sizeof(attr),
+		.pinned = true,
+		.exclude_host = true,
+		.sample_type = PERF_SAMPLE_BRANCH_STACK,
+		.branch_sample_type = PERF_SAMPLE_BRANCH_CALL_STACK

|

Quoted 4 lines

arch/x86/kvm/pmu_intel.c static void intel_pmu_reset(struct kvm_vcpu *vcpu) · line 357

Quoted 2 lines

arch/x86/kvm/pmu_intel.c +2 -0

+				      PERF_SAMPLE_BRANCH_USER |
+				      PERF_SAMPLE_BRANCH_KERNEL,

I think that will allocate an extra perfmon counter, right?

I throught the same too, but I think the exclude_host/guest, whichever is the right one makes that work for regular counters too.

That code is a wee bit magical and I didn't take the time to reverse engineer that. It most certainly needs a comment.

arch/x86/kvm/pmu_intel.c static void intel_pmu_reset(struct kvm_vcpu *vcpu)

Quoted 10 lines

arch/x86/kvm/pmu_intel.c +10 -0

+int intel_pmu_enable_save_guest_lbr(struct kvm_vcpu *vcpu) {
+	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
+	struct perf_event *event;
+	struct perf_event_attr attr = {
+		.type = PERF_TYPE_RAW,
+		.size = sizeof(attr),
+		.pinned = true,
+		.exclude_host = true,
+		.sample_type = PERF_SAMPLE_BRANCH_STACK,
+		.branch_sample_type = PERF_SAMPLE_BRANCH_CALL_STACK

|

arch/x86/kvm/pmu_intel.c static void intel_pmu_reset(struct kvm_vcpu *vcpu) · line 357

Quoted 2 lines

arch/x86/kvm/pmu_intel.c +2 -0

+				      PERF_SAMPLE_BRANCH_USER |
+				      PERF_SAMPLE_BRANCH_KERNEL,

I think that will allocate an extra perfmon counter, right?

So if the guest wants to use all perfmon counters we would start to multiplex, which would be bad

Would need to fix perf core to not allocate a perfmon counter in this case, if no period and no event count is requested.

-----Original Message-----
From: Wei Wang [mailto:[email protected]]
Sent: Thursday, September 20, 2018 6:06 PM
To: [email protected]; [email protected]; [email protected]; [email protected]
Cc: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Gonglei (Arei) <[email protected]>
Subject: [PATCH v3 5/5] KVM/x86/lbr: lazy save the guest lbr stack

When the vCPU is scheduled in:
- if the lbr feature was used in the last vCPU time slice, set the lbr stack to be interceptible, so that the host can capture whether the lbr feature will be used in this time slice;
- if the lbr feature wasn't used in the last vCPU time slice, disable the vCPU support of the guest lbr switching.

Upon the first access to one of the lbr related MSRs (since the vCPU was scheduled in):
- record that the guest has used the lbr;
- create a host perf event to help save/restore the guest lbr stack if the guest uses the user callstack mode lbr stack;
- pass the stack through to the guest.

Suggested-by Andi Kleen <[email protected]>

Signed-off-by Like Xu <[email protected]>

Signed-off-by Wei Wang <[email protected]>

Cc Paolo Bonzini <[email protected]>

Cc Andi Kleen <[email protected]>

---
 arch/x86/events/intel/lbr.c       |  16 +++++
 arch/x86/include/asm/kvm_host.h   |   4 ++
 arch/x86/include/asm/perf_event.h |   6 ++
 arch/x86/kvm/pmu.h                |   5 ++
 arch/x86/kvm/vmx.c                | 137
++++++++++++++++++++++++++++++++++++++
 5 files changed, 168 insertions(+)

arch/x86/events/intel/lbr.c +16 -0

index 915fcc3..a260015 100644
@@ -64,6 +64,7 @@ static const enum {
 #define LBR_NO_INFO	(1ULL << LBR_NO_INFO_BIT)
 
 #define LBR_PLM (LBR_KERNEL | LBR_USER)
+#define LBR_USER_CALLSTACK (LBR_CALL_STACK | LBR_USER)
 
 #define LBR_SEL_MASK	0x3ff	/* valid bits in LBR_SELECT */
 #define LBR_NOT_SUPP	-1	/* LBR filter not supported */

@@ -1283,6 +1284,21 @@ void intel_pmu_lbr_init_knl(void)
 }
 
 /**
+ * lbr_select_user_callstack - check if the user callstack mode is set
+ *
+ * @lbr_select: the lbr select msr
+ *
+ * Returns: true if the msr is configured to the user callstack mode.
+ * Otherwise, false.
+ *
+ */
+bool lbr_select_user_callstack(u64 lbr_select)
+{
+	return !!(lbr_select & LBR_USER_CALLSTACK);
+}
+EXPORT_SYMBOL_GPL(lbr_select_user_callstack);
+
+/**
  * perf_get_lbr_stack - get the lbr stack related MSRs
  *
  * @stack: the caller's memory to get the lbr stack

arch/x86/include/asm/kvm_host.h +4 -0

index fdcac01..41b4d29 100644
@@ -730,6 +730,10 @@ struct kvm_vcpu_arch {
 
 	/* Flush the L1 Data cache for L1TF mitigation on VMENTER */
 	bool l1tf_flush_l1d;
+	/* Indicate if the guest is using lbr with the user callstack mode */
+	bool lbr_user_callstack;
+	/* Indicate if the lbr msrs were accessed in this vCPU time slice */
+	bool lbr_used;
 };
 
 struct kvm_lpage_info {

arch/x86/include/asm/perf_event.h +6 -0

index e893a69..2d7ae55 100644
@@ -277,6 +277,7 @@ struct perf_lbr_stack {
 	unsigned long	info;
 };
 
+extern bool lbr_select_user_callstack(u64 msr_lbr_select);
 extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr);
 extern int perf_get_lbr_stack(struct perf_lbr_stack *stack);
 extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);

@@ -288,6 +289,11 @@ static inline struct perf_guest_switch_msr
 *perf_guest_get_msrs(int *nr)
 	return NULL;
 }
 
+static bool lbr_select_user_callstack(u64 msr_lbr_select)
+{
+	return false;
+}
+
 static inline int perf_get_lbr_stack(struct perf_lbr_stack *stack)
 {

arch/x86/include/asm/perf_event.h +0 -0

 	return -1;

arch/x86/kvm/pmu.h +5 -0

index e872aed..94f0624 100644
@@ -102,6 +102,11 @@ static inline struct kvm_pmc *get_fixed_pmc(struct
 kvm_pmu *pmu, u32 msr)
 	return NULL;
 }
 
+static inline bool intel_pmu_save_guest_lbr_enabled(struct kvm_vcpu *vcpu)
+{
+	return !!vcpu_to_pmu(vcpu)->guest_lbr_event;
+}
+
 void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel);
 void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 ctrl, int fixed_idx);

void reprogram_counter(struct kvm_pmu *pmu, int pmc_idx);

arch/x86/kvm/vmx.c +3 -0

index 92705b5..ae20563 100644
@@ -1282,6 +1282,9 @@ static bool
 nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
 static void __always_inline vmx_disable_intercept_for_msr(unsigned long
 *msr_bitmap,
 							  u32 msr, int type);
+static void
+__always_inline vmx_set_intercept_for_msr(unsigned long *msr_bitmap, u32
 msr,
+					  int type, bool value);

static DEFINE_PER_CPU(struct vmcs *, vmxarea); static DEFINE_PER_CPU(struct vmcs *, current_vmcs);

arch/x86/kvm/vmx.c +55 -0

@@ -4056,6 +4059,120 @@ static int vmx_get_msr_feature(struct
 kvm_msr_entry *msr)
 	return 0;
 }
 
+static void vmx_set_intercept_for_lbr_msrs(struct kvm_vcpu *vcpu, bool set)
+{
+	unsigned long *msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
+	struct perf_lbr_stack *stack = &vcpu->kvm->arch.lbr_stack;
+	int nr = stack->nr;
+	int i;
+
+	vmx_set_intercept_for_msr(msr_bitmap, stack->tos, MSR_TYPE_RW,
 set);
+	for (i = 0; i < nr; i++) {
+		vmx_set_intercept_for_msr(msr_bitmap, stack->from + i,
+					  MSR_TYPE_RW, set);
+		vmx_set_intercept_for_msr(msr_bitmap, stack->to + i,
+					  MSR_TYPE_RW, set);
+		if (stack->info)
+			vmx_set_intercept_for_msr(msr_bitmap, stack->info + i,
+						  MSR_TYPE_RW, set);
+	}
+}
+
+static inline bool msr_is_lbr_stack(struct kvm_vcpu *vcpu, u32 index)
+{
+	struct perf_lbr_stack *stack = &vcpu->kvm->arch.lbr_stack;
+	int nr = stack->nr;
+
+	return !!(index == stack->tos ||
+		 (index >= stack->from && index < stack->from + nr) ||
+		 (index >= stack->to && index < stack->to + nr) ||
+		 (index >= stack->info && index < stack->info));
+}
+
+static bool guest_get_lbr_msr(struct kvm_vcpu *vcpu, struct msr_data
 *msr_info)
+{
+	u32 index = msr_info->index;
+	bool ret = false;
+
+	switch (index) {
+	case MSR_IA32_DEBUGCTLMSR:
+		msr_info->data = vmcs_read64(GUEST_IA32_DEBUGCTL);
+		ret = true;
+		break;
+	case MSR_LBR_SELECT:
+		ret = true;
+		rdmsrl(index, msr_info->data);
+		break;
+	default:
+		if (msr_is_lbr_stack(vcpu, index)) {
+			ret = true;
+			rdmsrl(index, msr_info->data);
+		}
+	}
+
+	return ret;
+}
+
+static bool guest_set_lbr_msr(struct kvm_vcpu *vcpu, struct msr_data

*msr_info)

arch/x86/kvm/vmx.c +10 -0

+{
+	u32 index = msr_info->index;
+	u64 data = msr_info->data;
+	bool ret = false;
+
+	switch (index) {
+	case MSR_IA32_DEBUGCTLMSR:
+		ret = true;
+		/*
+		 * Currently, only FREEZE_LBRS_ON_PMI and DEBUGCTLMSR_LBR

are

arch/x86/kvm/vmx.c +3 -0

+		 * supported.
+		 */
+		data &= (DEBUGCTLMSR_FREEZE_LBRS_ON_PMI |

DEBUGCTLMSR_LBR);

arch/x86/kvm/vmx.c +27 -0

+		vmcs_write64(GUEST_IA32_DEBUGCTL, msr_info->data);
+		break;
+	case MSR_LBR_SELECT:
+		ret = true;
+		if (lbr_select_user_callstack(data))
+			vcpu->arch.lbr_user_callstack = true;
+		else
+			vcpu->arch.lbr_user_callstack = false;
+		wrmsrl(index, msr_info->data);
+		break;
+	default:
+		if (msr_is_lbr_stack(vcpu, index)) {
+			ret = true;
+			wrmsrl(index, msr_info->data);
+		}
+	}
+
+	return ret;
+}
+
+static bool guest_access_lbr_msr(struct kvm_vcpu *vcpu,
+				 struct msr_data *msr_info,
+				 bool set)
+{
+	bool ret = false;
+
+	if (!vcpu->kvm->arch.guest_lbr_enabled)

Quoted 12 lines

arch/x86/kvm/vmx.c +12 -0

+static bool guest_access_lbr_msr(struct kvm_vcpu *vcpu,
+				 struct msr_data *msr_info,
+				 bool set)
+{
+	bool ret = false;
+
+	if (!vcpu->kvm->arch.guest_lbr_enabled)
+		return false;
+
+	if (set)
+		ret = guest_set_lbr_msr(vcpu, msr_info);
+	else

arch/x86/kvm/vmx.c static int vmx_get_msr_feature(struct kvm_msr_entry *msr) · line 4166

Quoted 5 lines

arch/x86/kvm/vmx.c +5 -0

+		ret = guest_get_lbr_msr(vcpu, msr_info);
+
+	if (ret) {
+		vcpu->arch.lbr_used = true;
+		vmx_set_intercept_for_lbr_msrs(vcpu, false);

You can use if (!vcpu->arch.lbr_used) as the condition of assign values. They are need only once.

/**
+ * lbr_select_user_callstack - check if the user callstack mode is set
+ *
+ * @lbr_select: the lbr select msr
+ *
+ * Returns: true if the msr is configured to the user callstack mode.
+ * Otherwise, false.
+ *
+ */

Quoted 9 lines · Wei Wang

/**
+ * lbr_select_user_callstack - check if the user callstack mode is set
+ *
+ * @lbr_select: the lbr select msr
+ *
+ * Returns: true if the msr is configured to the user callstack mode.
+ * Otherwise, false.
+ *
+ */

arch/x86/events/intel/lbr.c void intel_pmu_lbr_init_knl(void) · line 1299

Quoted 5 lines

arch/x86/events/intel/lbr.c +5 -0

+bool lbr_select_user_callstack(u64 lbr_select)
+{
+	return !!(lbr_select & LBR_USER_CALLSTACK);
+}
+EXPORT_SYMBOL_GPL(lbr_select_user_callstack);

That function is pure and tiny, wth is that an exported symbol and not an inline?

Quoted 17 lines · Peter Zijlstra

Quoted 9 lines · Wei Wang

/**
+ * lbr_select_user_callstack - check if the user callstack mode is set
+ *
+ * @lbr_select: the lbr select msr
+ *
+ * Returns: true if the msr is configured to the user callstack mode.
+ * Otherwise, false.
+ *
+ */

arch/x86/events/intel/lbr.c void intel_pmu_lbr_init_knl(void) · line 1299

Quoted 5 lines

arch/x86/events/intel/lbr.c +5 -0

+bool lbr_select_user_callstack(u64 lbr_select)
+{
+	return !!(lbr_select & LBR_USER_CALLSTACK);
+}
+EXPORT_SYMBOL_GPL(lbr_select_user_callstack);

That function is pure and tiny, wth is that an exported symbol and not an inline?

Thanks Peter for the comments.

Because this function uses the LBR_ macros which are defined in this lbr.c file.
Do you think it would be OK to move all the above LBR_ macros to asm/perf_event.h?

-----Original Message-----
From: [email protected] [mailto:[email protected]] On Behalf Of Wei Wang
Sent: Thursday, September 20, 2018 6:06 PM
To: [email protected]; [email protected]; [email protected]; [email protected]
Cc: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Gonglei (Arei) <[email protected]>
Subject: [PATCH v3 0/5] Guest LBR Enabling

Last Branch Recording (LBR) is a performance monitor unit (PMU) feature on Intel CPUs that captures branch related info. This patch series enables this feature to KVM guests.

Here is a conclusion of the fundamental methods that we use:
1) the LBR feature is enabled per guest via QEMU setting of KVM_CAP_X86_GUEST_LBR;

2) the LBR stack is passed through to the guest for direct accesses after the guest's first access to any of the lbr related MSRs;
3) When the guest uses the LBR feature with the user callstack mode, the host will help save/resotre the LBR stack when the vCPU is scheduled out/in.

ChangeLog:
v2->v3:
- replaces the pv approach with a lazy save approach to saving the lbr stack on vCPU switching;
- destroy the host side perf event if the guest is torn down;
- remove the unnecessary event->pmu->stop() before calling perf_event_release_kernel().
v1->v2:
- add the per guest LBR capability, KVM_CAP_X86_GUEST_LBR;
- save/restore the LBR stack conditionally on the vCPU thread context switching, instead of on VMX transitions;
- expose MSR_IA32_PERF_CAPABILITIES to the guest.

Like Xu (1):
KVM/x86/vPMU: Add APIs to support host save/restore the guest lbr
stack

Wei Wang (4):
perf/x86: add a function to get the lbr stack KVM/x86: KVM_CAP_X86_GUEST_LBR
KVM/x86: expose MSR_IA32_PERF_CAPABILITIES to the guest KVM/x86/lbr: lazy save the guest lbr stack

 arch/x86/events/intel/lbr.c       |  49 ++++++++++++-
 arch/x86/events/perf_event.h      |   1 +
 arch/x86/include/asm/kvm_host.h   |   7 ++
 arch/x86/include/asm/perf_event.h |  22 ++++++
 arch/x86/kvm/cpuid.c              |   2 +-
 arch/x86/kvm/pmu.h                |   8 +++
 arch/x86/kvm/pmu_intel.c          |  41 +++++++++++
 arch/x86/kvm/vmx.c                | 144
++++++++++++++++++++++++++++++++++++++
 arch/x86/kvm/x86.c                |  10 +++
 include/uapi/linux/kvm.h          |   1 +
 10 files changed, 281 insertions(+), 4 deletions(-)

--
2.7.4

Quoted 11 lines

-----Original Message-----
From: [email protected] [mailto:[email protected]] On Behalf Of Wei Wang
Sent: Thursday, September 20, 2018 6:06 PM
To: [email protected]; [email protected]; [email protected]; [email protected]
Cc: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Gonglei (Arei) <[email protected]>
Subject: [PATCH v3 0/5] Guest LBR Enabling

Quoted 7 lines

Last Branch Recording (LBR) is a performance monitor unit (PMU) feature on Intel CPUs that captures branch related info. This patch series enables this feature to KVM guests.

Here is a conclusion of the fundamental methods that we use:
1) the LBR feature is enabled per guest via QEMU setting of

    KVM_CAP_X86_GUEST_LBR;

Did you send the QEMU parts for guest LBR support?