Guest LBR Enabling
Subsystems (4)
v5 cover Guest LBR Enabling
Last Branch Recording (LBR) is a performance monitor unit (PMU) feature on Intel CPUs that captures branch related info. This patch series enables this feature to KVM guests.
Here is a conclusion of the fundamental methods that we use:
1) the LBR feature is enabled per guest via QEMU setting of KVM_CAP_X86_GUEST_LBR;
2) the LBR stack is passed through to the guest for direct accesses after the guest's first access to any of the lbr related MSRs;
3) the host will help save/resotre the LBR stack when the vCPU is scheduled out/in.
ChangeLog:
- KVM/x86:
- patch 4: enable guest lbr when guest lbr msr index and host lbr msr index matches;
- patch 5: change kvm_pmu_get_msr to get the msr_data struct;
- patch 8: remove the PF_VCPU and is_kernel_event check;
- patch 10:
- move the lbr virtualization code from vmx.c to pmu_intel.c;
- save the lbr stack even when the guest is not using the user callstack mode in case some tools (e.g. autofdo) complain for bogus samples;
- patch 11: remove the common handling of the debugctl;
- patch 12: support to report GLOBAL_STATUS_LBRS_FROZEN.
previous:
https://lkml.org/lkml/2018/12/26/82
Like Xu (1):
KVM/x86/vPMU: Add APIs to support host save/restore the guest lbr
stack
Wei Wang (11):
perf/x86: fix the variable type of the LBR MSRs perf/x86: add a function to get the lbr stack KVM/x86: KVM_CAP_X86_GUEST_LBR
KVM/x86: intel_pmu_lbr_enable
KVM/x86/vPMU: tweak kvm_pmu_get_msr
KVM/x86: expose MSR_IA32_PERF_CAPABILITIES to the guest perf/x86: no counter allocation support perf/x86: save/restore LBR_SELECT on vCPU switching KVM/x86/lbr: lazy save the guest lbr stack KVM/x86: remove the common handling of the debugctl msr KVM/VMX/vPMU: support to report GLOBAL_STATUS_LBRS_FROZEN
arch/x86/events/core.c | 12 ++ arch/x86/events/intel/lbr.c | 42 +++- arch/x86/events/perf_event.h | 6 +- arch/x86/include/asm/kvm_host.h | 5 + arch/x86/include/asm/perf_event.h | 16 ++ arch/x86/kvm/cpuid.c | 2 +- arch/x86/kvm/cpuid.h | 8 + arch/x86/kvm/pmu.c | 18 +- arch/x86/kvm/pmu.h | 11 +- arch/x86/kvm/pmu_amd.c | 7 +- arch/x86/kvm/vmx/pmu_intel.c | 398 +++++++++++++++++++++++++++++++++++++- arch/x86/kvm/vmx/vmx.c | 4 +- arch/x86/kvm/vmx/vmx.h | 2 + arch/x86/kvm/x86.c | 33 ++-- include/linux/perf_event.h | 5 + include/uapi/linux/kvm.h | 1 + include/uapi/linux/perf_event.h | 3 +- 17 files changed, 535 insertions(+), 38 deletions(-)
Signature · 1 line
2.7.4
PATCH v5 1/12 perf/x86: fix the variable type of the LBR MSRs
The MSR variable type can be "unsigned int", which uses less memory than the longer unsigned long. The lbr nr won't be a negative number, so make it "unsigned int" as well.
--- arch/x86/events/perf_event.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
arch/x86/events/perf_event.h +2 -2
@@ -619,8 +619,8 @@ struct x86_pmu {/* * Intel LBR */ -unsigned long lbr_tos, lbr_from, lbr_to;/* MSR base regs */ -int lbr_nr;/* hardware stack size */ +unsigned int lbr_tos, lbr_from, lbr_to, + lbr_nr;/* lbr stack and size */ u64 lbr_sel_mask;/* LBR_SELECT valid bits */ const int *lbr_sel_map;/* lbr_select mappings */ bool lbr_double_abort;/* duplicated lbr aborts */
Signature · 1 line
2.7.4
PATCH v5 2/12 perf/x86: add a function to get the lbr stack
In reply to Wei WangThe LBR stack MSRs are architecturally specific. The perf subsystem has already assigned the abstracted MSR values based on the CPU architecture.
This patch enables a caller outside the perf subsystem to get the LBR stack info. This is useful for hyperviosrs to prepare the lbr feature for the guest.
--- arch/x86/events/intel/lbr.c | 23 +++++++++++++++++++++++ arch/x86/include/asm/perf_event.h | 14 ++++++++++++++ 2 files changed, 37 insertions(+)
arch/x86/events/intel/lbr.c +23 -0
@@ -1277,3 +1277,26 @@ void intel_pmu_lbr_init_knl(void)if (x86_pmu.intel_cap.lbr_format ==LBR_FORMAT_LIP ) x86_pmu.intel_cap.lbr_format =LBR_FORMAT_EIP_FLAGS ; } + +/** +* x86_perf_get_lbr_stack - get the lbr stack related MSRs +* +* @stack: the caller's memory to get the lbr stack +* +* Returns: 0 indicates that the lbr stack has been successfully obtained. +*/ +int x86_perf_get_lbr_stack (struct x86_perf_lbr_stack *stack) +{ + stack->nr = x86_pmu.lbr_nr; + stack->tos = x86_pmu.lbr_tos; + stack->from = x86_pmu.lbr_from; + stack->to = x86_pmu.lbr_to; + +if (x86_pmu.intel_cap.lbr_format ==LBR_FORMAT_INFO ) + stack->info =MSR_LBR_INFO_0 ; +else + stack->info =0 ; + +return 0 ; +} +EXPORT_SYMBOL_GPL (x86_perf_get_lbr_stack);
arch/x86/include/asm/perf_event.h +14 -0
@@ -275,7 +275,16 @@ struct perf_guest_switch_msr {u64 host, guest; }; +struct x86_perf_lbr_stack { +unsigned int nr; +unsigned int tos; +unsigned int from; +unsigned int to; +unsigned int info; +}; +extern struct perf_guest_switch_msr *perf_guest_get_msrs (int *nr); +extern int x86_perf_get_lbr_stack (struct x86_perf_lbr_stack *stack);extern void perf_get_x86_pmu_capability (struct x86_pmu_capability *cap);extern void perf_check_microcode (void );extern int x86_perf_rdpmc_index (struct perf_event *event);
@@ -286,6 +295,11 @@ static inline struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)return NULL ; } +static inline int x86_perf_get_lbr_stack (struct x86_perf_lbr_stack *stack) +{ +return -1 ; +} +static inline void perf_get_x86_pmu_capability (struct x86_pmu_capability *cap) {memset (cap,0 ,sizeof (*cap));
Signature · 1 line
2.7.4
PATCH v5 3/12 KVM/x86: KVM_CAP_X86_GUEST_LBR
In reply to Wei WangIntroduce KVM_CAP_X86_GUEST_LBR to allow per-VM enabling of the guest lbr feature.
--- arch/x86/include/asm/kvm_host.h | 2 ++ arch/x86/kvm/x86.c | 15 +++++++++++++++ include/uapi/linux/kvm.h | 1 + 3 files changed, 18 insertions(+)
arch/x86/include/asm/kvm_host.h +2 -0
@@ -869,6 +869,7 @@ struct kvm_arch {atomic_t vapics_in_nmi_mode;struct mutex apic_map_lock;struct kvm_apic_map *apic_map; +struct x86_perf_lbr_stack lbr_stack;bool apic_access_page_done;
@@ -877,6 +878,7 @@ struct kvm_arch {bool mwait_in_guest;bool hlt_in_guest;bool pause_in_guest; +bool lbr_in_guest;unsigned long irq_sources_bitmap;s64 kvmclock_offset;
arch/x86/kvm/x86.c +15 -0
@@ -3028,6 +3028,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)case KVM_CAP_GET_MSR_FEATURES :case KVM_CAP_MSR_PLATFORM_INFO :case KVM_CAP_EXCEPTION_PAYLOAD : +case KVM_CAP_X86_GUEST_LBR : r =1 ;break ;case KVM_CAP_SYNC_REGS :
@@ -4562,6 +4563,20 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm, kvm->arch.exception_payload_enabled = cap->args[0 ]; r =0 ;break ; +case KVM_CAP_X86_GUEST_LBR : + r = -EINVAL ; +if (cap->args[0 ] && +x86_perf_get_lbr_stack (&kvm->arch.lbr_stack)) { +pr_err ("Failed to enable the guest lbr feature\n" ); +break ; + } +if (copy_to_user ((void __user *)cap->args[1 ], + &kvm->arch.lbr_stack, +sizeof (struct x86_perf_lbr_stack ))) +break ; + kvm->arch.lbr_in_guest = cap->args[0 ]; + r =0 ; +break ;default : r = -EINVAL ;break ;
include/uapi/linux/kvm.h +1 -0
@@ -988,6 +988,7 @@ struct kvm_ppc_resize_hpt {#define KVM_CAP_ARM_VM_IPA_SIZE 165#define KVM_CAP_MANUAL_DIRTY_LOG_PROTECT 166#define KVM_CAP_HYPERV_CPUID 167 +#define KVM_CAP_X86_GUEST_LBR 168#ifdef KVM_CAP_IRQ_ROUTING
Signature · 1 line
2.7.4
Re: [PATCH v5 03/12] KVM/x86: KVM_CAP_X86_GUEST_LBR
arch/x86/kvm/x86.c int kvm_vm_ioctl_enable_cap(struct kvm *kvm, · line 4570
Quoted 5 lines
arch/x86/kvm/x86.c +5
-0+case KVM_CAP_X86_GUEST_LBR : + r = -EINVAL ; +if (cap->args[0 ] && +x86_perf_get_lbr_stack (&kvm->arch.lbr_stack)) { +pr_err ("Failed to enable the guest lbr feature\n" );
Remove the pr_err. We don't want unprivileged users trigger unlimited kernel printk.
PATCH v5 4/12 KVM/x86: intel_pmu_lbr_enable
In reply to Wei WangThe lbr stack is architecturally specific, for example, SKX has 32 lbr stack entries while HSW has 16 entries, so a HSW guest running on a SKX machine may not get accurate perf results. Currently, we forbid the guest lbr enabling when the guest and host see different lbr stack entries or the host and guest see different lbr stack msr indices.
--- arch/x86/kvm/cpuid.h | 8 +++ arch/x86/kvm/pmu.c | 8 +++ arch/x86/kvm/pmu.h | 2 + arch/x86/kvm/vmx/pmu_intel.c | 136 +++++++++++++++++++++++++++++++++++++++++++ arch/x86/kvm/x86.c | 3 +- 5 files changed, 155 insertions(+), 2 deletions(-)
arch/x86/kvm/cpuid.h +8 -0
@@ -123,6 +123,14 @@ static inline bool guest_cpuid_is_amd(struct kvm_vcpu *vcpu)return best && best->ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx; } +static inline bool guest_cpuid_is_intel (struct kvm_vcpu *vcpu) +{ +struct kvm_cpuid_entry2 *best; + + best =kvm_find_cpuid_entry (vcpu,0 ,0 ); +return best && best->ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx; +} +static inline int guest_cpuid_family (struct kvm_vcpu *vcpu) {struct kvm_cpuid_entry2 *best;
arch/x86/kvm/pmu.c +8 -0
@@ -299,6 +299,14 @@ int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned idx, u64 *data)return 0 ; } +bool kvm_pmu_lbr_enable (struct kvm_vcpu *vcpu) +{ +if (guest_cpuid_is_intel (vcpu)) +return kvm_x86_ops->pmu_ops->lbr_enable (vcpu); + +return false; +} +void kvm_pmu_deliver_pmi (struct kvm_vcpu *vcpu) {if (lapic_in_kernel (vcpu))
arch/x86/kvm/pmu.h +2 -0
@@ -28,6 +28,7 @@ struct kvm_pmu_ops {struct kvm_pmc *(*msr_idx_to_pmc)(struct kvm_vcpu *vcpu,unsigned idx);int (*is_valid_msr_idx)(struct kvm_vcpu *vcpu,unsigned idx);bool (*is_valid_msr)(struct kvm_vcpu *vcpu,u32 msr); +bool (*lbr_enable)(struct kvm_vcpu *vcpu);int (*get_msr)(struct kvm_vcpu *vcpu,u32 msr,u64 *data);int (*set_msr)(struct kvm_vcpu *vcpu,struct msr_data *msr_info);void (*refresh)(struct kvm_vcpu *vcpu);
@@ -106,6 +107,7 @@ void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel);void reprogram_fixed_counter (struct kvm_pmc *pmc,u8 ctrl,int fixed_idx);void reprogram_counter (struct kvm_pmu *pmu,int pmc_idx); +bool kvm_pmu_lbr_enable (struct kvm_vcpu *vcpu);void kvm_pmu_deliver_pmi (struct kvm_vcpu *vcpu);void kvm_pmu_handle_event (struct kvm_vcpu *vcpu);int kvm_pmu_rdpmc (struct kvm_vcpu *vcpu,unsigned pmc,u64 *data);
arch/x86/kvm/vmx/pmu_intel.c +136 -0
154 lines not on this page · raw message
arch/x86/kvm/x86.c +1 -2
@@ -4565,8 +4565,7 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm,break ;case KVM_CAP_X86_GUEST_LBR : r = -EINVAL ; -if (cap->args[0 ] && -x86_perf_get_lbr_stack (&kvm->arch.lbr_stack)) { +if (cap->args[0 ] && !kvm_pmu_lbr_enable (kvm->vcpus[0 ])) {pr_err ("Failed to enable the guest lbr feature\n" );break ; }
Signature · 1 line
2.7.4
PATCH v5 5/12 KVM/x86/vPMU: tweak kvm_pmu_get_msr
In reply to Wei WangThis patch changes kvm_pmu_get_msr to get the msr_data struct, because The host_initiated field from the struct could be used by get_msr. This also makes this API be consistent with kvm_pmu_set_msr.
--- arch/x86/kvm/pmu.c | 4 ++-- arch/x86/kvm/pmu.h | 4 ++-- arch/x86/kvm/pmu_amd.c | 7 ++++--- arch/x86/kvm/vmx/pmu_intel.c | 15 ++++++++------- arch/x86/kvm/x86.c | 4 ++-- 5 files changed, 18 insertions(+), 16 deletions(-)
arch/x86/kvm/pmu.c +2 -2
@@ -318,9 +318,9 @@ bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)return kvm_x86_ops->pmu_ops->is_valid_msr (vcpu, msr); } -int kvm_pmu_get_msr (struct kvm_vcpu *vcpu,u32 msr,u64 *data) +int kvm_pmu_get_msr (struct kvm_vcpu *vcpu,struct msr_data *msr_info) { -return kvm_x86_ops->pmu_ops->get_msr (vcpu, msr, data); +return kvm_x86_ops->pmu_ops->get_msr (vcpu, msr_info); }int kvm_pmu_set_msr (struct kvm_vcpu *vcpu,struct msr_data *msr_info)
arch/x86/kvm/pmu.h +2 -2
@@ -29,7 +29,7 @@ struct kvm_pmu_ops {int (*is_valid_msr_idx)(struct kvm_vcpu *vcpu,unsigned idx);bool (*is_valid_msr)(struct kvm_vcpu *vcpu,u32 msr);bool (*lbr_enable)(struct kvm_vcpu *vcpu); -int (*get_msr)(struct kvm_vcpu *vcpu,u32 msr,u64 *data); +int (*get_msr)(struct kvm_vcpu *vcpu,struct msr_data *msr_info);int (*set_msr)(struct kvm_vcpu *vcpu,struct msr_data *msr_info);void (*refresh)(struct kvm_vcpu *vcpu);void (*init)(struct kvm_vcpu *vcpu);
@@ -113,7 +113,7 @@ void kvm_pmu_handle_event(struct kvm_vcpu *vcpu);int kvm_pmu_rdpmc (struct kvm_vcpu *vcpu,unsigned pmc,u64 *data);int kvm_pmu_is_valid_msr_idx (struct kvm_vcpu *vcpu,unsigned idx);bool kvm_pmu_is_valid_msr (struct kvm_vcpu *vcpu,u32 msr); -int kvm_pmu_get_msr (struct kvm_vcpu *vcpu,u32 msr,u64 *data); +int kvm_pmu_get_msr (struct kvm_vcpu *vcpu,struct msr_data *msr_info);int kvm_pmu_set_msr (struct kvm_vcpu *vcpu,struct msr_data *msr_info);void kvm_pmu_refresh (struct kvm_vcpu *vcpu);void kvm_pmu_reset (struct kvm_vcpu *vcpu);
arch/x86/kvm/pmu_amd.c +4 -3
@@ -210,21 +210,22 @@ static bool amd_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)return ret; } -static int amd_pmu_get_msr (struct kvm_vcpu *vcpu,u32 msr,u64 *data) +static int amd_pmu_get_msr (struct kvm_vcpu *vcpu,struct msr_data *msr_info) {struct kvm_pmu *pmu =vcpu_to_pmu (vcpu);struct kvm_pmc *pmc; +u32 msr = msr_info->index;/* MSR_PERFCTRn */ pmc =get_gp_pmc_amd (pmu, msr,PMU_TYPE_COUNTER );if (pmc) { - *data =pmc_read_counter (pmc); + msr_info->data =pmc_read_counter (pmc);return 0 ; }/* MSR_EVNTSELn */ pmc =get_gp_pmc_amd (pmu, msr,PMU_TYPE_EVNTSEL );if (pmc) { - *data = pmc->eventsel; + msr_info->data = pmc->eventsel;return 0 ; }
arch/x86/kvm/vmx/pmu_intel.c +8 -7
@@ -299,31 +299,32 @@ static bool intel_pmu_lbr_enable(struct kvm_vcpu *vcpu)return true; } -static int intel_pmu_get_msr (struct kvm_vcpu *vcpu,u32 msr,u64 *data) +static int intel_pmu_get_msr (struct kvm_vcpu *vcpu,struct msr_data *msr_info) {struct kvm_pmu *pmu =vcpu_to_pmu (vcpu);struct kvm_pmc *pmc; +u32 msr = msr_info->index;switch (msr) {case MSR_CORE_PERF_FIXED_CTR_CTRL : - *data = pmu->fixed_ctr_ctrl; + msr_info->data = pmu->fixed_ctr_ctrl;return 0 ;case MSR_CORE_PERF_GLOBAL_STATUS : - *data = pmu->global_status; + msr_info->data = pmu->global_status;return 0 ;case MSR_CORE_PERF_GLOBAL_CTRL : - *data = pmu->global_ctrl; + msr_info->data = pmu->global_ctrl;return 0 ;case MSR_CORE_PERF_GLOBAL_OVF_CTRL : - *data = pmu->global_ovf_ctrl; + msr_info->data = pmu->global_ovf_ctrl;return 0 ;default :if ((pmc =get_gp_pmc (pmu, msr,MSR_IA32_PERFCTR0 )) || (pmc =get_fixed_pmc (pmu, msr))) { - *data =pmc_read_counter (pmc); + msr_info->data =pmc_read_counter (pmc);return 0 ; }else if ((pmc =get_gp_pmc (pmu, msr,MSR_P6_EVNTSEL0 ))) { - *data = pmc->eventsel; + msr_info->data = pmc->eventsel;return 0 ; } }
arch/x86/kvm/x86.c +2 -2
@@ -2741,7 +2741,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:if (kvm_pmu_is_valid_msr (vcpu, msr_info->index)) -return kvm_pmu_get_msr (vcpu, msr_info->index, &msr_info->data); +return kvm_pmu_get_msr (vcpu, msr_info); msr_info->data =0 ;break ;case MSR_IA32_UCODE_REV :
@@ -2884,7 +2884,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)break ;default :if (kvm_pmu_is_valid_msr (vcpu, msr_info->index)) -return kvm_pmu_get_msr (vcpu, msr_info->index, &msr_info->data); +return kvm_pmu_get_msr (vcpu, msr_info);if (!ignore_msrs) {vcpu_debug_ratelimited (vcpu,"unhandled rdmsr: 0x%x\n" , msr_info->index);
Signature · 1 line
2.7.4
PATCH v5 6/12 KVM/x86: expose MSR_IA32_PERF_CAPABILITIES to the guest
In reply to Wei WangBits [0, 5] of MSR_IA32_PERF_CAPABILITIES tell about the format of the addresses stored in the LBR stack. Expose those bits to the guest when the guest lbr feature is enabled.
--- arch/x86/include/asm/perf_event.h | 2 ++ arch/x86/kvm/cpuid.c | 2 +- arch/x86/kvm/vmx/pmu_intel.c | 16 ++++++++++++++++ 3 files changed, 19 insertions(+), 1 deletion(-)
arch/x86/include/asm/perf_event.h +2 -0
@@ -87,6 +87,8 @@#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6#define ARCH_PERFMON_EVENTS_COUNT 7 +#define X86_PERF_CAP_MASK_LBR_FMT 0x3f +/* * Intel "Architectural Performance Monitoring" CPUID * detection/enumeration details:
arch/x86/kvm/cpuid.c +1 -1
@@ -363,7 +363,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,F (XMM3 ) |F (PCLMULQDQ ) |0 /* DTES64, MONITOR */ |0 /* DS-CPL, VMX, SMX, EST */ |0 /* TM2 */ |F (SSSE3 ) |0 /* CNXT-ID */ |0 /* Reserved */ | -F (FMA ) |F (CX16 ) |0 /* xTPR Update, PDCM */ | +F (FMA ) |F (CX16 ) |0 /* xTPR Update*/ |F (PDCM ) |F (PCID ) |0 /* Reserved, DCA */ |F (XMM4_1 ) |F (XMM4_2 ) |F (X2APIC ) |F (MOVBE ) |F (POPCNT ) | 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
arch/x86/kvm/vmx/pmu_intel.c +16 -0
@@ -153,6 +153,7 @@ static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)case MSR_CORE_PERF_GLOBAL_STATUS :case MSR_CORE_PERF_GLOBAL_CTRL :case MSR_CORE_PERF_GLOBAL_OVF_CTRL : +case MSR_IA32_PERF_CAPABILITIES : ret = pmu->version >1 ;break ;default :
@@ -318,6 +319,19 @@ static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)case MSR_CORE_PERF_GLOBAL_OVF_CTRL : msr_info->data = pmu->global_ovf_ctrl;return 0 ; +case MSR_IA32_PERF_CAPABILITIES : { +u64 data; + +if (!boot_cpu_has (X86_FEATURE_PDCM ) || + (!msr_info->host_initiated && + !guest_cpuid_has (vcpu,X86_FEATURE_PDCM ))) +return 1 ; + data =native_read_msr (MSR_IA32_PERF_CAPABILITIES ); + msr_info->data =0 ; +if (vcpu->kvm->arch.lbr_in_guest) + msr_info->data |= (data &X86_PERF_CAP_MASK_LBR_FMT ); +return 0 ; + }default :if ((pmc =get_gp_pmc (pmu, msr,MSR_IA32_PERFCTR0 )) || (pmc =get_fixed_pmc (pmu, msr))) {
@@ -370,6 +384,8 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)return 0 ; }break ; +case MSR_IA32_PERF_CAPABILITIES : +return 1 ;/* RO MSR */ default :if ((pmc =get_gp_pmc (pmu, msr,MSR_IA32_PERFCTR0 )) || (pmc =get_fixed_pmc (pmu, msr))) {
Signature · 1 line
2.7.4
PATCH v5 7/12 perf/x86: no counter allocation support
In reply to Wei WangIn some cases, an event may be created without needing a counter allocation. For example, an lbr event may be created by the host only to help save/restore the lbr stack on the vCPU context switching.
This patch adds a "no_counter" attr boolean to let the callers explicitly tell the perf core that no counter is needed.
--- arch/x86/events/core.c | 12 ++++++++++++ include/linux/perf_event.h | 5 +++++ include/uapi/linux/perf_event.h | 3 ++- 3 files changed, 19 insertions(+), 1 deletion(-)
arch/x86/events/core.c +12 -0
@@ -410,6 +410,9 @@ int x86_setup_perfctr(struct perf_event *event)struct hw_perf_event *hwc = &event->hw;u64 config; +if (is_no_counter_event (event)) +return 0 ; +if (!is_sampling_event (event)) { hwc->sample_period = x86_pmu.max_period; hwc->last_period = hwc->sample_period;
@@ -1209,6 +1212,12 @@ static int x86_pmu_add(struct perf_event *event, int flags) hwc = &event->hw; n0 = cpuc->n_events; + +if (is_no_counter_event (event)) { + n = n0; + goto done_collect; + } + ret = n =collect_events (cpuc, event, false);if (ret <0 ) goto out;
@@ -1387,6 +1396,9 @@ static void x86_pmu_del(struct perf_event *event, int flags)if (cpuc->txn_flags &PERF_PMU_TXN_ADD ) goto do_del; +if (is_no_counter_event (event)) + goto do_del; +/* * Not a TXN, therefore cleanup properly. */
include/linux/perf_event.h +5 -0
@@ -1009,6 +1009,11 @@ static inline bool is_sampling_event(struct perf_event *event)return event->attr.sample_period !=0 ; } +static inline bool is_no_counter_event (struct perf_event *event) +{ +return event->attr.no_counter; +} +/* * Return 1 for a software event, 0 for a hardware event */
include/uapi/linux/perf_event.h +2 -1
@@ -372,7 +372,8 @@ struct perf_event_attr { context_switch : 1, /* context switch data */ write_backward : 1, /* Write ring buffer from end to beginning */ namespaces : 1, /* include namespaces data */ - __reserved_1 : 35; + no_counter : 1, /* no counter allocation */ + __reserved_1 : 34;union {__u32 wakeup_events;/* wakeup every n events */
Signature · 1 line
2.7.4
Re: [PATCH v5 07/12] perf/x86: no counter allocation support
include/uapi/linux/perf_event.h struct perf_event_attr { · line 375
Quoted 10 lines
include/uapi/linux/perf_event.h +1
-1@@ -372,7 +372,8 @@ struct perf_event_attr { context_switch : 1, /* context switch data */ write_backward : 1, /* Write ring buffer from end to beginning */ namespaces : 1, /* include namespaces data */ - __reserved_1 : 35; + no_counter : 1, /* no counter allocation */
Not sure we really want to expose this in the user ABI. Perhaps make it a feature of the in kernel API only?
-Andi
RE: [PATCH v5 07/12] perf/x86: no counter allocation support
Quoted 8 lines · Andi Kleen
include/uapi/linux/perf_event.h struct perf_event_attr { · line 373
Quoted 7 lines
(quoted diff) +0
-0
b/include/uapi/linux/perf_event.hindex 9de8780..ec97a70 100644include/uapi/linux/perf_event.h +0
-0@@ -372,7 +372,8 @@ struct perf_event_attr { context_switch : 1, /* context switch data */ write_backward : 1, /* Write ring buffer fromend to beginning */
Quoted 7 lines
include/uapi/linux/perf_event.h struct perf_event_attr { · line 374
Quoted 1 line
include/uapi/linux/perf_event.h +0
-0namespaces : 1, /* include namespacesdata */
include/uapi/linux/perf_event.h struct perf_event_attr { · line 375
Quoted 2 lines
include/uapi/linux/perf_event.h +1
-1- __reserved_1 :35 ; + no_counter : 1, /* no counter allocation */Not sure we really want to expose this in the user ABI. Perhaps make it a feature of the in kernel API only?
OK. I plan to move it to the perf_event struct.
Best,
Wei
PATCH v5 8/12 KVM/x86/vPMU: Add APIs to support host save/restore the guest lbr stack
In reply to Wei WangFrom: Like Xu <[email protected]>
This patch adds support to enable/disable the host side save/restore for the guest lbr stack on vCPU switching. To enable that, the host creates a perf event for the vCPU, and the event attributes are set to the user callstack mode lbr so that all the conditions are meet in the host perf subsystem to save the lbr stack on task switching.
The host side lbr perf event are created only for the purpose of saving and restoring the lbr stack. There is no need to enable the lbr functionality for this perf event, because the feature is essentially used in the vCPU. So use "no_counter=true" to have the perf core not allocate a counter for this event.
The vcpu_lbr field is added to cpuc, to indicate if the lbr perf event is used by the vCPU only for context switching. When the perf subsystem handles this event (e.g. lbr enable or read lbr stack on PMI) and finds it's non-zero, it simply returns.
--- arch/x86/events/intel/lbr.c | 12 ++++++-- arch/x86/events/perf_event.h | 1 + arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/pmu.h | 3 ++ arch/x86/kvm/vmx/pmu_intel.c | 66 +++++++++++++++++++++++++++++++++++++++++ 5 files changed, 80 insertions(+), 3 deletions(-)
arch/x86/events/intel/lbr.c +9 -3
@@ -462,6 +462,9 @@ void intel_pmu_lbr_add(struct perf_event *event)if (!x86_pmu.lbr_nr)return ; +if (event->attr.exclude_guest && event->attr.no_counter) + cpuc->vcpu_lbr =1 ; + cpuc->br_sel = event->hw.branch_reg.reg;if (branch_user_callstack (cpuc->br_sel) && event->ctx->task_ctx_data) {
@@ -507,6 +510,9 @@ void intel_pmu_lbr_del(struct perf_event *event) task_ctx->lbr_callstack_users--; } +if (event->attr.exclude_guest && event->attr.no_counter) + cpuc->vcpu_lbr =0 ; + cpuc->lbr_users--;WARN_ON_ONCE (cpuc->lbr_users <0 );perf_sched_cb_dec (event->ctx->pmu);
@@ -516,7 +522,7 @@ void intel_pmu_lbr_enable_all(bool pmi) {struct cpu_hw_events *cpuc =this_cpu_ptr (&cpu_hw_events); -if (cpuc->lbr_users) +if (cpuc->lbr_users && !cpuc->vcpu_lbr)__intel_pmu_lbr_enable (pmi); }
@@ -524,7 +530,7 @@ void intel_pmu_lbr_disable_all(void) {struct cpu_hw_events *cpuc =this_cpu_ptr (&cpu_hw_events); -if (cpuc->lbr_users) +if (cpuc->lbr_users && !cpuc->vcpu_lbr)__intel_pmu_lbr_disable (); }
@@ -658,7 +664,7 @@ void intel_pmu_lbr_read(void) {struct cpu_hw_events *cpuc =this_cpu_ptr (&cpu_hw_events); -if (!cpuc->lbr_users) +if (!cpuc->lbr_users || cpuc->vcpu_lbr)return ;if (x86_pmu.intel_cap.lbr_format ==LBR_FORMAT_32 )
arch/x86/events/perf_event.h +1 -0
@@ -210,6 +210,7 @@ struct cpu_hw_events {/* * Intel LBR bits */ +u8 vcpu_lbr;int lbr_users;struct perf_branch_stack lbr_stack;struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES ];
arch/x86/include/asm/kvm_host.h +1 -0
@@ -474,6 +474,7 @@ struct kvm_pmu {struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED ];struct irq_work irq_work;u64 reprogram_pmi; +struct perf_event *vcpu_lbr_event; };struct kvm_pmu_ops ;
arch/x86/kvm/pmu.h +3 -0
@@ -122,6 +122,9 @@ void kvm_pmu_destroy(struct kvm_vcpu *vcpu);bool is_vmware_backdoor_pmc (u32 pmc_idx); +extern int intel_pmu_enable_save_guest_lbr (struct kvm_vcpu *vcpu); +extern void intel_pmu_disable_save_guest_lbr (struct kvm_vcpu *vcpu); +extern struct kvm_pmu_ops intel_pmu_ops;extern struct kvm_pmu_ops amd_pmu_ops;#endif /* __KVM_X86_PMU_H */
arch/x86/kvm/vmx/pmu_intel.c +66 -0
72 lines not on this page · raw message
Signature · 1 line
2.7.4
PATCH v5 9/12 perf/x86: save/restore LBR_SELECT on vCPU switching
In reply to Wei WangThe vCPU lbr event relies on the host to save/restore all the lbr related MSRs. So add the LBR_SELECT save/restore to the related functions for the vCPU case.
--- arch/x86/events/intel/lbr.c | 7 +++++++ arch/x86/events/perf_event.h | 1 + 2 files changed, 8 insertions(+)
arch/x86/events/intel/lbr.c +7 -0
@@ -383,6 +383,9 @@ static void __intel_pmu_lbr_restore(struct x86_perf_task_context *task_ctx)wrmsrl (x86_pmu.lbr_tos, tos); task_ctx->lbr_stack_state =LBR_NONE ; + +if (cpuc->vcpu_lbr) +wrmsrl (MSR_LBR_SELECT , task_ctx->lbr_sel); }static void __intel_pmu_lbr_save (struct x86_perf_task_context *task_ctx)
@@ -409,6 +412,10 @@ static void __intel_pmu_lbr_save(struct x86_perf_task_context *task_ctx)if (x86_pmu.intel_cap.lbr_format ==LBR_FORMAT_INFO )rdmsrl (MSR_LBR_INFO_0 + lbr_idx, task_ctx->lbr_info[i]); } + +if (cpuc->vcpu_lbr) +rdmsrl (MSR_LBR_SELECT , task_ctx->lbr_sel); + task_ctx->valid_lbrs = i; task_ctx->tos = tos; task_ctx->lbr_stack_state =LBR_VALID ;
arch/x86/events/perf_event.h +1 -0
@@ -653,6 +653,7 @@ struct x86_perf_task_context {u64 lbr_from[MAX_LBR_ENTRIES ];u64 lbr_to[MAX_LBR_ENTRIES ];u64 lbr_info[MAX_LBR_ENTRIES ]; +u64 lbr_sel;int tos;int valid_lbrs;int lbr_callstack_users;
Signature · 1 line
2.7.4
PATCH v5 10/12 KVM/x86/lbr: lazy save the guest lbr stack
In reply to Wei WangWhen the vCPU is scheduled in:
- if the lbr feature was used in the last vCPU time slice, set the lbr stack to be interceptible, so that the host can capture whether the lbr feature will be used in this time slice;
- if the lbr feature wasn't used in the last vCPU time slice, disable the vCPU support of the guest lbr switching.
Upon the first access to one of the lbr related MSRs (since the vCPU was scheduled in):
- record that the guest has used the lbr;
- create a host perf event to help save/restore the guest lbr stack;
- pass the stack through to the guest.
--- arch/x86/include/asm/kvm_host.h | 2 + arch/x86/kvm/pmu.c | 6 ++ arch/x86/kvm/pmu.h | 2 + arch/x86/kvm/vmx/pmu_intel.c | 146 ++++++++++++++++++++++++++++++++++++++++ arch/x86/kvm/vmx/vmx.c | 4 +- arch/x86/kvm/vmx/vmx.h | 2 + arch/x86/kvm/x86.c | 2 + 7 files changed, 162 insertions(+), 2 deletions(-)
arch/x86/include/asm/kvm_host.h +2 -0
@@ -469,6 +469,8 @@ struct kvm_pmu {u64 counter_bitmask[2 ];u64 global_ctrl_mask;u64 reserved_bits; +/* Indicate if the lbr msrs were accessed in this vCPU time slice */ +bool lbr_used;u8 version;struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC ];struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED ];
arch/x86/kvm/pmu.c +6 -0
@@ -328,6 +328,12 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)return kvm_x86_ops->pmu_ops->set_msr (vcpu, msr_info); } +void kvm_pmu_sched_in (struct kvm_vcpu *vcpu,int cpu) +{ +if (kvm_x86_ops->pmu_ops->sched_in) + kvm_x86_ops->pmu_ops->sched_in (vcpu, cpu); +} +/* refresh PMU settings. This function generally is called when underlying * settings are changed (such as changes of PMU CPUID by guest VMs), which * should rarely happen.
arch/x86/kvm/pmu.h +2 -0
@@ -31,6 +31,7 @@ struct kvm_pmu_ops {bool (*lbr_enable)(struct kvm_vcpu *vcpu);int (*get_msr)(struct kvm_vcpu *vcpu,struct msr_data *msr_info);int (*set_msr)(struct kvm_vcpu *vcpu,struct msr_data *msr_info); +void (*sched_in)(struct kvm_vcpu *vcpu,int cpu);void (*refresh)(struct kvm_vcpu *vcpu);void (*init)(struct kvm_vcpu *vcpu);void (*reset)(struct kvm_vcpu *vcpu);
@@ -115,6 +116,7 @@ int kvm_pmu_is_valid_msr_idx(struct kvm_vcpu *vcpu, unsigned idx);bool kvm_pmu_is_valid_msr (struct kvm_vcpu *vcpu,u32 msr);int kvm_pmu_get_msr (struct kvm_vcpu *vcpu,struct msr_data *msr_info);int kvm_pmu_set_msr (struct kvm_vcpu *vcpu,struct msr_data *msr_info); +void kvm_pmu_sched_in (struct kvm_vcpu *vcpu,int cpu);void kvm_pmu_refresh (struct kvm_vcpu *vcpu);void kvm_pmu_reset (struct kvm_vcpu *vcpu);void kvm_pmu_init (struct kvm_vcpu *vcpu);
arch/x86/kvm/vmx/pmu_intel.c +146 -0
207 lines not on this page · raw message
arch/x86/kvm/vmx/vmx.c +2 -2
@@ -3526,8 +3526,8 @@ static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitm } } -static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap, -u32 msr,int type,bool value) +void vmx_set_intercept_for_msr (unsigned long *msr_bitmap,u32 msr,int type, +bool value) {if (value)vmx_enable_intercept_for_msr (msr_bitmap, msr, type);
arch/x86/kvm/vmx/vmx.h +2 -0
@@ -314,6 +314,8 @@ void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);bool vmx_get_nmi_mask (struct kvm_vcpu *vcpu);void vmx_set_nmi_mask (struct kvm_vcpu *vcpu,bool masked);void vmx_set_virtual_apic_mode (struct kvm_vcpu *vcpu); +void vmx_set_intercept_for_msr (unsigned long *msr_bitmap,u32 msr,int type, +bool value);struct shared_msr_entry *find_msr_entry (struct vcpu_vmx *vmx,u32 msr);void pt_update_intercept_for_msr (struct vcpu_vmx *vmx);
arch/x86/kvm/x86.c +2 -0
@@ -9101,6 +9101,8 @@ void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)void kvm_arch_sched_in (struct kvm_vcpu *vcpu,int cpu) { vcpu->arch.l1tf_flush_l1d = true; + +kvm_pmu_sched_in (vcpu, cpu); kvm_x86_ops->sched_in (vcpu, cpu); }
Signature · 1 line
2.7.4
Re: [PATCH v5 10/12] KVM/x86/lbr: lazy save the guest lbr stack
Quoted 11 lines · Wei Wang
When the vCPU is scheduled in:
- if the lbr feature was used in the last vCPU time slice, set the lbr stack to be interceptible, so that the host can capture whether the lbr feature will be used in this time slice;
- if the lbr feature wasn't used in the last vCPU time slice, disable the vCPU support of the guest lbr switching.Upon the first access to one of the lbr related MSRs (since the vCPU was scheduled in):
- record that the guest has used the lbr;
- create a host perf event to help save/restore the guest lbr stack;
Based on commit "15ad71460" and guest-use-lbr-only usage,
is this possible to create none of host perf event for vcpu
and simply reuse __intel_pmu_lbr_save/restore
in intel_pmu_sched_out/in and keep the lbr_stack sync with kvm_pmu->lbr_stack rather than task_ctx of perf_event ?
Quoted 328 lines
- pass the stack through to the guest.
Suggested-by Andi Kleen <[email protected]>Signed-off-by Wei Wang <[email protected]>Cc Paolo Bonzini <[email protected]>Cc Andi Kleen <[email protected]>Cc Peter Zijlstra <[email protected]>--- arch/x86/include/asm/kvm_host.h | 2 + arch/x86/kvm/pmu.c | 6 ++ arch/x86/kvm/pmu.h | 2 + arch/x86/kvm/vmx/pmu_intel.c | 146 ++++++++++++++++++++++++++++++++++++++++ arch/x86/kvm/vmx/vmx.c | 4 +- arch/x86/kvm/vmx/vmx.h | 2 + arch/x86/kvm/x86.c | 2 + 7 files changed, 162 insertions(+), 2 deletions(-)arch/x86/include/asm/kvm_host.h +2
-0@@ -469,6 +469,8 @@ struct kvm_pmu {u64 counter_bitmask[2 ];u64 global_ctrl_mask;u64 reserved_bits; +/* Indicate if the lbr msrs were accessed in this vCPU time slice */ +bool lbr_used;u8 version;struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC ];struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED ];arch/x86/kvm/pmu.c +6
-0@@ -328,6 +328,12 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)return kvm_x86_ops->pmu_ops->set_msr (vcpu, msr_info); } +void kvm_pmu_sched_in (struct kvm_vcpu *vcpu,int cpu) +{ +if (kvm_x86_ops->pmu_ops->sched_in) + kvm_x86_ops->pmu_ops->sched_in (vcpu, cpu); +} +/* refresh PMU settings. This function generally is called when underlying * settings are changed (such as changes of PMU CPUID by guest VMs), which * should rarely happen. arch/x86/kvm/pmu.h +2
-0@@ -31,6 +31,7 @@ struct kvm_pmu_ops {bool (*lbr_enable)(struct kvm_vcpu *vcpu);int (*get_msr)(struct kvm_vcpu *vcpu,struct msr_data *msr_info);int (*set_msr)(struct kvm_vcpu *vcpu,struct msr_data *msr_info); +void (*sched_in)(struct kvm_vcpu *vcpu,int cpu);void (*refresh)(struct kvm_vcpu *vcpu);void (*init)(struct kvm_vcpu *vcpu);void (*reset)(struct kvm_vcpu *vcpu);@@ -115,6 +116,7 @@ int kvm_pmu_is_valid_msr_idx(struct kvm_vcpu *vcpu, unsigned idx);bool kvm_pmu_is_valid_msr (struct kvm_vcpu *vcpu,u32 msr);int kvm_pmu_get_msr (struct kvm_vcpu *vcpu,struct msr_data *msr_info);int kvm_pmu_set_msr (struct kvm_vcpu *vcpu,struct msr_data *msr_info); +void kvm_pmu_sched_in (struct kvm_vcpu *vcpu,int cpu);void kvm_pmu_refresh (struct kvm_vcpu *vcpu);void kvm_pmu_reset (struct kvm_vcpu *vcpu);void kvm_pmu_init (struct kvm_vcpu *vcpu);arch/x86/kvm/vmx/pmu_intel.c +146
-0@@ -16,10 +16,12 @@#include <linux/perf_event.h> #include <asm/perf_event.h> #include <asm/intel-family.h> +#include <asm/vmx.h> #include "x86.h" #include "cpuid.h" #include "lapic.h" #include "pmu.h" +#include "vmx.h" static struct kvm_event_hw_type_mapping intel_arch_events[] = {/* Index must match CPUID 0x0A.EBX bit vector */ @@ -143,6 +145,17 @@ static struct kvm_pmc *intel_msr_idx_to_pmc(struct kvm_vcpu *vcpu,return &counters[idx]; } +static inline bool msr_is_lbr_stack (struct kvm_vcpu *vcpu,u32 index) +{ +struct x86_perf_lbr_stack *stack = &vcpu->kvm->arch.lbr_stack; +int nr = stack->nr; + +return !!(index == stack->tos || + (index >= stack->from && index < stack->from + nr) || + (index >= stack->to && index < stack->to + nr) || + (index >= stack->info && index < stack->info)); +} +static bool intel_is_valid_msr (struct kvm_vcpu *vcpu,u32 msr) {struct kvm_pmu *pmu =vcpu_to_pmu (vcpu);@@ -154,9 +167,13 @@ static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)case MSR_CORE_PERF_GLOBAL_CTRL :case MSR_CORE_PERF_GLOBAL_OVF_CTRL :case MSR_IA32_PERF_CAPABILITIES : +case MSR_IA32_DEBUGCTLMSR : +case MSR_LBR_SELECT : ret = pmu->version >1 ;break ;default : +if (msr_is_lbr_stack (vcpu, msr)) +return pmu->version >1 ; ret =get_gp_pmc (pmu, msr,MSR_IA32_PERFCTR0 ) ||get_gp_pmc (pmu, msr,MSR_P6_EVNTSEL0 ) ||get_fixed_pmc (pmu, msr);@@ -300,6 +317,109 @@ static bool intel_pmu_lbr_enable(struct kvm_vcpu *vcpu)return true; } +static void intel_pmu_set_intercept_for_lbr_msrs (struct kvm_vcpu *vcpu, +bool set) +{ +unsigned long *msr_bitmap =to_vmx (vcpu)->vmcs01.msr_bitmap; +struct x86_perf_lbr_stack *stack = &vcpu->kvm->arch.lbr_stack; +int nr = stack->nr; +int i; + +vmx_set_intercept_for_msr (msr_bitmap, stack->tos,MSR_TYPE_RW , set); +for (i =0 ; i < nr; i++) { +vmx_set_intercept_for_msr (msr_bitmap, stack->from + i, +MSR_TYPE_RW , set); +vmx_set_intercept_for_msr (msr_bitmap, stack->to + i, +MSR_TYPE_RW , set); +if (stack->info) +vmx_set_intercept_for_msr (msr_bitmap, stack->info + i, +MSR_TYPE_RW , set); + } +} + +static bool intel_pmu_get_lbr_msr (struct kvm_vcpu *vcpu, +struct msr_data *msr_info) +{ +u32 index = msr_info->index; +bool ret = false; + +switch (index) { +case MSR_IA32_DEBUGCTLMSR : + msr_info->data =vmcs_read64 (GUEST_IA32_DEBUGCTL ); + ret = true; +break ; +case MSR_LBR_SELECT : + ret = true; +rdmsrl (index, msr_info->data); +break ; +default : +if (msr_is_lbr_stack (vcpu, index)) { + ret = true; +rdmsrl (index, msr_info->data); + } + } + +return ret; +} + +static bool intel_pmu_set_lbr_msr (struct kvm_vcpu *vcpu, +struct msr_data *msr_info) +{ +u32 index = msr_info->index; +u64 data = msr_info->data; +bool ret = false; + +switch (index) { +case MSR_IA32_DEBUGCTLMSR : + ret = true; +/* +* Currently, only FREEZE_LBRS_ON_PMI and DEBUGCTLMSR_LBR are +* supported. +*/ + data &= (DEBUGCTLMSR_FREEZE_LBRS_ON_PMI |DEBUGCTLMSR_LBR ); +vmcs_write64 (GUEST_IA32_DEBUGCTL , data); +break ; +case MSR_LBR_SELECT : + ret = true; +wrmsrl (index, data); +break ; +default : +if (msr_is_lbr_stack (vcpu, index)) { + ret = true; +wrmsrl (index, data); + } + } + +return ret; +} + +static bool intel_pmu_access_lbr_msr (struct kvm_vcpu *vcpu, +struct msr_data *msr_info, +bool set) +{ +bool ret = false; + +/* +* Some userspace implementations (e.g. QEMU) expects the msrs to be +* always accesible. +*/ +if (!msr_info->host_initiated && !vcpu->kvm->arch.lbr_in_guest) +return false; + +if (set) + ret =intel_pmu_set_lbr_msr (vcpu, msr_info); +else + ret =intel_pmu_get_lbr_msr (vcpu, msr_info); + +if (ret && !vcpu->arch.pmu.lbr_used) { + vcpu->arch.pmu.lbr_used = true; +intel_pmu_set_intercept_for_lbr_msrs (vcpu, false); +intel_pmu_enable_save_guest_lbr (vcpu); + } + +return ret; +} +static int intel_pmu_get_msr (struct kvm_vcpu *vcpu,struct msr_data *msr_info) {struct kvm_pmu *pmu =vcpu_to_pmu (vcpu);@@ -340,6 +460,8 @@ static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) }else if ((pmc =get_gp_pmc (pmu, msr,MSR_P6_EVNTSEL0 ))) { msr_info->data = pmc->eventsel;return 0 ; + }else if (intel_pmu_access_lbr_msr (vcpu, msr_info, false)) { +return 0 ; } }@@ -400,12 +522,33 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)reprogram_gp_counter (pmc, data);return 0 ; } + }else if (intel_pmu_access_lbr_msr (vcpu, msr_info, true)) { +return 0 ; } }return 1 ; } +static void intel_pmu_sched_in (struct kvm_vcpu *vcpu,int cpu) +{ +struct kvm_pmu *pmu =vcpu_to_pmu (vcpu); +u64 guest_debugctl; + +if (pmu->lbr_used) { + pmu->lbr_used = false; +intel_pmu_set_intercept_for_lbr_msrs (vcpu, true); + }else if (pmu->vcpu_lbr_event) { +/* +* The lbr feature wasn't used during that last vCPU time +* slice, so it's time to disable the vCPU side save/restore. +*/ + guest_debugctl =vmcs_read64 (GUEST_IA32_DEBUGCTL ); +if (!(guest_debugctl &DEBUGCTLMSR_LBR )) +intel_pmu_disable_save_guest_lbr (vcpu); + } +} +static void intel_pmu_refresh (struct kvm_vcpu *vcpu) {struct kvm_pmu *pmu =vcpu_to_pmu (vcpu);@@ -492,6 +635,8 @@ static void intel_pmu_reset(struct kvm_vcpu *vcpu) pmu->fixed_ctr_ctrl = pmu->global_ctrl = pmu->global_status = pmu->global_ovf_ctrl =0 ; + +intel_pmu_disable_save_guest_lbr (vcpu); }int intel_pmu_enable_save_guest_lbr (struct kvm_vcpu *vcpu)@@ -571,6 +716,7 @@ struct kvm_pmu_ops intel_pmu_ops = { .lbr_enable = intel_pmu_lbr_enable, .get_msr = intel_pmu_get_msr, .set_msr = intel_pmu_set_msr, + .sched_in = intel_pmu_sched_in, .refresh = intel_pmu_refresh, .init = intel_pmu_init, .reset = intel_pmu_reset,arch/x86/kvm/vmx/vmx.c +2
-2@@ -3526,8 +3526,8 @@ static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitm } } -static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap, -u32 msr,int type,bool value) +void vmx_set_intercept_for_msr (unsigned long *msr_bitmap,u32 msr,int type, +bool value) {if (value)vmx_enable_intercept_for_msr (msr_bitmap, msr, type);arch/x86/kvm/vmx/vmx.h +2
-0@@ -314,6 +314,8 @@ void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);bool vmx_get_nmi_mask (struct kvm_vcpu *vcpu);void vmx_set_nmi_mask (struct kvm_vcpu *vcpu,bool masked);void vmx_set_virtual_apic_mode (struct kvm_vcpu *vcpu); +void vmx_set_intercept_for_msr (unsigned long *msr_bitmap,u32 msr,int type, +bool value);struct shared_msr_entry *find_msr_entry (struct vcpu_vmx *vmx,u32 msr);void pt_update_intercept_for_msr (struct vcpu_vmx *vmx);arch/x86/kvm/x86.c +2
-0@@ -9101,6 +9101,8 @@ void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)void kvm_arch_sched_in (struct kvm_vcpu *vcpu,int cpu) { vcpu->arch.l1tf_flush_l1d = true; + +kvm_pmu_sched_in (vcpu, cpu); kvm_x86_ops->sched_in (vcpu, cpu); }
RE: [PATCH v5 10/12] KVM/x86/lbr: lazy save the guest lbr stack
Quoted 21 lines · Like Xu
To: Wang, Wei W <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]
Cc: Liang, Kan <[email protected]>; [email protected]; [email protected]; Xu, Like <[email protected]>; [email protected]; [email protected]; [email protected]
Subject: Re: [PATCH v5 10/12] KVM/x86/lbr: lazy save the guest lbr stackQuoted 11 lines · Wei Wang
When the vCPU is scheduled in:
- if the lbr feature was used in the last vCPU time slice, set the lbr stack to be interceptible, so that the host can capture whether the lbr feature will be used in this time slice;
- if the lbr feature wasn't used in the last vCPU time slice, disable the vCPU support of the guest lbr switching.Upon the first access to one of the lbr related MSRs (since the vCPU was scheduled in):
- record that the guest has used the lbr;
- create a host perf event to help save/restore the guest lbr stack;
Quoted 4 lines
Based on commit "
15ad71460" and guest-use-lbr-only usage, is this possible to create none of host perf event for vcpu and simply reuse __intel_pmu_lbr_save/restore in intel_pmu_sched_out/in and keep thelbr_stacksync withkvm_pmu->lbr_stackrather thantask_ctxofperf_event?
Yes, both method should work. People may have different opinions about kvm or perf to own the job of lbr switching. Let's see.. if most people vote for kvm to do the switching, I'll make that change.
Otherwise, I'll stay with what we already have.
Best,
Wei
PATCH v5 11/12 KVM/x86: remove the common handling of the debugctl msr
In reply to Wei WangThe debugctl msr is not completely identical on AMD and Intel CPUs, for example, FREEZE_LBRS_ON_PMI is supported by Intel CPUs only. Now, this msr is handled separatedly in svm.c and intel_pmu.c. So remove the common debugctl msr handling code in kvm_get/set_msr_common.
--- arch/x86/kvm/x86.c | 13 ------------- 1 file changed, 13 deletions(-)
arch/x86/kvm/x86.c +0 -13
@@ -2463,18 +2463,6 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)return 1 ; }break ; -case MSR_IA32_DEBUGCTLMSR : -if (!data) { -/* We support the non-activated case already */ -break ; - }else if (data & ~(DEBUGCTLMSR_LBR |DEBUGCTLMSR_BTF )) { -/* Values other than LBR and BTF are vendor-specific, -thus reserved and should throw a #GP */ -return 1 ; - } -vcpu_unimpl (vcpu,"%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n" , - __func__, data); -break ; case 0x200 ... 0x2ff:return kvm_mtrr_set_msr (vcpu, msr, data);case MSR_IA32_APICBASE :
@@ -2716,7 +2704,6 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)switch (msr_info->index) {case MSR_IA32_PLATFORM_ID :case MSR_IA32_EBL_CR_POWERON : -case MSR_IA32_DEBUGCTLMSR :case MSR_IA32_LASTBRANCHFROMIP :case MSR_IA32_LASTBRANCHTOIP :case MSR_IA32_LASTINTFROMIP :
Signature · 1 line
2.7.4
PATCH v5 12/12 KVM/VMX/vPMU: support to report GLOBAL_STATUS_LBRS_FROZEN
In reply to Wei WangArch v4 supports streamlined Freeze_LBR_on_PMI, so we set the GLOBAL_STATUS_LBRS_FROZEN bit when the guest reads the global status msr with freezing lbr in use.
--- arch/x86/kvm/vmx/pmu_intel.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-)
arch/x86/kvm/vmx/pmu_intel.c +20 -1
@@ -420,6 +420,25 @@ static bool intel_pmu_access_lbr_msr(struct kvm_vcpu *vcpu,return ret; } +static void intel_pmu_get_global_status (struct kvm_pmu *pmu, +struct msr_data *msr_info) +{ +u64 guest_debugctl, freeze_lbr_bits =DEBUGCTLMSR_FREEZE_LBRS_ON_PMI | +DEBUGCTLMSR_LBR ; + +if (!pmu->global_status) { + msr_info->data =0 ; +return ; + } + + msr_info->data = pmu->global_status; +if (pmu->version >=4 ) { + guest_debugctl =vmcs_read64 (GUEST_IA32_DEBUGCTL ); +if ((guest_debugctl & freeze_lbr_bits) == freeze_lbr_bits) + msr_info->data |=GLOBAL_STATUS_LBRS_FROZEN ; + } +} +static int intel_pmu_get_msr (struct kvm_vcpu *vcpu,struct msr_data *msr_info) {struct kvm_pmu *pmu =vcpu_to_pmu (vcpu);
@@ -431,7 +450,7 @@ static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) msr_info->data = pmu->fixed_ctr_ctrl;return 0 ;case MSR_CORE_PERF_GLOBAL_STATUS : - msr_info->data = pmu->global_status; +intel_pmu_get_global_status (pmu, msr_info);return 0 ;case MSR_CORE_PERF_GLOBAL_CTRL : msr_info->data = pmu->global_ctrl;
Signature · 1 line
2.7.4
Re: [PATCH v5 12/12] KVM/VMX/vPMU: support to report GLOBAL_STATUS_LBRS_FROZEN
Quoted 5 lines
arch/x86/kvm/vmx/pmu_intel.c +5
-0+static void intel_pmu_get_global_status (struct kvm_pmu *pmu, +struct msr_data *msr_info) +{ +u64 guest_debugctl, freeze_lbr_bits =DEBUGCTLMSR_FREEZE_LBRS_ON_PMI | +DEBUGCTLMSR_LBR ;
arch/x86/kvm/vmx/pmu_intel.c static bool intel_pmu_access_lbr_msr(struct kvm_vcpu *vcpu, · line 437
Quoted 10 lines
arch/x86/kvm/vmx/pmu_intel.c +10
-0+ +if (!pmu->global_status) { + msr_info->data =0 ; +return ; + } + + msr_info->data = pmu->global_status; +if (pmu->version >=4 ) { + guest_debugctl =vmcs_read64 (GUEST_IA32_DEBUGCTL ); +if ((guest_debugctl & freeze_lbr_bits) == freeze_lbr_bits)
It should only check for the freeze bit, the freeze bit can be set even when LBRs are disabled.
Also you seem to set the bit unconditionally?
That doesn't seem right. It should only be set after an overflow.
So the PMI injection needs to set it.
-Andi
RE: [PATCH v5 12/12] KVM/VMX/vPMU: support to report GLOBAL_STATUS_LBRS_FROZEN
Quoted 21 lines · Andi Kleen
arch/x86/kvm/vmx/pmu_intel.c static bool intel_pmu_access_lbr_msr(struct kvm_vcpu *vcpu,
Quoted 5 lines
arch/x86/kvm/vmx/pmu_intel.c +4
-0+static void intel_pmu_get_global_status (struct kvm_pmu *pmu, +struct msr_data *msr_info) +{ + u64 guest_debugctl, freeze_lbr_bits =
DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|arch/x86/kvm/vmx/pmu_intel.c static bool intel_pmu_access_lbr_msr(struct kvm_vcpu *vcpu, · line 437
Quoted 11 lines
arch/x86/kvm/vmx/pmu_intel.c +11
-0+DEBUGCTLMSR_LBR ; + +if (!pmu->global_status) { + msr_info->data =0 ; +return ; + } + + msr_info->data = pmu->global_status; +if (pmu->version >=4 ) { + guest_debugctl =vmcs_read64 (GUEST_IA32_DEBUGCTL ); +if ((guest_debugctl & freeze_lbr_bits) == freeze_lbr_bits)It should only check for the freeze bit, the freeze bit can be set even when LBRs are disabled.
Quoted 4 lines
Also you seem to set the bit unconditionally?
That doesn't seem right. It should only be set after an overflow.So the PMI injection needs to set it.
OK. The freeze bits need to be cleared by IA32_PERF_GLOBAL_STATUS_RESET, which seems not supported by the perf code yet (thus guest won't clear them). Would handle_irq_v4 also need to be changed to support that?
Best,
Wei
Re: [PATCH v5 12/12] KVM/VMX/vPMU: support to report GLOBAL_STATUS_LBRS_FROZEN
Quoted 22 lines · Wei W
Quoted 21 lines · Andi Kleen
arch/x86/kvm/vmx/pmu_intel.c static bool intel_pmu_access_lbr_msr(struct kvm_vcpu *vcpu,
Quoted 5 lines
arch/x86/kvm/vmx/pmu_intel.c +4
-0+static void intel_pmu_get_global_status (struct kvm_pmu *pmu, +struct msr_data *msr_info) +{ + u64 guest_debugctl, freeze_lbr_bits =
DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|arch/x86/kvm/vmx/pmu_intel.c static bool intel_pmu_access_lbr_msr(struct kvm_vcpu *vcpu, · line 437
Quoted 11 lines
arch/x86/kvm/vmx/pmu_intel.c +11
-0+DEBUGCTLMSR_LBR ; + +if (!pmu->global_status) { + msr_info->data =0 ; +return ; + } + + msr_info->data = pmu->global_status; +if (pmu->version >=4 ) { + guest_debugctl =vmcs_read64 (GUEST_IA32_DEBUGCTL ); +if ((guest_debugctl & freeze_lbr_bits) == freeze_lbr_bits)It should only check for the freeze bit, the freeze bit can be set even when LBRs are disabled.
Quoted 6 lines
Quoted 4 lines
Also you seem to set the bit unconditionally?
That doesn't seem right. It should only be set after an overflow.So the PMI injection needs to set it.
OK. The freeze bits need to be cleared by
IA32_PERF_GLOBAL_STATUS_RESET, which seems not supported by the perf code yet (thus guest won't clear them). Wouldhandle_irq_v4also need to be changed to support that?
In Arch Perfmon v4 it is cleared by the MSR_CORE_PERF_GLOBAL_OVF_CTRL write
But the guest KVM pmu doesn't support v4 so far, so the only way to clear it is through DEBUGCTL.
STATUS_RESET would only be needed to set it from the guest, which is not necessary at least for now (and would be also v4)
At some point the guest PMU should probably be updated for v4, but it can be done separately from this.
-Andi
Re: [PATCH v5 12/12] KVM/VMX/vPMU: support to report GLOBAL_STATUS_LBRS_FROZEN
Quoted 3 lines · Andi Kleen
OK. The freeze bits need to be cleared by
IA32_PERF_GLOBAL_STATUS_RESET, which seems not supported by the perf code yet (thus guest won't clear them). Wouldhandle_irq_v4also need to be changed to support that? In Arch Perfmon v4 it is cleared by theMSR_CORE_PERF_GLOBAL_OVF_CTRLwrite
Not very sure about this one. The spec 18.2.4.2 mentions "IA32_PERF_GLOBAL_STATUS_RESET provides additional bit fields to clear the new indicators.." IIUIC, the new freeze bits can only be cleared by RESET.
Quoted 8 lines
But the guest KVM pmu doesn't support v4 so far, so the only way to clear it is through DEBUGCTL.
STATUS_RESETwould only be needed to set it from the guest, which is not necessary at least for now (and would be also v4)At some point the guest PMU should probably be updated for v4, but it can be done separately from this.
Agree. I think the guest perf won't work in v4 mode if the KVM vPMU exposes it is v3. Probably we could also leave the freeze bits virtualization support to another series of vPMU v4 support? We would also need to use the STATUS_SET in v4 to set the freeze bits of GLOBAL_STATUS when entering the guest (instead of clearing the guest debugctl), so that we could achieve architectural emulation.
Best,
Wei