arm64: hibernate: Avoid sending cross-calling with interrupts disabled

PATCH Applied Will Deacon 2 participants 2 messages Dec 7, 2018

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Stable branch arm64

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Will Deacon

author

2018-12-07 12:46 UTC #0 lore raw

PATCH 1/1 arm64: hibernate: Avoid sending cross-calling with interrupts disabled

Since commit 3b8c9f1cdfc50 ("arm64: IPI each CPU after invalidating the I-cache for kernel mappings"), a call to flush_icache_range() will use an IPI to cross-call other online CPUs so that any stale instructions are flushed from their pipelines. This triggers a WARN during the hibernation resume path, where flush_icache_range() is called with interrupts disabled and is therefore prone to deadlock:

  | Disabling non-boot CPUs ...
  | CPU1: shutdown
  | psci: CPU1 killed.
  | CPU2: shutdown
  | psci: CPU2 killed.
  | CPU3: shutdown
  | psci: CPU3 killed.
  | WARNING: CPU: 0 PID: 1 at ../kernel/smp.c:416 smp_call_function_many+0xd4/0x350
  | Modules linked in:
  | CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.20.0-rc4 #1

Since all secondary CPUs have been taken offline prior to invalidating the I-cache, there's actually no need for an IPI and we can simply call __flush_icache_range() instead.

Cc <[email protected]>

Fixes 3b8c9f1cdfc50 ("arm64: IPI each CPU after invalidating the I-cache for kernel mappings")

Reported-by Kunihiko Hayashi <[email protected]>

Tested-by Kunihiko Hayashi <[email protected]>

Tested-by James Morse <[email protected]>

Signed-off-by Will Deacon <[email protected]>

---
 arch/arm64/kernel/hibernate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm64/kernel/hibernate.c +1 -1

index 6b2686d54411..29cdc99688f3 100644
@@ -214,7 +214,7 @@ static int create_safe_exec_page(void *src_start, size_t length,
 	}
 
 	memcpy((void *)dst, src_start, length);
-	flush_icache_range(dst, dst + length);
+	__flush_icache_range(dst, dst + length);
 
 	pgdp = pgd_offset_raw(allocator(mask), dst_addr);
 	if (pgd_none(READ_ONCE(*pgdp))) {

Signature · 1 line

2.1.4

Catalin Marinas

maintainer Applied

2018-12-07 15:52 UTC #1 lore raw

Quoted 22 lines · Will Deacon

Since commit 3b8c9f1cdfc50 ("arm64: IPI each CPU after invalidating the I-cache for kernel mappings"), a call to flush_icache_range() will use an IPI to cross-call other online CPUs so that any stale instructions are flushed from their pipelines. This triggers a WARN during the hibernation resume path, where flush_icache_range() is called with interrupts disabled and is therefore prone to deadlock:
  | Disabling non-boot CPUs ...
  | CPU1: shutdown
  | psci: CPU1 killed.
  | CPU2: shutdown
  | psci: CPU2 killed.
  | CPU3: shutdown
  | psci: CPU3 killed.
  | WARNING: CPU: 0 PID: 1 at ../kernel/smp.c:416 smp_call_function_many+0xd4/0x350
  | Modules linked in:
  | CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.20.0-rc4 #1
Since all secondary CPUs have been taken offline prior to invalidating the I-cache, there's actually no need for an IPI and we can simply call __flush_icache_range() instead.

Quoted 6 lines

Cc <[email protected]>
Fixes 3b8c9f1cdfc50 ("arm64: IPI each CPU after invalidating the I-cache for kernel mappings")
Reported-by Kunihiko Hayashi <[email protected]>
Tested-by Kunihiko Hayashi <[email protected]>
Tested-by James Morse <[email protected]>
Signed-off-by Will Deacon <[email protected]>

Queued for 4.20. Thanks.

Signature · 1 line

Catalin