ARM/MIPS: DTS: add child nodes describing the PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more)
Subsystems (5)
v3 cover ARM/MIPS: DTS: add child nodes describing the PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more)
* reworked YAML format with help by Rob Herring
* removed .txt binding document
* change compatible "ti,am335x-sgx" to "ti,am3352-sgx" - suggested by Tony Lindgren
PATCH V2 2019-11-07 12:06:17:
* tried to convert bindings to YAML format - suggested by Rob Herring
* added JZ4780 DTS node (proven to load the driver)
* removed timer and img,cores properties until we know we really need them - suggested by Rob Herring
PATCH V1 2019-10-18 20:46:35:
This patch series defines child nodes for the SGX5xx interface inside different SoC so that a driver can be found and probed by the compatible strings and can retrieve information about the SGX revision that is included in a specific SoC. It also defines the interrupt number to be used by the SGX driver.
There is currently no mainline driver for these GPUs, but a project [1] is ongoing with the goal to get the open-source part as provided by TI/IMG and others into drivers/gpu/drm/pvrsgx.
The kernel modules built from this project have successfully demonstrated to work with the DTS definitions from this patch set on AM335x BeagleBone Black, DM3730 and OMAP5 Pyra and Droid 4. They partially work on OMAP3530 and PandaBoard ES but that is likely a problem in the kernel driver or the (non-free) user-space libraries and binaries.
Wotk for JZ4780 (CI20 board) is in progress and there is potential to extend this work to e.g. BananaPi-M3 (A83) and some Intel Poulsbo and CedarView devices.
[1]: https://github.com/openpvrsgx-devgroup
H. Nikolaus Schaller (8):
dt-bindings: add img,pvrsgx.yaml for Imagination GPUs
ARM: DTS: am33xx: add sgx gpu child node
ARM: DTS: am3517: add sgx gpu child node
ARM: DTS: omap3: add sgx gpu child node
ARM: DTS: omap36xx: add sgx gpu child node
ARM: DTS: omap4: add sgx gpu child node
ARM: DTS: omap5: add sgx gpu child node
MIPS: DTS: jz4780: add sgx gpu node
.../devicetree/bindings/gpu/img,pvrsgx.yaml | 83 +++++++++++++++++++ arch/arm/boot/dts/am33xx.dtsi | 38 ++++++++- arch/arm/boot/dts/am3517.dtsi | 11 +-- arch/arm/boot/dts/omap34xx.dtsi | 11 +-- arch/arm/boot/dts/omap36xx.dtsi | 11 +-- arch/arm/boot/dts/omap4.dtsi | 9 +- arch/arm/boot/dts/omap4470.dts | 15 ++++ arch/arm/boot/dts/omap5.dtsi | 9 +- arch/mips/boot/dts/ingenic/jz4780.dtsi | 11 +++ 9 files changed, 171 insertions(+), 27 deletions(-) create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml create mode 100644 arch/arm/boot/dts/omap4470.dts
Signature · 1 line
2.23.0
PATCH v3 1/8 dt-bindings: add img,pvrsgx.yaml for Imagination GPUs
The Imagination PVR/SGX GPU is part of several SoC from multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo and others.
With this binding, we describe how the SGX processor is interfaced to the SoC (registers, interrupt etc.).
In most cases, Clock, Reset and power management is handled by a parent node or elsewhere.
Tested by make dt_binding_check dtbs_check
--- .../devicetree/bindings/gpu/img,pvrsgx.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +83 -0
@@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Imagination PVR/SGX GPU + +maintainers: + - H. Nikolaus Schaller <[email protected]> + +description: |+ + This binding describes the Imagination SGX5 series of 3D accelerators which + are found in several different SoC like TI OMAP, Sitara, Ingenic JZ4780, + Allwinner A83, and Intel Poulsbo and CedarView and more. + + For an almost complete list see: https://en.wikipedia.org/wiki/PowerVR#Implementations + + Only the Imagination SGX530, SGX540 and SGX544 GPUs are currently covered by + this binding but the extension of the pattern is straightforward. + + The SGX node is usually a child node of some DT node belonging to the SoC + which handles clocks, reset and general address space mapping of the SGX + register area. + +properties: + compatible: + enum: + # BeagleBoard ABC, OpenPandora 600MHz + - ti,omap3-sgx530-121, img,sgx530-121, img,sgx530, img,sgx5 + # BeagleBoard XM, GTA04, OpenPandora 1GHz + - ti,omap3-sgx530-125, img,sgx530-125, img,sgx530, img,sgx5 + # BeagleBone Black + - ti,am3352-sgx530-125, img,sgx530-125, img,sgx530, img,sgx5 + # Pandaboard, Pandaboard ES + - ti,omap4-sgx540-120, img,sgx540-120, img,sgx540, img,sgx5 + - ti,omap4-sgx544-112, img,sgx544-112, img,sgx544, img,sgx5 + # OMAP5 UEVM, Pyra Handheld + - ti,omap5-sgx544-116, img,sgx544-116, img,sgx544, img,sgx5 + - ti,dra7-sgx544-116, img,sgx544-116, img,sgx544, img,sgx5 + # CI20 + - ingenic,jz4780-sgx540-120, img,sgx540-120, img,sgx540, img,sgx5 + # the following entries are not validated with real hardware + # more TI + - ti,am3517-sgx530-125, img,sgx530-125, img,sgx530, img,sgx5 + - ti,am4-sgx530-125, img,sgx530-125, img,sgx530, img,sgx5 + - ti,ti81xx-sgx530-125, img,sgx530-125, img,sgx530, img,sgx5 + # Banana-Pi-M3 (Allwinner A83T) + - allwinner,sun8i-a83t-sgx544-116, img,sgx544-116, img,sgx544, img,sgx5 + # Atom Z5xx + - intel,poulsbo-gma500-sgx535, img,sgx535-116, img,sgx535, img,sgx5 + # Atom Z24xx + - intel,medfield-gma-sgx540, img,sgx540-116, img,sgx540, img,sgx5 + # Atom N2600, D2500 + - intel,cedarview-gma3600-sgx545, img,sgx545-116, img,sgx545, img,sgx5 + + reg: + maxItems: 1 + description: physical base address and length of the register area + + interrupts: + maxItems: 1 + description: interrupt line from SGX subsystem to core processor + + clocks: + description: optional clocks + +required: + - compatible + - reg + - interrupts + +examples: + - |+ + #include <dt-bindings/interrupt-controller/arm-gic.h> + + gpu@fe00 { + compatible = "ti,omap-omap5-sgx544-116", "img,sgx544-116", "img,sgx544", "img,sgx5"; + reg = <0xfe00 0x200>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + }; + +...
Signature · 1 line
2.23.0
Rob Herring
maintainerRe: [PATCH v3 1/8] dt-bindings: add img,pvrsgx.yaml for Imagination GPUs
Quoted 24 lines · H. Nikolaus Schaller
The Imagination PVR/SGX GPU is part of several SoC from multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo and others.
With this binding, we describe how the SGX processor is interfaced to the SoC (registers, interrupt etc.).
In most cases, Clock, Reset and power management is handled by a parent node or elsewhere.
Tested by make
dt_binding_checkdtbs_checkSigned-off-by H. Nikolaus Schaller <[email protected]>--- .../devicetree/bindings/gpu/img,pvrsgx.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yamlDocumentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +0
-0
Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml line 1
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Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +1
-0@@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0
Dual license new bindings: (GPL-2.0-only OR BSD-2-Clause)
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Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +18
-0+%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Imagination PVR/SGX GPU + +maintainers: + - H. Nikolaus Schaller <[email protected]> + +description: |+ + This binding describes the Imagination SGX5 series of 3D accelerators which + are found in several different SoC like TI OMAP, Sitara, Ingenic JZ4780, + Allwinner A83, and Intel Poulsbo and CedarView and more. + + For an almost complete list see: https://en.wikipedia.org/wiki/PowerVR#Implementations + + Only the Imagination SGX530, SGX540 and SGX544 GPUs are currently covered by
Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml line 29
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Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +10
-0+ this binding but the extension of the pattern is straightforward. + + The SGX node is usually a child node of some DT node belonging to the SoC + which handles clocks, reset and general address space mapping of the SGX + register area. + +properties: + compatible: + enum: + # BeagleBoard ABC, OpenPandora 600MHz
I'd expect compatibles to be per SoC, not per board.
Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml line 30
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Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +1
-0+ - ti,omap3-sgx530-121, img,sgx530-121, img,sgx530, img,sgx5
4 compatibles is probably a bit much. Are there not any version or feature registers that some of this could be detected? If there are, I'd assume the middle 2 strings could be dropped. If not, drop the last one and just match on the 3rd string. It's not a long list.
Quoted 19 lines
Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +19
-0+ # BeagleBoard XM, GTA04, OpenPandora 1GHz + - ti,omap3-sgx530-125, img,sgx530-125, img,sgx530, img,sgx5 + # BeagleBone Black + - ti,am3352-sgx530-125, img,sgx530-125, img,sgx530, img,sgx5 + # Pandaboard, Pandaboard ES + - ti,omap4-sgx540-120, img,sgx540-120, img,sgx540, img,sgx5 + - ti,omap4-sgx544-112, img,sgx544-112, img,sgx544, img,sgx5 + # OMAP5 UEVM, Pyra Handheld + - ti,omap5-sgx544-116, img,sgx544-116, img,sgx544, img,sgx5 + - ti,dra7-sgx544-116, img,sgx544-116, img,sgx544, img,sgx5 + # CI20 + - ingenic,jz4780-sgx540-120, img,sgx540-120, img,sgx540, img,sgx5 + # the following entries are not validated with real hardware + # more TI + - ti,am3517-sgx530-125, img,sgx530-125, img,sgx530, img,sgx5 + - ti,am4-sgx530-125, img,sgx530-125, img,sgx530, img,sgx5 + - ti,ti81xx-sgx530-125, img,sgx530-125, img,sgx530, img,sgx5 + # Banana-Pi-M3 (Allwinner A83T) + - allwinner,sun8i-a83t-sgx544-116, img,sgx544-116, img,sgx544, img,sgx5
Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml line 59
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Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +10
-0+ # Atom Z5xx + - intel,poulsbo-gma500-sgx535, img,sgx535-116, img,sgx535, img,sgx5 + # Atom Z24xx + - intel,medfield-gma-sgx540, img,sgx540-116, img,sgx540, img,sgx5 + # Atom N2600, D2500 + - intel,cedarview-gma3600-sgx545, img,sgx545-116, img,sgx545, img,sgx5 + + reg: + maxItems: 1 + description: physical base address and length of the register area
No need to give a generic description of a standard property.
Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml line 63
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Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +4
-0+ + interrupts: + maxItems: 1 + description: interrupt line from SGX subsystem to core processor
Same here.
Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml line 66
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Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +3
-0+ + clocks: + description: optional clocks
Need to define how many and what they are. Or drop until you know.
Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml line 71
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Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +5
-0+ +required: + - compatible + - reg + - interrupts
Add:
additionalProperties: false
Quoted 15 lines
Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +12
-0+ +examples: + - |+ + #include <dt-bindings/interrupt-controller/arm-gic.h> + + gpu@fe00 { + compatible = "ti,omap-omap5-sgx544-116", "img,sgx544-116", "img,sgx544", "img,sgx5"; + reg = <0xfe00 0x200>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + }; + +...Signature · 1 line
2.23.0
Re: [PATCH v3 1/8] dt-bindings: add img,pvrsgx.yaml for Imagination GPUs
Hi Rob,
sorry for the delay. I wanted to wait for v5.5-rc1 and it did take longer...
Quoted 21 lines
Am 05.12.2019 um 18:01 schrieb Rob Herring <[email protected]>:
Quoted 18 lines · H. Nikolaus Schaller
The Imagination PVR/SGX GPU is part of several SoC from multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo and others.
With this binding, we describe how the SGX processor is interfaced to the SoC (registers, interrupt etc.).
In most cases, Clock, Reset and power management is handled by a parent node or elsewhere.
Tested by make
dt_binding_checkdtbs_checkSigned-off-by H. Nikolaus Schaller <[email protected]>---
.../devicetree/bindings/gpu/img,pvrsgx.yaml| 83 +++++++++++++++++++1 file changed, 83 insertions(+)create mode 100644
Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
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Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml line 1
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Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +1
-0@@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0Dual license new bindings: (GPL-2.0-only OR BSD-2-Clause)
What are the consequences?
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Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +22
-0+%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Imagination PVR/SGX GPU + +maintainers: + - H. Nikolaus Schaller <[email protected]> + +description: |+ + This binding describes the Imagination SGX5 series of 3D accelerators which + are found in several different SoC like TI OMAP, Sitara, Ingenic JZ4780, + Allwinner A83, and Intel Poulsbo and CedarView and more. + + For an almost complete list see: https://en.wikipedia.org/wiki/PowerVR#Implementations + + Only the Imagination SGX530, SGX540 and SGX544 GPUs are currently covered by + this binding but the extension of the pattern is straightforward. + + The SGX node is usually a child node of some DT node belonging to the SoC + which handles clocks, reset and general address space mapping of the SGX
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Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml line 29
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Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +6
-0+ register area. + +properties: + compatible: + enum: + # BeagleBoard ABC, OpenPandora 600MHzI'd expect compatibles to be per SoC, not per board.
Yes.
The boards are examples I can test, but any board with the same SoC should work. I have added "Example: " in front of all these comments.
Quoted 5 lines
Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml line 30
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Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +1
-0+ - ti,omap3-sgx530-121, img,sgx530-121, img,sgx530, img,sgx54 compatibles is probably a bit much. Are there not any version or feature registers that some of this could be detected?
Well, there are hints that they exist but there is no good documentation about it. This means that at the moment the user-space must be able to identify the correct blobs that are to be used for a specific SoC. And we need different variants compiled as .ko and loaded on demand.
The first one is also used to match different .ko builds from the same source tree with different macro definitions for the individual SoC.
It may be possible that we end up in a more generic driver that only matches on one of the second to fourth compatible record, and asks runtime API about the SoC, but at the moment this does not exist.
Quoted 3 lines
If there are, I'd
assume the middle 2 strings could be dropped. If not, drop the last one and just match on the 3rd string. It's not a long list.
The fourth one is intended to be able distinguish between sgx5 and sgx6.
I also found that I have not defined it in most of the device tree patches.
But yes, we can drop it since AFAIK there are no activities for sgx6. And if they start, we can update bindings and boards.
Quoted 31 lines
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Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +19
-0+ # BeagleBoard XM, GTA04, OpenPandora 1GHz + - ti,omap3-sgx530-125, img,sgx530-125, img,sgx530, img,sgx5 + # BeagleBone Black + - ti,am3352-sgx530-125, img,sgx530-125, img,sgx530, img,sgx5 + # Pandaboard, Pandaboard ES + - ti,omap4-sgx540-120, img,sgx540-120, img,sgx540, img,sgx5 + - ti,omap4-sgx544-112, img,sgx544-112, img,sgx544, img,sgx5 + # OMAP5 UEVM, Pyra Handheld + - ti,omap5-sgx544-116, img,sgx544-116, img,sgx544, img,sgx5 + - ti,dra7-sgx544-116, img,sgx544-116, img,sgx544, img,sgx5 + # CI20 + - ingenic,jz4780-sgx540-120, img,sgx540-120, img,sgx540, img,sgx5 + # the following entries are not validated with real hardware + # more TI + - ti,am3517-sgx530-125, img,sgx530-125, img,sgx530, img,sgx5 + - ti,am4-sgx530-125, img,sgx530-125, img,sgx530, img,sgx5 + - ti,ti81xx-sgx530-125, img,sgx530-125, img,sgx530, img,sgx5 + # Banana-Pi-M3 (Allwinner A83T) + - allwinner,sun8i-a83t-sgx544-116, img,sgx544-116, img,sgx544, img,sgx5Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml line 59
Quoted 10 lines
Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +10
-0+ # Atom Z5xx + - intel,poulsbo-gma500-sgx535, img,sgx535-116, img,sgx535, img,sgx5 + # Atom Z24xx + - intel,medfield-gma-sgx540, img,sgx540-116, img,sgx540, img,sgx5 + # Atom N2600, D2500 + - intel,cedarview-gma3600-sgx545, img,sgx545-116, img,sgx545, img,sgx5 + + reg: + maxItems: 1 + description: physical base address and length of the register area
Quoted 1 line
No need to give a generic description of a standard property.
Ok. Dropped.
Quoted 7 lines
Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml line 63
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Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +4
-0+ + interrupts: + maxItems: 1 + description: interrupt line from SGX subsystem to core processorSame here.
Ok. Dropped.
Quoted 6 lines
Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml line 66
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Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +3
-0+ + clocks: + description: optional clocksNeed to define how many and what they are. Or drop until you know.
It differs depending on the integration of the SoC. OMAP does not need any clock defintions on the gpu node (clocks are handled by sysc parent) while JZ4780 needs one (at least in the v3.18 vendor kernel with working SGX).
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Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml line 71
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Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +5
-0+ +required: + - compatible + - reg + - interruptsAdd:
additionalProperties: false
Ok.
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Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +12
-0+ +examples: + - |+ + #include <dt-bindings/interrupt-controller/arm-gic.h> + + gpu@fe00 { + compatible = "ti,omap-omap5-sgx544-116", "img,sgx544-116", "img,sgx544", "img,sgx5"; + reg = <0xfe00 0x200>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + }; + +...Signature · 1 line
2.23.0
[PATCH v4] coming.
BR and thanks,
Nikolaus
PATCH v3 2/8 ARM: DTS: am33xx: add sgx gpu child node
In reply to H. Nikolaus Schallerand add timer and interrupt
--- arch/arm/boot/dts/am33xx.dtsi | 38 +++++++++++++++++++++++++++++++---- 1 file changed, 34 insertions(+), 4 deletions(-)
arch/arm/boot/dts/am33xx.dtsi +34 -4
@@ -480,13 +480,43 @@ #size-cells = <1>; ranges = <0 0x56000000 0x1000000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + sgx: gpu@0 { + compatible = "ti,am3352-sgx530-125", "img,sgx530-125", "img,sgx530"; + reg = <0x00 0x1000000>; /* 16 MB */ + interrupts = <37>; + }; }; }; }; #include "am33xx-l4.dtsi" #include "am33xx-clocks.dtsi" + +&prcm { + prm_per: prm@c00 { + compatible = "ti,am3-prm-inst"; + reg = <0xc00 0x100>; + #reset-cells = <1>; + clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>; + }; + + prm_wkup: prm@d00 { + compatible = "ti,am3-prm-inst"; + reg = <0xd00 0x100>; + #reset-cells = <1>; + clocks = <&l4_wkup_clkctrl AM3_WKUP_M3_CLKCTRL 0>; + }; + + prm_device: prm@f00 { + compatible = "ti,am3-prm-inst"; + reg = <0xf00 0x100>; + #reset-cells = <1>; + }; + + prm_gfx: prm@1100 { + compatible = "ti,am3-prm-inst"; + reg = <0x1100 0x100>; + #reset-cells = <1>; + clocks = <&gfx_l3_clkctrl AM3_GFX_CLKCTRL 0>; + }; +};
Signature · 1 line
2.23.0
PATCH v3 3/8 ARM: DTS: am3517: add sgx gpu child node
In reply to H. Nikolaus Schallerand add interrupt.
--- arch/arm/boot/dts/am3517.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)
arch/arm/boot/dts/am3517.dtsi +6 -5
@@ -97,7 +97,7 @@ * revision register instead of the unreadable OCP revision * register. */ - sgx_module: target-module@50000000 { + target-module@50000000 { compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x50000014 0x4>; reg-names = "rev";
@@ -107,10 +107,11 @@ #size-cells = <1>; ranges = <0 0x50000000 0x4000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + sgx: gpu@0 { + compatible = "ti,am3517-sgx530-125", "img,sgx530-125", "img,sgx530"; + reg = <0x0 0x4000>; + interrupts = <21>; + }; }; }; };
Signature · 1 line
2.23.0
PATCH v3 4/8 ARM: DTS: omap3: add sgx gpu child node
In reply to H. Nikolaus Schallerand add interrupt
--- arch/arm/boot/dts/omap34xx.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)
arch/arm/boot/dts/omap34xx.dtsi +6 -5
@@ -111,7 +111,7 @@ * are also different clocks, but we do not have any dts users * for it. */ - sgx_module: target-module@50000000 { + target-module@50000000 { compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x50000014 0x4>; reg-names = "rev";
@@ -121,10 +121,11 @@ #size-cells = <1>; ranges = <0 0x50000000 0x4000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + sgx: gpu@0 { + compatible = "ti,omap3-sgx530-121", "img,sgx530-121", "img,sgx530"; + reg = <0x0 0x4000>; /* 64kB */ + interrupts = <21>; + }; }; };
Signature · 1 line
2.23.0
PATCH v3 5/8 ARM: DTS: omap36xx: add sgx gpu child node
In reply to H. Nikolaus Schallerand add interrupt.
--- arch/arm/boot/dts/omap36xx.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)
arch/arm/boot/dts/omap36xx.dtsi +6 -5
@@ -145,7 +145,7 @@ * "ti,sysc-omap4" type register with just sidle and midle bits * available while omap34xx has "ti,sysc-omap2" type sysconfig. */ - sgx_module: target-module@50000000 { + target-module@50000000 { compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x5000fe00 0x4>, <0x5000fe10 0x4>;
@@ -162,10 +162,11 @@ #size-cells = <1>; ranges = <0 0x50000000 0x2000000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + sgx: gpu@0 { + compatible = "ti,omap3-sgx530-125", "img,sgx530-125", "img,sgx530"; + reg = <0x0 0x10000>; /* 64kB */ + interrupts = <21>; + }; }; };
Signature · 1 line
2.23.0
PATCH v3 6/8 ARM: DTS: omap4: add sgx gpu child node
In reply to H. Nikolaus Schallerand add interrupt.
Since omap4420/30/60 and omap4470 come with different SGX variants we need to introduce a new omap4470.dtsi. If an omap4470 board does not want to use SGX it is no problem to still include omap4460.dtsi.
--- arch/arm/boot/dts/omap4.dtsi | 9 +++++---- arch/arm/boot/dts/omap4470.dts | 15 +++++++++++++++ 2 files changed, 20 insertions(+), 4 deletions(-) create mode 100644 arch/arm/boot/dts/omap4470.dts
arch/arm/boot/dts/omap4.dtsi +5 -4
@@ -347,10 +347,11 @@ #size-cells = <1>; ranges = <0 0x56000000 0x2000000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + sgx: img@0 { + compatible = "ti,omap4-sgx540-120", "img,sgx540-120", "img,sgx540"; + reg = <0x0 0x2000000>; /* 32MB */ + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + }; }; dss: dss@58000000 {
arch/arm/boot/dts/omap4470.dts new file +15 -0
@@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for OMAP4470 SoC + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ +#include "omap4460.dtsi" + +&sgx { + compatible = "img,sgx544-112", "img,sgx544", "ti,omap-omap4-sgx544-112"; +};
Signature · 1 line
2.23.0
PATCH v3 7/8 ARM: DTS: omap5: add sgx gpu child node
In reply to H. Nikolaus Schallerand add interrupt.
--- arch/arm/boot/dts/omap5.dtsi | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)
arch/arm/boot/dts/omap5.dtsi +5 -4
@@ -274,10 +274,11 @@ #size-cells = <1>; ranges = <0 0x56000000 0x2000000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + sgx: gpu@0 { + compatible = "ti,omap5-sgx544-116", "img,sgx544-116", "img,sgx544"; + reg = <0x0 0x10000>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + }; }; dss: dss@58000000 {
Signature · 1 line
2.23.0
PATCH v3 8/8 MIPS: DTS: jz4780: add sgx gpu node
In reply to H. Nikolaus Schallerand add interrupt and clocks.
Tested to build for CI20 board and load a (non-working) driver.
--- arch/mips/boot/dts/ingenic/jz4780.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+)
arch/mips/boot/dts/ingenic/jz4780.dtsi +11 -0
@@ -46,6 +46,17 @@ #clock-cells = <1>; }; + gpu: gpu@13040000 { + compatible = "ingenic,jz4780-sgx540-120", "img,sgx540-120", "img,sgx540", "img,sgx5"; + reg = <0x13040000 0x4000>; + + clocks = <&cgu JZ4780_CLK_GPU>; + clock-names = "gpu"; + + interrupt-parent = <&intc>; + interrupts = <63>; + }; + tcu: timer@10002000 { compatible = "ingenic,jz4780-tcu", "ingenic,jz4770-tcu",
Signature · 1 line
2.23.0
Paul Cercueil
maintainerRe: [PATCH v3 8/8] MIPS: DTS: jz4780: add sgx gpu node
Hi Nikolaus,
Quoted 15 lines · H. Nikolaus Schaller
and add interrupt and clocks.
Tested to build for CI20 board and load a (non-working) driver.
Suggested-by Paul Boddie <[email protected]>Signed-off-by H. Nikolaus Schaller <[email protected]>--- arch/mips/boot/dts/ingenic/jz4780.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+)arch/mips/boot/dts/ingenic/jz4780.dtsi +0
-0
arch/mips/boot/dts/ingenic/jz4780.dtsi line 49
Quoted 4 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +1
-0@@ -46,6 +46,17 @@ #clock-cells = <1>; }; + gpu: gpu@13040000 {
We try to keep the nodes ordered by address, could you move this node where it belongs?
Thanks,
-Paul
Quoted 17 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +10
-0+ compatible = "ingenic,jz4780-sgx540-120", "img,sgx540-120", "img,sgx540", "img,sgx5"; + reg = <0x13040000 0x4000>; + + clocks = <&cgu JZ4780_CLK_GPU>; + clock-names = "gpu"; + + interrupt-parent = <&intc>; + interrupts = <63>; + }; + tcu: timer@10002000 { compatible = "ingenic,jz4780-tcu","ingenic,jz4770-tcu",
--
2.23.0
Re: [PATCH v3 8/8] MIPS: DTS: jz4780: add sgx gpu node
Quoted 3 lines · Paul Cercueil
Le dim., nov. 24, 2019 at 12:40, H. Nikolaus Schaller <[email protected]> a écrit :
Quoted 1 line
and add interrupt and clocks.
...
Quoted 10 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi line 49
Quoted 7 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +1
-0@@ -46,6 +46,17 @@ #clock-cells = <1>; }; + gpu: gpu@13040000 {We try to keep the nodes ordered by address, could you move this node where it belongs?
...
Quoted 6 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi line 54
Quoted 6 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +1
-0+ compatible = "ingenic,jz4780-sgx540-120", "img,sgx540-120","img,sgx540", "img,sgx5";
arch/mips/boot/dts/ingenic/jz4780.dtsi +4
-0+ reg = <0x13040000 0x4000>; + + clocks = <&cgu JZ4780_CLK_GPU>; + clock-names = "gpu";
Just checking.. Is there something else to configure here potentially in addition to the clocks?
That is, do we need to do some interconnect specific configuration etc in addition to the clocks to have runtime PM work for enabling and disabling sgx on jz4780?
Regards,
Tony
Re: [PATCH v3 8/8] MIPS: DTS: jz4780: add sgx gpu node
Hi Paul, Tony,
Quoted 13 lines
Am 24.11.2019 um 18:48 schrieb Tony Lindgren <[email protected]>:
Quoted 3 lines · Paul Cercueil
Le dim., nov. 24, 2019 at 12:40, H. Nikolaus Schaller <[email protected]> a écrit :
Quoted 1 line
and add interrupt and clocks.
...
Quoted 6 lines
Quoted 6 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +0
-0@@ -46,6 +46,17 @@ #clock-cells = <1>; };
Quoted 5 lines
Quoted 4 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi line 49
Quoted 1 line
arch/mips/boot/dts/ingenic/jz4780.dtsi +1
-0+ gpu: gpu@13040000 {We try to keep the nodes ordered by address, could you move this node where it belongs?
...
Yes, I have noted.
Quoted 10 lines
Quoted 7 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi line 54
Quoted 7 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +1
-0+ compatible = "ingenic,jz4780-sgx540-120", "img,sgx540-120","img,sgx540", "img,sgx5";
arch/mips/boot/dts/ingenic/jz4780.dtsi +4
-0+ reg = <0x13040000 0x4000>; + + clocks = <&cgu JZ4780_CLK_GPU>; + clock-names = "gpu";Just checking.. Is there something else to configure here potentially in addition to the clocks?
It doesn't look so. Unfortuantely there isn't much information except a v3.18 kernel supported by the vendor and that one also just has a gpu node with clock control.
Quoted 4 lines
That is, do we need to do some interconnect specific configuration etc in addition to the clocks to have runtime PM work for enabling and disabling sgx on jz4780?
I think we have to leave that open for further study.
BR,
Nikolaus
Re: [PATCH v3 8/8] MIPS: DTS: jz4780: add sgx gpu node
Quoted 38 lines · H. Nikolaus Schaller
Hi Paul, Tony,
Quoted 13 lines
Am 24.11.2019 um 18:48 schrieb Tony Lindgren <[email protected]>:
Quoted 3 lines · Paul Cercueil
Le dim., nov. 24, 2019 at 12:40, H. Nikolaus Schaller <[email protected]> a écrit :
Quoted 1 line
and add interrupt and clocks.
...
Quoted 6 lines
Quoted 6 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +0
-0@@ -46,6 +46,17 @@ #clock-cells = <1>; };Quoted 5 lines
Quoted 4 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi line 49
Quoted 1 line
arch/mips/boot/dts/ingenic/jz4780.dtsi +1
-0+ gpu: gpu@13040000 {We try to keep the nodes ordered by address, could you move this node where it belongs?
...
Yes, I have noted.
Quoted 10 lines
Quoted 7 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi line 54
Quoted 7 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +1
-0+ compatible = "ingenic,jz4780-sgx540-120", "img,sgx540-120","img,sgx540", "img,sgx5";
arch/mips/boot/dts/ingenic/jz4780.dtsi +4
-0+ reg = <0x13040000 0x4000>; + + clocks = <&cgu JZ4780_CLK_GPU>; + clock-names = "gpu";Just checking.. Is there something else to configure here potentially in addition to the clocks?
It doesn't look so. Unfortuantely there isn't much information except a v3.18 kernel supported by the vendor and that one also just has a gpu node with clock control.
Quoted 6 lines
Quoted 4 lines
That is, do we need to do some interconnect specific configuration etc in addition to the clocks to have runtime PM work for enabling and disabling sgx on jz4780?
I think we have to leave that open for further study.
OK for now, let's assume we just need to call clk_enable/disable from the PM runtime functions if a clock exists.
Regards,
Tony