clk: qcom: Support for Low Power Audio Clocks on SC7180
v4 cover clk: qcom: Support for Low Power Audio Clocks on SC7180
[v4]
* Fix minor comments in the documentation binding.
[v3]
* Update the clock-name to iface instead of gcc_lpass_sway.
* Update the documentation with the reg descriptions and use maxItems.
[v2]
* Update retention macro name.
* Update the register description in the documentation.
[v1]
* Add support for Retention of GDSCR.
* Add YAML schema for LPASS clocks and clock IDs for LPASS.
* Add clock driver for LPASS core clocks and GCC LPASS clock.
Taniya Das (4):
clk: qcom: gdsc: Add support to enable retention of GSDCR
dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180
clk: qcom: gcc: Add support for GCC LPASS clock for SC7180
clk: qcom: lpass: Add support for LPASS clock controller for SC7180
.../bindings/clock/qcom,sc7180-lpasscorecc.yaml | 103 +++++ drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-sc7180.c | 14 + drivers/clk/qcom/gdsc.c | 12 + drivers/clk/qcom/gdsc.h | 1 + drivers/clk/qcom/lpasscorecc-sc7180.c | 478 +++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sc7180.h | 1 + .../dt-bindings/clock/qcom,lpasscorecc-sc7180.h | 29 ++ 9 files changed, 648 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml create mode 100644 drivers/clk/qcom/lpasscorecc-sc7180.c create mode 100644 include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
PATCH v4 1/4 clk: qcom: gdsc: Add support to enable retention of GSDCR
Add support for the RETAIN_FF_ENABLE feature which enables the usage of retention registers. These registers maintain their state after disabling and re-enabling a GDSC.
--- drivers/clk/qcom/gdsc.c | 12 ++++++++++++ drivers/clk/qcom/gdsc.h | 1 + 2 files changed, 13 insertions(+)
drivers/clk/qcom/gdsc.c +12 -0
@@ -29,6 +29,7 @@/* CFG_GDSCR */ #define GDSC_POWER_UP_COMPLETE BIT(16)#define GDSC_POWER_DOWN_COMPLETE BIT(15) +#define GDSC_RETAIN_FF_ENABLE BIT(11)#define CFG_GDSCR_OFFSET 0x4/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
@@ -216,6 +217,14 @@ static inline void gdsc_assert_reset_aon(struct gdsc *sc)regmap_update_bits (sc->regmap, sc->clamp_io_ctrl,GMEM_RESET_MASK ,0 ); } + +static void gdsc_retain_ff_on (struct gdsc *sc) +{ +u32 mask =GDSC_RETAIN_FF_ENABLE ; + +regmap_update_bits (sc->regmap, sc->gdscr, mask, mask); +} +static int gdsc_enable (struct generic_pm_domain *domain) {struct gdsc *sc =domain_to_gdsc (domain);
@@ -268,6 +277,9 @@ static int gdsc_enable(struct generic_pm_domain *domain)udelay (1 ); } +if (sc->flags &RETAIN_FF_ENABLE ) +gdsc_retain_ff_on (sc); +return 0 ; }
drivers/clk/qcom/gdsc.h +1 -0
@@ -50,6 +50,7 @@ struct gdsc {#define AON_RESET BIT(4)#define POLL_CFG_GDSCR BIT(5)#define ALWAYS_ON BIT(6) +#define RETAIN_FF_ENABLE BIT(7)struct reset_controller_dev *rcdev;unsigned int *resets;unsigned int reset_count;
Signature · 2 lines
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
PATCH v4 2/4 dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180
In reply to Taniya DasThe LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic properties that are needed in a device tree. Also add clock ids for GCC LPASS and LPASS Core clock IDs for LPASS client to request for the clocks.
--- .../bindings/clock/qcom,sc7180-lpasscorecc.yaml | 103 +++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sc7180.h | 1 + .../dt-bindings/clock/qcom,lpasscorecc-sc7180.h | 29 ++++++ 3 files changed, 133 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml create mode 100644 include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml new file +103 -0
@@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core Clock Controller Binding for SC7180 + +maintainers: + - Taniya Das <[email protected]> + +description: | + Qualcomm LPASS core clock control module which supports the clocks and + power domains on SC7180. + + See also: + - dt-bindings/clock/qcom,lpasscorecc-sc7180.h + +properties: + compatible: + enum: + - qcom,sc7180-lpasshm + - qcom,sc7180-lpasscorecc + + clocks: + items: + - description: gcc_lpass_sway clock from GCC + + clock-names: + items: + - const: iface + + power-domains: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + minItems: 1 + items: + - description: lpass core cc register + - description: lpass audio cc register + + reg-names: + items: + - const: lpass_core_cc + - const: lpass_audio_cc + +if: + properties: + compatible: + contains: + const: qcom,sc7180-lpasshm +then: + properties: + reg: + maxItems: 1 + +else: + properties: + reg: + minItems: 2 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> + clock-controller@63000000 { + compatible = "qcom,sc7180-lpasshm"; + reg = <0x63000000 0x28>; + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>; + clock-names = "iface"; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + - | + clock-controller@62d00000 { + compatible = "qcom,sc7180-lpasscorecc"; + reg = <0x62d00000 0x50000>, + <0x62780000 0x30000>; + reg-names = "lpass_core_cc", "lpass_audio_cc"; + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>; + clock-names = "iface"; + power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; +...
include/dt-bindings/clock/qcom,gcc-sc7180.h +1 -0
@@ -138,6 +138,7 @@#define GCC_MSS_Q6_MEMNOC_AXI_CLK 128#define GCC_MSS_SNOC_AXI_CLK 129#define GCC_SEC_CTRL_CLK_SRC 130 +#define GCC_LPASS_CFG_NOC_SWAY_CLK 131/* GCC resets */ #define GCC_QUSB2PHY_PRIM_BCR 0
include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h new file +29 -0
@@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +* Copyright (c) 2020, The Linux Foundation. All rights reserved. +*/ + +#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H +#define _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H + +/* LPASS_CORE_CC clocks */ +#define LPASS_LPAAUDIO_DIG_PLL 0 +#define LPASS_LPAAUDIO_DIG_PLL_OUT_ODD 1 +#define CORE_CLK_SRC 2 +#define EXT_MCLK0_CLK_SRC 3 +#define LPAIF_PRI_CLK_SRC 4 +#define LPAIF_SEC_CLK_SRC 5 +#define LPASS_AUDIO_CORE_CORE_CLK 6 +#define LPASS_AUDIO_CORE_EXT_MCLK0_CLK 7 +#define LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK 8 +#define LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK 9 +#define LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK 10 + +/* LPASS Core power domains */ +#define LPASS_CORE_HM_GDSCR 0 + +/* LPASS Audio power domains */ +#define LPASS_AUDIO_HM_GDSCR 0 +#define LPASS_PDC_HM_GDSCR 1 + +#endif
Signature · 2 lines
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
Re: [PATCH v4 2/4] dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180
Quoted 4 lines · Taniya Das
The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic properties that are needed in a device tree. Also add clock ids for GCC LPASS and LPASS Core clock IDs for LPASS client to request for the clocks.
Quoted 9 lines
Signed-off-by Taniya Das <[email protected]>--- .../bindings/clock/qcom,sc7180-lpasscorecc.yaml | 103 +++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sc7180.h | 1 + .../dt-bindings/clock/qcom,lpasscorecc-sc7180.h | 29 ++++++ 3 files changed, 133 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml create mode 100644 include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h
Stephen Boyd
maintainerRe: [PATCH v4 2/4] dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180
In reply to Taniya DasQuoting Taniya Das (2020-07-14 23:36:48)
Quoted 23 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml new file +17
-0@@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core Clock Controller Binding for SC7180 + +maintainers: + - Taniya Das <[email protected]> + +description: | + Qualcomm LPASS core clock control module which supports the clocks and + power domains on SC7180. + + See also: + - dt-bindings/clock/qcom,lpasscorecc-sc7180.h
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml line 27
Quoted 10 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml new file +10
-0+ +properties: + compatible: + enum: + - qcom,sc7180-lpasshm + - qcom,sc7180-lpasscorecc + + clocks: + items: + - description: gcc_lpass_sway clock from GCC
Needs bi_tcxo description.
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml line 31
Quoted 4 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml new file +4
-0+ + clock-names: + items: + - const: iface
Needs bi_tcxo
Quoted 54 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml new file +54
-0+ + power-domains: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + minItems: 1 + items: + - description: lpass core cc register + - description: lpass audio cc register + + reg-names: + items: + - const: lpass_core_cc + - const: lpass_audio_cc + +if: + properties: + compatible: + contains: + const: qcom,sc7180-lpasshm +then: + properties: + reg: + maxItems: 1 + +else: + properties: + reg: + minItems: 2 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> + clock-controller@63000000 { + compatible = "qcom,sc7180-lpasshm"; + reg = <0x63000000 0x28>; + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>;
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml line 95
Quoted 10 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml new file +10
-0+ clock-names = "iface"; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + - | + clock-controller@62d00000 { + compatible = "qcom,sc7180-lpasscorecc"; + reg = <0x62d00000 0x50000>, + <0x62780000 0x30000>;
Tabbing looks wrong. Just use spaces?
Quoted 13 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml new file +8
-0+ reg-names = "lpass_core_cc", "lpass_audio_cc"; + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>; + clock-names = "iface"; + power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; +...include/dt-bindings/clock/qcom,gcc-sc7180.h +0
-0
include/dt-bindings/clock/qcom,gcc-sc7180.h line 144
Quoted 7 lines
include/dt-bindings/clock/qcom,gcc-sc7180.h +1
-0@@ -138,6 +138,7 @@#define GCC_MSS_Q6_MEMNOC_AXI_CLK 128#define GCC_MSS_SNOC_AXI_CLK 129#define GCC_SEC_CTRL_CLK_SRC 130 +#define GCC_LPASS_CFG_NOC_SWAY_CLK 131/* GCC resets */ #define GCC_QUSB2PHY_PRIM_BCR 0
This hunk should be in the next patch. Oh but then that patch should come before this one so the binding can use it. Either way, shouldn't be part of this patch.
Re: [PATCH v4 2/4] dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180
Hi Stephen,
Thanks for the review.
Quoted 11 lines · Stephen Boyd
Quoted 11 lines
+...
include/dt-bindings/clock/qcom,gcc-sc7180.h +1
-0@@ -138,6 +138,7 @@#define GCC_MSS_Q6_MEMNOC_AXI_CLK 128#define GCC_MSS_SNOC_AXI_CLK 129#define GCC_SEC_CTRL_CLK_SRC 130 +#define GCC_LPASS_CFG_NOC_SWAY_CLK 131
Quoted 7 lines
include/dt-bindings/clock/qcom,gcc-sc7180.h line 144
Quoted 2 lines
include/dt-bindings/clock/qcom,gcc-sc7180.h +0
-0/* GCC resets */ #define GCC_QUSB2PHY_PRIM_BCR 0This hunk should be in the next patch. Oh but then that patch should come before this one so the binding can use it. Either way, shouldn't be part of this patch.
We had a problem with the bot complaining about the clock handles being used in the example.
https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]/
Thus I have kept the GCC bindings in the same patch.
Signature · 4 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation. --
Stephen Boyd
maintainerRe: [PATCH v4 2/4] dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180
Quoting Taniya Das (2020-07-21 10:26:53)
Quoted 26 lines
Hi Stephen,
Thanks for the review.
Quoted 11 lines · Stephen Boyd
Quoted 11 lines
+...
include/dt-bindings/clock/qcom,gcc-sc7180.h +1
-0@@ -138,6 +138,7 @@#define GCC_MSS_Q6_MEMNOC_AXI_CLK 128#define GCC_MSS_SNOC_AXI_CLK 129#define GCC_SEC_CTRL_CLK_SRC 130 +#define GCC_LPASS_CFG_NOC_SWAY_CLK 131Quoted 7 lines
include/dt-bindings/clock/qcom,gcc-sc7180.h line 144
Quoted 2 lines
include/dt-bindings/clock/qcom,gcc-sc7180.h +0
-0/* GCC resets */ #define GCC_QUSB2PHY_PRIM_BCR 0This hunk should be in the next patch. Oh but then that patch should come before this one so the binding can use it. Either way, shouldn't be part of this patch.
Quoted 7 lines
We had a problem with the bot complaining about the clock handles being used in the example.
https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]/
Thus I have kept the GCC bindings in the same patch.
Ah ok. Well I'll fix it when you resend to fix the comment on patch 4.
PATCH v4 3/4 clk: qcom: gcc: Add support for GCC LPASS clock for SC7180
In reply to Taniya DasAdd the GCC lpass clock which is required to access the LPASS core clocks.
--- drivers/clk/qcom/gcc-sc7180.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
drivers/clk/qcom/gcc-sc7180.c +14 -0
@@ -2251,6 +2251,19 @@ static struct clk_branch gcc_mss_q6_memnoc_axi_clk = { }, }; +static struct clk_branch gcc_lpass_cfg_noc_sway_clk = { + .halt_reg =0x47018 , + .halt_check =BRANCH_HALT_DELAY , + .clkr = { + .enable_reg =0x47018 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_lpass_cfg_noc_sway_clk" , + .ops = &clk_branch2_ops, + }, + }, +}; +static struct gdsc ufs_phy_gdsc = { .gdscr =0x77004 , .pd = {
@@ -2428,6 +2441,7 @@ static struct clk_regmap *gcc_sc7180_clocks[] = { [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr, [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, [GCC_SEC_CTRL_CLK_SRC] = &gcc_sec_ctrl_clk_src.clkr, + [GCC_LPASS_CFG_NOC_SWAY_CLK] = &gcc_lpass_cfg_noc_sway_clk.clkr, };static const struct qcom_reset_map gcc_sc7180_resets[] = {
Signature · 2 lines
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
PATCH v4 4/4 clk: qcom: lpass: Add support for LPASS clock controller for SC7180
In reply to Taniya DasThe Low Power Audio subsystem clocks are required for Audio client to be able to request for the clocks and power domains.
--- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/lpasscorecc-sc7180.c | 478 ++++++++++++++++++++++++++++++++++ 3 files changed, 488 insertions(+) create mode 100644 drivers/clk/qcom/lpasscorecc-sc7180.c
drivers/clk/qcom/Kconfig +9 -0
@@ -308,6 +308,15 @@ config SC_GCC_7180 Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, UFS, SDCC, etc. +config SC_LPASS_CORECC_7180 + tristate "SC7180 LPASS Core Clock Controller" + select SC_GCC_7180 + help + Support for the LPASS(Low Power Audio Subsystem) core clock controller + on SC7180 devices. + Say Y if you want to use LPASS clocks and power domains of the LPASS + core clock controller. + config SC_GPUCC_7180 tristate "SC7180 Graphics Clock Controller" select SC_GCC_7180
drivers/clk/qcom/Makefile +1 -0
@@ -54,6 +54,7 @@ obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o obj-$(CONFIG_SC_DISPCC_7180) += dispcc-sc7180.o obj-$(CONFIG_SC_GCC_7180) += gcc-sc7180.o obj-$(CONFIG_SC_GPUCC_7180) += gpucc-sc7180.o +obj-$(CONFIG_SC_LPASS_CORECC_7180) += lpasscorecc-sc7180.o obj-$(CONFIG_SC_MSS_7180) += mss-sc7180.o obj-$(CONFIG_SC_VIDEOCC_7180) += videocc-sc7180.o obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o
drivers/clk/qcom/lpasscorecc-sc7180.c new file +478 -0
478 lines not on this page · raw message
Signature · 2 lines
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
Stephen Boyd
maintainerRe: [PATCH v4 4/4] clk: qcom: lpass: Add support for LPASS clock controller for SC7180
Quoting Taniya Das (2020-07-14 23:36:50)
Quoted 69 lines
drivers/clk/qcom/lpasscorecc-sc7180.c new file +63
-0@@ -0,0 +1,478 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* +* Copyright (c) 2020, The Linux Foundation. All rights reserved. +*/ + +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> +#include <linux/of.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "gdsc.h" + +enum { +P_BI_TCXO , +P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD , +P_SLEEP_CLK , +}; + +static struct pll_vco fabia_vco[] = { + {249600000 ,2000000000 ,0 }, +}; + +static const struct alpha_pll_config lpass_lpaaudio_dig_pll_config = { + .l =0x20 , + .alpha =0x0 , + .config_ctl_val =0x20485699 , + .config_ctl_hi_val =0x00002067 , + .test_ctl_val =0x40000000 , + .test_ctl_hi_val =0x00000000 , + .user_ctl_val =0x00005105 , + .user_ctl_hi_val =0x00004805 , +}; + +static const u8 clk_alpha_pll_regs_offset[][PLL_OFF_MAX_REGS ] = { + [CLK_ALPHA_PLL_TYPE_FABIA ] = { + [PLL_OFF_L_VAL ] =0x04 , + [PLL_OFF_CAL_L_VAL ] =0x8 , + [PLL_OFF_USER_CTL ] =0x0c , + [PLL_OFF_USER_CTL_U ] =0x10 , + [PLL_OFF_USER_CTL_U1 ] =0x14 , + [PLL_OFF_CONFIG_CTL ] =0x18 , + [PLL_OFF_CONFIG_CTL_U ] =0x1C , + [PLL_OFF_CONFIG_CTL_U1 ] =0x20 , + [PLL_OFF_TEST_CTL ] =0x24 , + [PLL_OFF_TEST_CTL_U ] =0x28 , + [PLL_OFF_STATUS ] =0x30 , + [PLL_OFF_OPMODE ] =0x38 , + [PLL_OFF_FRAC ] =0x40 , + }, +}; + +static struct clk_alpha_pll lpass_lpaaudio_dig_pll = {
drivers/clk/qcom/lpasscorecc-sc7180.c line 73
Quoted 10 lines
drivers/clk/qcom/lpasscorecc-sc7180.c new file +10
-0+ .offset = 0x1000, + .vco_table = fabia_vco, + .num_vco = ARRAY_SIZE(fabia_vco), + .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_FABIA], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "lpass_lpaaudio_dig_pll", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + .name = "bi_tcxo",
We don't need .name if we have .fw_name and this is a new binding/device.
Quoted 7 lines
drivers/clk/qcom/lpasscorecc-sc7180.c new file +7
-0+ }, + .num_parents = 1, + .ops = &clk_alpha_pll_fabia_ops, + }, + }, +}; +
Re: [PATCH v4 4/4] clk: qcom: lpass: Add support for LPASS clock controller for SC7180
Hi Stephen,
Thanks for the review.
Quoted 15 lines · Stephen Boyd
Quoting Taniya Das (2020-07-14 23:36:50)
drivers/clk/qcom/lpasscorecc-sc7180.c line 73
Quoted 13 lines
drivers/clk/qcom/lpasscorecc-sc7180.c +11
-0+static struct clk_alpha_pll lpass_lpaaudio_dig_pll = { + .offset =0x1000 , + .vco_table = fabia_vco, + .num_vco =ARRAY_SIZE (fabia_vco), + .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_FABIA ], + .clkr = { + .hw.init = &(struct clk_init_data ){ + .name ="lpass_lpaaudio_dig_pll" , + .parent_data = &(const struct clk_parent_data ){ + .fw_name ="bi_tcxo" , + .name ="bi_tcxo" ,
Quoted 2 lines
We don't need .name if we have .fw_name and this is a new binding/device.
My bad, will cleanup in the next patch.
Quoted 7 lines
Quoted 7 lines
drivers/clk/qcom/lpasscorecc-sc7180.c +7
-0+ }, + .num_parents = 1, + .ops = &clk_alpha_pll_fabia_ops, + }, + }, +}; +
Signature · 4 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation. --