Expose new features for Intel processor
v3 cover Expose new features for Intel processor
This patchset is to expose two new features, SERIALIZE and TSX suspend load tracking to KVM CPUID for processors which support them. KVM reports this information and guest can make use of them finally.
Detailed information on the instructions and CPUID feature flags can be found in the latest "extensions" manual [1].
This series applies on top of TIP tree as it depends on
Changes since v2:
* Combine the two kvm patches into a single one.
* Provide features' overview introduction in kvm patch commit message.
* Get the latest kernel patches.
* Change definition from TSX_LDTRK to TSXLDTRK for TSX new feature.
* Change kernel patches Author to the owner.
* Remove SERIALIZE enumeration patch.
Reference:
[1]. https://software.intel.com/content/dam/develop/public/us/en/documents/architecture-instruction-set-extensions-programming-reference.pdf
Cathy Zhang (1):
x86/kvm: Expose new features for supported cpuid
Kyung Min Park (1):
x86/cpufeatures: Enumerate TSX suspend load address tracking
instructions
arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kvm/cpuid.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-)
Signature · 1 line
1.8.3.1
PATCH v3 1/2 x86/cpufeatures: Enumerate TSX suspend load address tracking instructions
From: Kyung Min Park <[email protected]>
Intel TSX suspend load tracking instructions aim to give a way to choose which memory accesses do not need to be tracked in the TSX read set. Add TSX suspend load tracking CPUID feature flag TSXLDTRK for enumeration.
A processor supports Intel TSX suspend load address tracking if CPUID.0x07.0x0:EDX[16] is present. Two instructions XSUSLDTRK, XRESLDTRK are available when this feature is present.
The CPU feature flag is shown as "tsxldtrk" in /proc/cpuinfo.
This instruction is currently documented in the the latest "extensions" manual (ISE). It will appear in the "main" manual (SDM) in the future.
---
Changes since v2:
* Shorten documentation names for readability. Links to documentation can be found in the cover letter. (Dave Hansen)
--- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+)
arch/x86/include/asm/cpufeatures.h +1 -0
@@ -368,6 +368,7 @@#define X86_FEATURE_MD_CLEAR (18*32+10)/* VERW clears CPU buffers */ #define X86_FEATURE_TSX_FORCE_ABORT (18*32+13)/* "" TSX_FORCE_ABORT */ #define X86_FEATURE_SERIALIZE (18*32+14)/* SERIALIZE instruction */ +#define X86_FEATURE_TSXLDTRK (18*32+16)/* TSX Suspend Load Address Tracking */ #define X86_FEATURE_PCONFIG (18*32+18)/* Intel PCONFIG */ #define X86_FEATURE_ARCH_LBR (18*32+19)/* Intel ARCH LBR */ #define X86_FEATURE_SPEC_CTRL (18*32+26)/* "" Speculation Control (IBRS + IBPB) */
Signature · 1 line
1.8.3.1
PATCH v3 2/2 x86/kvm: Expose new features for supported cpuid
In reply to Cathy ZhangExpose the SERIALIZE and TSX Suspend Load Address Tracking features in KVM CPUID, so when running on processors which support them, KVM could pass this information to guests and they can make use of these features accordingly.
SERIALIZE is a faster serializing instruction which does not modify registers, arithmetic flags or memory, will not cause VM exit. It's availability is indicated by CPUID.(EAX=7,ECX=0):ECX[bit 14].
TSX suspend load tracking instruction aims to give a way to choose which memory accesses do not need to be tracked in the TSX read set. It's availability is indicated as CPUID.(EAX=7,ECX=0):EDX[bit 16].
Those instructions are currently documented in the the latest "extensions" manual (ISE). It will appear in the "main" manual (SDM) in the future.
---
Changes since v2:
* Merge two patches into a single one. (Luck, Tony)
* Add overview introduction for features. (Sean Christopherson)
* Refactor commit message to explain why expose feature bits. (Luck, Tony)
--- arch/x86/kvm/cpuid.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
arch/x86/kvm/cpuid.c +2 -1
@@ -341,7 +341,8 @@ void kvm_set_cpu_caps(void)kvm_cpu_cap_mask (CPUID_7_EDX ,F (AVX512_4VNNIW ) |F (AVX512_4FMAPS ) |F (SPEC_CTRL ) |F (SPEC_CTRL_SSBD ) |F (ARCH_CAPABILITIES ) |F (INTEL_STIBP ) | -F (MD_CLEAR ) |F (AVX512_VP2INTERSECT ) |F (FSRM ) +F (MD_CLEAR ) |F (AVX512_VP2INTERSECT ) |F (FSRM ) | +F (SERIALIZE ) |F (TSXLDTRK ) );/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
Signature · 1 line
1.8.3.1
Paolo Bonzini
maintainerRe: [PATCH v3 2/2] x86/kvm: Expose new features for supported cpuid
Quoted 33 lines · Cathy Zhang
Expose the SERIALIZE and TSX Suspend Load Address Tracking features in KVM CPUID, so when running on processors which support them, KVM could pass this information to guests and they can make use of these features accordingly.
SERIALIZE is a faster serializing instruction which does not modify registers, arithmetic flags or memory, will not cause VM exit. It's availability is indicated by CPUID.(EAX=7,ECX=0):ECX[bit 14].
TSX suspend load tracking instruction aims to give a way to choose which memory accesses do not need to be tracked in the TSX read set. It's availability is indicated as CPUID.(EAX=7,ECX=0):EDX[bit 16].
Those instructions are currently documented in the the latest "extensions" manual (ISE). It will appear in the "main" manual (SDM) in the future.
Signed-off-by Cathy Zhang <[email protected]>Reviewed-by Tony Luck <[email protected]>---
Changes since v2:
* Merge two patches into a single one. (Luck, Tony)
* Add overview introduction for features. (Sean Christopherson)
* Refactor commit message to explain why expose feature bits. (Luck, Tony)--- arch/x86/kvm/cpuid.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)arch/x86/kvm/cpuid.c +0
-0
arch/x86/kvm/cpuid.c void kvm_set_cpu_caps(void) · line 348
Quoted 9 lines
arch/x86/kvm/cpuid.c +2
-1@@ -341,7 +341,8 @@ void kvm_set_cpu_caps(void)kvm_cpu_cap_mask (CPUID_7_EDX ,F (AVX512_4VNNIW ) |F (AVX512_4FMAPS ) |F (SPEC_CTRL ) |F (SPEC_CTRL_SSBD ) |F (ARCH_CAPABILITIES ) |F (INTEL_STIBP ) | -F (MD_CLEAR ) |F (AVX512_VP2INTERSECT ) |F (FSRM ) +F (MD_CLEAR ) |F (AVX512_VP2INTERSECT ) |F (FSRM ) | +F (SERIALIZE ) |F (TSXLDTRK ) );/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
TSXLDTRK is not going to be in 5.9 as far as I can see, so I split back again the patches (this is why I prefer them to be split, sorry Tony :)) and committed the SERIALIZE part.
Paolo
Re: [PATCH v3 2/2] x86/kvm: Expose new features for supported cpuid
Quoted 41 lines · Paolo Bonzini
Quoted 40 lines · Cathy Zhang
Expose the SERIALIZE and TSX Suspend Load Address Tracking features in KVM CPUID, so when running on processors which support them, KVM could pass this information to guests and they can make use of these features accordingly.
SERIALIZE is a faster serializing instruction which does not modify registers, arithmetic flags or memory, will not cause VM exit. It's availability is indicated by CPUID.(EAX=7,ECX=0):ECX[bit 14].
TSX suspend load tracking instruction aims to give a way to choose which memory accesses do not need to be tracked in the TSX read set. It's availability is indicated as CPUID.(EAX=7,ECX=0):EDX[bit 16].
Those instructions are currently documented in the the latest "extensions" manual (ISE). It will appear in the "main" manual (SDM) in the future.
Signed-off-by Cathy Zhang <[email protected]>Reviewed-by Tony Luck <[email protected]>---
Changes since v2:
* Merge two patches into a single one. (Luck, Tony)
* Add overview introduction for features. (Sean Christopherson)
* Refactor commit message to explain why expose feature bits. (Luck, Tony)--- arch/x86/kvm/cpuid.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)arch/x86/kvm/cpuid.c +2
-1@@ -341,7 +341,8 @@ void kvm_set_cpu_caps(void)kvm_cpu_cap_mask (CPUID_7_EDX ,F (AVX512_4VNNIW ) |F (AVX512_4FMAPS ) |F (SPEC_CTRL ) |F (SPEC_CTRL_SSBD ) |F (ARCH_CAPABILITIES ) |F (INTEL_STIBP ) | -F (MD_CLEAR ) |F (AVX512_VP2INTERSECT ) |F (FSRM ) +F (MD_CLEAR ) |F (AVX512_VP2INTERSECT ) |F (FSRM ) | +F (SERIALIZE ) |F (TSXLDTRK ) );
Quoted 7 lines
arch/x86/kvm/cpuid.c void kvm_set_cpu_caps(void) · line 348
Quoted 2 lines
arch/x86/kvm/cpuid.c +0
-0/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ TSXLDTRK is not going to be in 5.9 as far as I can see, so I split back again the patches (this is why I prefer them to be split, sorry Tony :)) and committed the SERIALIZE part.
Paolo
Hello Paolo,
As you suggest, I will split the kvm patch into two parts, SERIALIZE and TSXLDTRK, and this series will include three patches then, 2 kvm patches and 1 kernel patch. SERIALIZE could get merged into 5.9, but TSXLDTRK should wait for the next release. I just want to double confirm with you, please help correct me if I'm wrong.
RE: [PATCH v3 2/2] x86/kvm: Expose new features for supported cpuid
Quoted 5 lines
As you suggest, I will split the kvm patch into two parts, SERIALIZE and TSXLDTRK, and this series will include three patches then, 2 kvm patches and 1 kernel patch. SERIALIZE could get merged into 5.9, but TSXLDTRK should wait for the next release. I just want to double confirm with you, please help correct me if I'm wrong.
Paolo is saying that he has applied the SERIALIZE part to his KVM tree.
Next step for you is a two part series.
Part 1: Add TSXLDTRK to cpufeatures.h
Part 2: Add TSXLDTRK to arch/x86/kvm/cpuid.c (on top of the version that Paolo committed with SERIALIZE)
Paolo: The 5.9 merge window is still open this week. Will you send the KVM serialize patch to Linus before this merge window closes? Or do you have it queued for v5.10?
-Tony
Re: [PATCH v3 2/2] x86/kvm: Expose new features for supported cpuid
Quoted 11 lines · Tony
Quoted 5 lines
As you suggest, I will split the kvm patch into two parts, SERIALIZE and TSXLDTRK, and this series will include three patches then, 2 kvm patches and 1 kernel patch. SERIALIZE could get merged into 5.9, but TSXLDTRK should wait for the next release. I just want to double confirm with you, please help correct me if I'm wrong.
Paolo is saying that he has applied the SERIALIZE part to his KVM tree.
Next step for you is a two part series.
Quoted 7 lines
Part 1: Add TSXLDTRK to
cpufeatures.h
Part 2: Add TSXLDTRK toarch/x86/kvm/cpuid.c(on top of the version that Paolo committed with SERIALIZE)Paolo: The 5.9 merge window is still open this week. Will you send the KVM serialize patch to Linus before this merge window closes? Or do you have it queued for v5.10?
-Tony
Got it! Thanks for the explanation, Tony!
Paolo Bonzini
maintainerRe: [PATCH v3 2/2] x86/kvm: Expose new features for supported cpuid
In reply to Luck, TonyQuoted 8 lines · Tony
Part 1: Add TSXLDTRK to
cpufeatures.hPart 2: Add TSXLDTRK toarch/x86/kvm/cpuid.c(on top of the version that Paolo committed with SERIALIZE)Paolo: The 5.9 merge window is still open this week. Will you send the KVM serialize patch to Linus before this merge window closes? Or do you have it queued for v5.10?
Yes, I am sending it today together with the bulk of ARM and PPC changes. I just wanted to soak the branch in linux-next for a day or two, just in case I screwed up the ARM and PPC pull requests.
Paolo