Expose new feature for Intel processor

This patchset is to introduce TSX suspend load tracking feature and expose it to KVM CPUID for processors which support it. KVM reports this information and guests can make use of it finally.

Detailed information on the instruction and CPUID feature flag can be found in the latest "extensions" manual [1].

Changes since v3:
* Remove SERIALIZE part from kvm patch and update commit message

Changes since v2:
* Combine the two kvm patches into a single one.
* Provide features' overview introduction in kvm patch commit message.
* Get the latest kernel patches.
* Change definition from TSX_LDTRK to TSXLDTRK for TSX new feature.
* Change kernel patches Author to the owner.
* Remove SERIALIZE enumeration patch.

Reference:
[1]. https://software.intel.com/content/dam/develop/public/us/en/documents/architecture-instruction-set-extensions-programming-reference.pdf

Cathy Zhang (1):
x86/kvm: Expose TSX Suspend Load Tracking feature

Kyung Min Park (1):
x86/cpufeatures: Enumerate TSX suspend load address tracking
instructions

 arch/x86/include/asm/cpufeatures.h | 1 +
 arch/x86/kvm/cpuid.c               | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

1.8.3.1

From: Kyung Min Park <[email protected]>

Intel TSX suspend load tracking instructions aim to give a way to choose which memory accesses do not need to be tracked in the TSX read set. Add TSX suspend load tracking CPUID feature flag TSXLDTRK for enumeration.

A processor supports Intel TSX suspend load address tracking if CPUID.0x07.0x0:EDX[16] is present. Two instructions XSUSLDTRK, XRESLDTRK are available when this feature is present.

The CPU feature flag is shown as "tsxldtrk" in /proc/cpuinfo.

This instruction is currently documented in the the latest "extensions" manual (ISE). It will appear in the "main" manual (SDM) in the future.

---
Changes since v3:
* N/A

Changes since v2:
* Shorten documentation names for readability. Links to documentation can be found in the cover letter. (Dave Hansen)

---
 arch/x86/include/asm/cpufeatures.h | 1 +
 1 file changed, 1 insertion(+)

index 2901d5d..83fc9d3 100644
@@ -368,6 +368,7 @@
 #define X86_FEATURE_MD_CLEAR		(18*32+10) /* VERW clears CPU buffers */
 #define X86_FEATURE_TSX_FORCE_ABORT	(18*32+13) /* "" TSX_FORCE_ABORT */
 #define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */
+#define X86_FEATURE_TSXLDTRK		(18*32+16) /* TSX Suspend Load Address Tracking */
 #define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */
 #define X86_FEATURE_ARCH_LBR		(18*32+19) /* Intel ARCH LBR */
 #define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */

1.8.3.1

TSX suspend load tracking instruction is supported by Intel processor, Sapphire Rapids. It aims to give a way to choose which memory accesses do not need to be tracked in the TSX read set. It's availability is indicated as CPUID.(EAX=7,ECX=0):EDX[bit 16].

Expose TSX Suspend Load Address Tracking feature in KVM CPUID, so KVM could pass this information to guests and they can make use of this feature accordingly.

---
Changes since v3:
* Remove SERIALIZE part and refactor commit message..

Changes since v2:
* Merge two patches into a single one. (Luck, Tony)
* Add overview introduction for features. (Sean Christopherson)
* Refactor commit message to explain why expose feature bits. (Luck, Tony)

---
 arch/x86/kvm/cpuid.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

index 3fd6eec..7456f9a 100644
@@ -371,7 +371,7 @@ void kvm_set_cpu_caps(void)
 		F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
 		F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
 		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
-		F(SERIALIZE)
+		F(SERIALIZE) | F(TSXLDTRK)
 	);
 
 	/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */

1.8.3.1