dt-bindings: msm: disp: add yaml schemas for DPU bindings

Add YAML schema for the device tree bindings for DSI

Signed-off-by Krishna Manikandan <[email protected]>

Changes in v1:
- Separate dsi controller bindings to a separate patch (Stephen Boyd)
- Merge dsi-common-controller.yaml and dsi-controller-main.yaml to a single file (Stephen Boyd)
- Drop supply entries and definitions from properties (Stephen Boyd)
- Modify phy-names property for dsi controller (Stephen Boyd)
- Remove boolean from description (Stephen Boyd)
- Drop pinctrl properties as they are standard entries (Stephen Boyd)
- Modify the description for ports property and keep the reference to the generic binding where this is defined (Stephen Boyd)
- Add description to clock names (Stephen Boyd)
- Correct the indendation (Stephen Boyd)
- Drop the label for display dt nodes and correct the node name (Stephen Boyd)

Changes in v2:
- Drop maxItems for clock (Stephen Boyd)
- Drop qcom,mdss-mdp-transfer-time-us as it is not used in upstream dt file (Stephen Boyd)
- Keep child node directly under soc node (Stephen Boyd)
- Drop qcom,sync-dual-dsi as it is not used in upstream dt

Changes in v3:
- Add description for register property (Stephen Boyd)

Changes in v4:
- Add maxItems for phys property (Stephen Boyd)
- Add maxItems for reg property (Stephen Boyd)
- Add reference for data-lanes property (Stephen Boyd)
- Remove soc from example (Stephen Boyd)

Changes in v5:
- Modify title and description (Stephen Boyd)
- Add required properties for ports node (Stephen Boyd)
- Add data-lanes in the example (Stephen Boyd)
- Drop qcom,master-dsi property (Stephen Boyd)

Changes in v6:
- Add required properties for port@0, port@1 and corresponding endpoints (Stephen Boyd)
- Add address-cells and size-cells for ports (Stephen Boyd)
- Use additionalProperties instead of unevaluatedProperties (Stephen Boyd)

---
 .../bindings/display/msm/dsi-controller-main.yaml  | 213 ++++++++++++++++++
 .../devicetree/bindings/display/msm/dsi.txt        | 249 ---------------------
 2 files changed, 213 insertions(+), 249 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
 delete mode 100644 Documentation/devicetree/bindings/display/msm/dsi.txt

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +57 -0

new file mode 100644
index 0000000..7858524
@@ -0,0 +1,213 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DSI controller
+
+maintainers:
+  - Krishna Manikandan <[email protected]>
+
+allOf:
+  - $ref: "../dsi-controller.yaml#"
+
+properties:
+  compatible:
+    items:
+      - const: qcom,mdss-dsi-ctrl
+
+  reg:
+    maxItems: 1
+
+  reg-names:
+    const: dsi_ctrl
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Display byte clock
+      - description: Display byte interface clock
+      - description: Display pixel clock
+      - description: Display escape clock
+      - description: Display AHB clock
+      - description: Display AXI clock
+
+  clock-names:
+    items:
+      - const: byte
+      - const: byte_intf
+      - const: pixel
+      - const: core
+      - const: iface
+      - const: bus
+
+  phys:
+    maxItems: 1
+
+  phy-names:
+    const: dsi
+
+  "#address-cells": true
+
+  "#size-cells": true
+
+  syscon-sfpb:

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +10 -0

+    $ref: "/schemas/graph.yaml#/properties/port"
+    type: object
+    description: |
+      Contains DSI controller input and output ports as children, each
+      containing one endpoint subnode.
+
+    properties:
+      port@0:
+        type: object
+        description: |

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +108 -0

+
+            required:
+              - remote-endpoint
+
+        required:
+          - reg
+          - endpoint
+
+      port@1:
+        type: object
+        description: |
+          Output endpoints of the controller.
+        properties:
+          reg:
+            const: 1
+
+          endpoint:
+            type: object
+            properties:
+              remote-endpoint: true
+              data-lanes:
+                items:
+                  - const: 0
+                  - const: 1
+                  - const: 2
+                  - const: 3
+
+            required:
+              - remote-endpoint
+              - data-lanes
+
+        required:
+          - reg
+          - endpoint
+
+    required:
+      - port@0
+      - port@1
+      - "#address-cells"
+      - "#size-cells"
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - clocks
+  - clock-names
+  - phys
+  - phy-names
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+     #include <dt-bindings/interrupt-controller/arm-gic.h>
+     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+
+     dsi@ae94000 {
+           compatible = "qcom,mdss-dsi-ctrl";
+           reg = <0x0ae94000 0x400>;
+           reg-names = "dsi_ctrl";
+
+           #address-cells = <1>;
+           #size-cells = <0>;
+
+           interrupt-parent = <&mdss>;
+           interrupts = <4>;
+
+           clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+                    <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+                    <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+                    <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+                    <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                    <&dispcc DISP_CC_MDSS_AXI_CLK>;
+           clock-names = "byte",
+                         "byte_intf",
+                         "pixel",
+                         "core",
+                         "iface",
+                         "bus";
+
+           phys = <&dsi0_phy>;
+           phy-names = "dsi";
+
+           ports {
+                  #address-cells = <1>;
+                  #size-cells = <0>;
+
+                  port@0 {
+                          reg = <0>;
+                          dsi0_in: endpoint {
+                                   remote-endpoint = <&dpu_intf1_out>;
+                          };
+                  };
+
+                  port@1 {
+                          reg = <1>;
+                          dsi0_out: endpoint {
+                                   remote-endpoint = <&sn65dsi86_in>;
+                                   data-lanes = <0 1 2 3>;
+                          };
+                  };
+           };
+     };
+...

Documentation/devicetree/bindings/display/msm/dsi.txt deleted +0 -70

deleted file mode 100644
index b9a64d3..0000000
@@ -1,249 +0,0 @@
-Qualcomm Technologies Inc. adreno/snapdragon DSI output
-
-DSI Controller:
-Required properties:
-- compatible:
-  * "qcom,mdss-dsi-ctrl"
-- reg: Physical base address and length of the registers of controller
-- reg-names: The names of register regions. The following regions are required:
-  * "dsi_ctrl"
-- interrupts: The interrupt signal from the DSI block.
-- power-domains: Should be <&mmcc MDSS_GDSC>.
-- clocks: Phandles to device clocks.
-- clock-names: the following clocks are required:
-  * "mdp_core"
-  * "iface"
-  * "bus"
-  * "core_mmss"
-  * "byte"
-  * "pixel"
-  * "core"
-  For DSIv2, we need an additional clock:
-   * "src"
-  For DSI6G v2.0 onwards, we need also need the clock:
-   * "byte_intf"
-- assigned-clocks: Parents of "byte" and "pixel" for the given platform.
-- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
-  by a DSI PHY block. See [1] for details on clock bindings.
-- vdd-supply: phandle to vdd regulator device node
-- vddio-supply: phandle to vdd-io regulator device node
-- vdda-supply: phandle to vdda regulator device node
-- phys: phandle to DSI PHY device node
-- phy-names: the name of the corresponding PHY device
-- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
-- ports: Contains 2 DSI controller ports as child nodes. Each port contains
-  an endpoint subnode as defined in [2] and [3].
-
-Optional properties:
-- panel@0: Node of panel connected to this DSI controller.
-  See files in [4] for each supported panel.
-- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
-  driving a panel which needs 2 DSI links.
-- qcom,master-dsi: Boolean value indicating if the DSI controller is driving
-  the master link of the 2-DSI panel.
-- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
-  driving a 2-DSI panel whose 2 links need receive command simultaneously.
-- pinctrl-names: the pin control state names; should contain "default"
-- pinctrl-0: the default pinctrl state (active)
-- pinctrl-n: the "sleep" pinctrl state
-- ports: contains DSI controller input and output ports as children, each
-  containing one endpoint subnode.
-
-  DSI Endpoint properties:
-  - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
-    input endpoint. For port@1, set to the MDP interface output. See [2] for
-    device graph info.
-
-  - data-lanes: this describes how the physical DSI data lanes are mapped
-    to the logical lanes on the given platform. The value contained in
-    index n describes what physical lane is mapped to the logical lane n
-    (DATAn, where n lies between 0 and 3). The clock lane position is fixed
-    and can't be changed. Hence, they aren't a part of the DT bindings. See
-    [3] for more info on the data-lanes property.
-
-    For example:
-
-    data-lanes = <3 0 1 2>;
-
-    The above mapping describes that the logical data lane DATA0 is mapped to
-    the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2
-    to phys DATA1 and logic DATA3 to phys DATA2.

Quoted 127 lines · Krishna Manikandan

Add YAML schema for the device tree bindings for DSI

Signed-off-by Krishna Manikandan <[email protected]>

Changes in v1:
- Separate dsi controller bindings to a separate patch (Stephen
Boyd)
- Merge dsi-common-controller.yaml and dsi-controller-main.yaml to a single file (Stephen Boyd)
- Drop supply entries and definitions from properties (Stephen
Boyd)
- Modify phy-names property for dsi controller (Stephen Boyd)
- Remove boolean from description (Stephen Boyd)
- Drop pinctrl properties as they are standard entries (Stephen
Boyd)
- Modify the description for ports property and keep the reference to the generic binding where this is defined (Stephen Boyd)
- Add description to clock names (Stephen Boyd)
- Correct the indendation (Stephen Boyd)
- Drop the label for display dt nodes and correct the node name (Stephen Boyd)

Changes in v2:
- Drop maxItems for clock (Stephen Boyd)
- Drop qcom,mdss-mdp-transfer-time-us as it is not used in
upstream
dt file (Stephen Boyd)
- Keep child node directly under soc node (Stephen Boyd)
- Drop qcom,sync-dual-dsi as it is not used in upstream dt

Changes in v3:
- Add description for register property (Stephen Boyd)

Changes in v4:
- Add maxItems for phys property (Stephen Boyd)
- Add maxItems for reg property (Stephen Boyd)
- Add reference for data-lanes property (Stephen Boyd)
- Remove soc from example (Stephen Boyd)

Changes in v5:
- Modify title and description (Stephen Boyd)
- Add required properties for ports node (Stephen Boyd)
- Add data-lanes in the example (Stephen Boyd)
- Drop qcom,master-dsi property (Stephen Boyd)

Changes in v6:
- Add required properties for port@0, port@1 and corresponding endpoints (Stephen Boyd)
- Add address-cells and size-cells for ports (Stephen Boyd)
- Use additionalProperties instead of unevaluatedProperties
(Stephen Boyd)

---
 .../bindings/display/msm/dsi-controller-main.yaml  | 213 
++++++++++++++++++
 .../devicetree/bindings/display/msm/dsi.txt        | 249 
---------------------
 2 files changed, 213 insertions(+), 249 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
 delete mode 100644 

Documentation/devicetree/bindings/display/msm/dsi.txt

(quoted diff) +0 -0

new file mode 100644
index 0000000..7858524

b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +4 -0

@@ -0,0 +1,213 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: 

http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +52 -0

+
+title: Qualcomm Display DSI controller
+
+maintainers:
+  - Krishna Manikandan <[email protected]>
+
+allOf:
+  - $ref: "../dsi-controller.yaml#"
+
+properties:
+  compatible:
+    items:
+      - const: qcom,mdss-dsi-ctrl
+
+  reg:
+    maxItems: 1
+
+  reg-names:
+    const: dsi_ctrl
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Display byte clock
+      - description: Display byte interface clock
+      - description: Display pixel clock
+      - description: Display escape clock
+      - description: Display AHB clock
+      - description: Display AXI clock
+
+  clock-names:
+    items:
+      - const: byte
+      - const: byte_intf
+      - const: pixel
+      - const: core
+      - const: iface
+      - const: bus
+
+  phys:
+    maxItems: 1
+
+  phy-names:
+    const: dsi
+
+  "#address-cells": true
+
+  "#size-cells": true
+
+  syscon-sfpb:

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml line 67

Quoted 10 lines

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +10 -0

+    description: A phandle to mmss_sfpb syscon node (only for DSIv2).
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  qcom,dual-dsi-mode:
+    type: boolean
+    description: |
+      Indicates if the DSI controller is driving a panel which needs
+      2 DSI links.
+
+  ports:

Same issues in this one.

Quoted 11 lines

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +4 -0

+    $ref: "/schemas/graph.yaml#/properties/port"
+    type: object
+    description: |
+      Contains DSI controller input and output ports as children, 

each

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +6 -0

+      containing one endpoint subnode.
+
+    properties:
+      port@0:
+        type: object
+        description: |

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml line 87

Quoted 10 lines

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +10 -0

+          Input endpoints of the controller.
+
+        properties:
+          reg:
+            const: 0
+
+          endpoint:
+            type: object
+            properties:
+              remote-endpoint:

Don't need to describe this, the common schema does.

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml line 93

Quoted 8 lines

(quoted diff) +2 -0

+                description: |
+                  For port@1, set to phandle of the connected 

panel/bridge's
+ input endpoint. For port@0, set to the MDP
interface output.

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +3 -0

+
+              data-lanes:
+                $ref: "/schemas/media/video-interfaces.yaml#"

Not how this reference works. Look at other examples.

Quoted 11 lines

(quoted diff) +2 -0

+                description: |
+                  This describes how the physical DSI data lanes are 

mapped
+ to the logical lanes on the given platform. The
value contained in
+ index n describes what physical lane is mapped to
the logical lane n
+ (DATAn, where n lies between 0 and 3). The clock
lane position is fixed
+ and can't be changed. Hence, they aren't a part of
the DT bindings.

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml line 105

Quoted 6 lines

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +6 -0

+
+                items:
+                  - const: 0
+                  - const: 1
+                  - const: 2
+                  - const: 3

If this is the only possible value, why does it need to be in DT?

Quoted 209 lines

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +95 -0

+
+            required:
+              - remote-endpoint
+
+        required:
+          - reg
+          - endpoint
+
+      port@1:
+        type: object
+        description: |
+          Output endpoints of the controller.
+        properties:
+          reg:
+            const: 1
+
+          endpoint:
+            type: object
+            properties:
+              remote-endpoint: true
+              data-lanes:
+                items:
+                  - const: 0
+                  - const: 1
+                  - const: 2
+                  - const: 3
+
+            required:
+              - remote-endpoint
+              - data-lanes
+
+        required:
+          - reg
+          - endpoint
+
+    required:
+      - port@0
+      - port@1
+      - "#address-cells"
+      - "#size-cells"
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - clocks
+  - clock-names
+  - phys
+  - phy-names
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+     #include <dt-bindings/interrupt-controller/arm-gic.h>
+     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+
+     dsi@ae94000 {
+           compatible = "qcom,mdss-dsi-ctrl";
+           reg = <0x0ae94000 0x400>;
+           reg-names = "dsi_ctrl";
+
+           #address-cells = <1>;
+           #size-cells = <0>;
+
+           interrupt-parent = <&mdss>;
+           interrupts = <4>;
+
+           clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+                    <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+                    <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+                    <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+                    <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                    <&dispcc DISP_CC_MDSS_AXI_CLK>;
+           clock-names = "byte",
+                         "byte_intf",
+                         "pixel",
+                         "core",
+                         "iface",
+                         "bus";
+
+           phys = <&dsi0_phy>;
+           phy-names = "dsi";
+
+           ports {
+                  #address-cells = <1>;
+                  #size-cells = <0>;
+
+                  port@0 {
+                          reg = <0>;
+                          dsi0_in: endpoint {
+                                   remote-endpoint = 

<&dpu_intf1_out>;

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +13 -0

+                          };
+                  };
+
+                  port@1 {
+                          reg = <1>;
+                          dsi0_out: endpoint {
+                                   remote-endpoint = <&sn65dsi86_in>;
+                                   data-lanes = <0 1 2 3>;
+                          };
+                  };
+           };
+     };
+...

Documentation/devicetree/bindings/display/msm/dsi.txt deleted +0 -7

deleted file mode 100644
index b9a64d3..0000000
@@ -1,249 +0,0 @@
-Qualcomm Technologies Inc. adreno/snapdragon DSI output
-
-DSI Controller:
-Required properties:
-- compatible:
-  * "qcom,mdss-dsi-ctrl"
-- reg: Physical base address and length of the registers of 

controller
-- reg-names: The names of register regions. The following regions are required:

Documentation/devicetree/bindings/display/msm/dsi.txt deleted +0 -17

-  * "dsi_ctrl"
-- interrupts: The interrupt signal from the DSI block.
-- power-domains: Should be <&mmcc MDSS_GDSC>.
-- clocks: Phandles to device clocks.
-- clock-names: the following clocks are required:
-  * "mdp_core"
-  * "iface"
-  * "bus"
-  * "core_mmss"
-  * "byte"
-  * "pixel"
-  * "core"
-  For DSIv2, we need an additional clock:
-   * "src"
-  For DSI6G v2.0 onwards, we need also need the clock:
-   * "byte_intf"
-- assigned-clocks: Parents of "byte" and "pixel" for the given 

platform.
-- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
- by a DSI PHY block. See [1] for details on clock bindings. -- vdd-supply: phandle to vdd regulator device node
-- vddio-supply: phandle to vdd-io regulator device node -- vdda-supply: phandle to vdda regulator device node
-- phys: phandle to DSI PHY device node
-- phy-names: the name of the corresponding PHY device
-- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2) -- ports: Contains 2 DSI controller ports as child nodes. Each port contains

Documentation/devicetree/bindings/display/msm/dsi.txt deleted +0 -6

-  an endpoint subnode as defined in [2] and [3].
-
-Optional properties:
-- panel@0: Node of panel connected to this DSI controller.
-  See files in [4] for each supported panel.
-- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller 

is
- driving a panel which needs 2 DSI links.
-- qcom,master-dsi: Boolean value indicating if the DSI controller is driving
- the master link of the 2-DSI panel.
-- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
- driving a 2-DSI panel whose 2 links need receive command simultaneously.
-- pinctrl-names: the pin control state names; should contain "default"
-- pinctrl-0: the default pinctrl state (active)
-- pinctrl-n: the "sleep" pinctrl state
-- ports: contains DSI controller input and output ports as children, each

Documentation/devicetree/bindings/display/msm/dsi.txt deleted +0 -4

-  containing one endpoint subnode.
-
-  DSI Endpoint properties:
-  - remote-endpoint: For port@0, set to phandle of the connected 

panel/bridge's
- input endpoint. For port@1, set to the MDP interface output. See
[2] for

Documentation/devicetree/bindings/display/msm/dsi.txt deleted +0 -3

-    device graph info.
-
-  - data-lanes: this describes how the physical DSI data lanes are 

mapped
- to the logical lanes on the given platform. The value contained
in
- index n describes what physical lane is mapped to the logical
lane n
- (DATAn, where n lies between 0 and 3). The clock lane position is
fixed
- and can't be changed. Hence, they aren't a part of the DT
bindings. See

Documentation/devicetree/bindings/display/msm/dsi.txt deleted +0 -7

-    [3] for more info on the data-lanes property.
-
-    For example:
-
-    data-lanes = <3 0 1 2>;
-
-    The above mapping describes that the logical data lane DATA0 is 

mapped to
- the physical data lane DATA3, logical DATA1 to physical DATA0,
logic DATA2

Documentation/devicetree/bindings/display/msm/dsi.txt deleted +0 -3

-    to phys DATA1 and logic DATA3 to phys DATA2.
-
-    There are only a limited number of physical to logical mappings 

possible:

Documentation/devicetree/bindings/display/msm/dsi.txt line 80

Quoted 8 lines

Documentation/devicetree/bindings/display/msm/dsi.txt deleted +0 -8

-    <0 1 2 3>
-    <1 2 3 0>
-    <2 3 0 1>
-    <3 0 1 2>
-    <0 3 2 1>
-    <1 0 3 2>
-    <2 1 0 3>
-    <3 2 1 0>

You've dropped all these?

Quoted 127 lines · Krishna Manikandan

Add YAML schema for the device tree bindings for DSI

Signed-off-by Krishna Manikandan <[email protected]>

Changes in v1:
- Separate dsi controller bindings to a separate patch (Stephen
Boyd)
- Merge dsi-common-controller.yaml and dsi-controller-main.yaml to a single file (Stephen Boyd)
- Drop supply entries and definitions from properties (Stephen
Boyd)
- Modify phy-names property for dsi controller (Stephen Boyd)
- Remove boolean from description (Stephen Boyd)
- Drop pinctrl properties as they are standard entries (Stephen
Boyd)
- Modify the description for ports property and keep the reference to the generic binding where this is defined (Stephen Boyd)
- Add description to clock names (Stephen Boyd)
- Correct the indendation (Stephen Boyd)
- Drop the label for display dt nodes and correct the node name (Stephen Boyd)

Changes in v2:
- Drop maxItems for clock (Stephen Boyd)
- Drop qcom,mdss-mdp-transfer-time-us as it is not used in
upstream
dt file (Stephen Boyd)
- Keep child node directly under soc node (Stephen Boyd)
- Drop qcom,sync-dual-dsi as it is not used in upstream dt

Changes in v3:
- Add description for register property (Stephen Boyd)

Changes in v4:
- Add maxItems for phys property (Stephen Boyd)
- Add maxItems for reg property (Stephen Boyd)
- Add reference for data-lanes property (Stephen Boyd)
- Remove soc from example (Stephen Boyd)

Changes in v5:
- Modify title and description (Stephen Boyd)
- Add required properties for ports node (Stephen Boyd)
- Add data-lanes in the example (Stephen Boyd)
- Drop qcom,master-dsi property (Stephen Boyd)

Changes in v6:
- Add required properties for port@0, port@1 and corresponding endpoints (Stephen Boyd)
- Add address-cells and size-cells for ports (Stephen Boyd)
- Use additionalProperties instead of unevaluatedProperties
(Stephen Boyd)

---
 .../bindings/display/msm/dsi-controller-main.yaml  | 213 
++++++++++++++++++
 .../devicetree/bindings/display/msm/dsi.txt        | 249 
---------------------
 2 files changed, 213 insertions(+), 249 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
 delete mode 100644 

Documentation/devicetree/bindings/display/msm/dsi.txt

(quoted diff) +0 -0

new file mode 100644
index 0000000..7858524

b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +4 -0

@@ -0,0 +1,213 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: 

http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +52 -0

+
+title: Qualcomm Display DSI controller
+
+maintainers:
+  - Krishna Manikandan <[email protected]>
+
+allOf:
+  - $ref: "../dsi-controller.yaml#"
+
+properties:
+  compatible:
+    items:
+      - const: qcom,mdss-dsi-ctrl
+
+  reg:
+    maxItems: 1
+
+  reg-names:
+    const: dsi_ctrl
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Display byte clock
+      - description: Display byte interface clock
+      - description: Display pixel clock
+      - description: Display escape clock
+      - description: Display AHB clock
+      - description: Display AXI clock
+
+  clock-names:
+    items:
+      - const: byte
+      - const: byte_intf
+      - const: pixel
+      - const: core
+      - const: iface
+      - const: bus
+
+  phys:
+    maxItems: 1
+
+  phy-names:
+    const: dsi
+
+  "#address-cells": true
+
+  "#size-cells": true
+
+  syscon-sfpb:

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml line 67

Quoted 10 lines

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +10 -0

+    description: A phandle to mmss_sfpb syscon node (only for DSIv2).
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  qcom,dual-dsi-mode:
+    type: boolean
+    description: |
+      Indicates if the DSI controller is driving a panel which needs
+      2 DSI links.
+
+  ports:

Same issues in this one.

Quoted 11 lines

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +4 -0

+    $ref: "/schemas/graph.yaml#/properties/port"
+    type: object
+    description: |
+      Contains DSI controller input and output ports as children, 

each

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +6 -0

+      containing one endpoint subnode.
+
+    properties:
+      port@0:
+        type: object
+        description: |

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml line 87

Quoted 10 lines

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +10 -0

+          Input endpoints of the controller.
+
+        properties:
+          reg:
+            const: 0
+
+          endpoint:
+            type: object
+            properties:
+              remote-endpoint:

Don't need to describe this, the common schema does.

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml line 93

Quoted 8 lines

(quoted diff) +2 -0

+                description: |
+                  For port@1, set to phandle of the connected 

panel/bridge's
+ input endpoint. For port@0, set to the MDP
interface output.

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +3 -0

+
+              data-lanes:
+                $ref: "/schemas/media/video-interfaces.yaml#"

Not how this reference works. Look at other examples.

Quoted 11 lines

(quoted diff) +2 -0

+                description: |
+                  This describes how the physical DSI data lanes are 

mapped
+ to the logical lanes on the given platform. The
value contained in
+ index n describes what physical lane is mapped to
the logical lane n
+ (DATAn, where n lies between 0 and 3). The clock
lane position is fixed
+ and can't be changed. Hence, they aren't a part of
the DT bindings.

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml line 105

Quoted 6 lines

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +6 -0

+
+                items:
+                  - const: 0
+                  - const: 1
+                  - const: 2
+                  - const: 3

If this is the only possible value, why does it need to be in DT?

Quoted 209 lines

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +95 -0

+
+            required:
+              - remote-endpoint
+
+        required:
+          - reg
+          - endpoint
+
+      port@1:
+        type: object
+        description: |
+          Output endpoints of the controller.
+        properties:
+          reg:
+            const: 1
+
+          endpoint:
+            type: object
+            properties:
+              remote-endpoint: true
+              data-lanes:
+                items:
+                  - const: 0
+                  - const: 1
+                  - const: 2
+                  - const: 3
+
+            required:
+              - remote-endpoint
+              - data-lanes
+
+        required:
+          - reg
+          - endpoint
+
+    required:
+      - port@0
+      - port@1
+      - "#address-cells"
+      - "#size-cells"
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - clocks
+  - clock-names
+  - phys
+  - phy-names
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+     #include <dt-bindings/interrupt-controller/arm-gic.h>
+     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+
+     dsi@ae94000 {
+           compatible = "qcom,mdss-dsi-ctrl";
+           reg = <0x0ae94000 0x400>;
+           reg-names = "dsi_ctrl";
+
+           #address-cells = <1>;
+           #size-cells = <0>;
+
+           interrupt-parent = <&mdss>;
+           interrupts = <4>;
+
+           clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+                    <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+                    <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+                    <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+                    <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                    <&dispcc DISP_CC_MDSS_AXI_CLK>;
+           clock-names = "byte",
+                         "byte_intf",
+                         "pixel",
+                         "core",
+                         "iface",
+                         "bus";
+
+           phys = <&dsi0_phy>;
+           phy-names = "dsi";
+
+           ports {
+                  #address-cells = <1>;
+                  #size-cells = <0>;
+
+                  port@0 {
+                          reg = <0>;
+                          dsi0_in: endpoint {
+                                   remote-endpoint = 

<&dpu_intf1_out>;

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +13 -0

+                          };
+                  };
+
+                  port@1 {
+                          reg = <1>;
+                          dsi0_out: endpoint {
+                                   remote-endpoint = <&sn65dsi86_in>;
+                                   data-lanes = <0 1 2 3>;
+                          };
+                  };
+           };
+     };
+...

Documentation/devicetree/bindings/display/msm/dsi.txt deleted +0 -7

deleted file mode 100644
index b9a64d3..0000000
@@ -1,249 +0,0 @@
-Qualcomm Technologies Inc. adreno/snapdragon DSI output
-
-DSI Controller:
-Required properties:
-- compatible:
-  * "qcom,mdss-dsi-ctrl"
-- reg: Physical base address and length of the registers of 

controller
-- reg-names: The names of register regions. The following regions are required:

Documentation/devicetree/bindings/display/msm/dsi.txt deleted +0 -17

-  * "dsi_ctrl"
-- interrupts: The interrupt signal from the DSI block.
-- power-domains: Should be <&mmcc MDSS_GDSC>.
-- clocks: Phandles to device clocks.
-- clock-names: the following clocks are required:
-  * "mdp_core"
-  * "iface"
-  * "bus"
-  * "core_mmss"
-  * "byte"
-  * "pixel"
-  * "core"
-  For DSIv2, we need an additional clock:
-   * "src"
-  For DSI6G v2.0 onwards, we need also need the clock:
-   * "byte_intf"
-- assigned-clocks: Parents of "byte" and "pixel" for the given 

platform.
-- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
- by a DSI PHY block. See [1] for details on clock bindings. -- vdd-supply: phandle to vdd regulator device node
-- vddio-supply: phandle to vdd-io regulator device node -- vdda-supply: phandle to vdda regulator device node
-- phys: phandle to DSI PHY device node
-- phy-names: the name of the corresponding PHY device
-- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2) -- ports: Contains 2 DSI controller ports as child nodes. Each port contains

Documentation/devicetree/bindings/display/msm/dsi.txt deleted +0 -6

-  an endpoint subnode as defined in [2] and [3].
-
-Optional properties:
-- panel@0: Node of panel connected to this DSI controller.
-  See files in [4] for each supported panel.
-- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller 

is
- driving a panel which needs 2 DSI links.
-- qcom,master-dsi: Boolean value indicating if the DSI controller is driving
- the master link of the 2-DSI panel.
-- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
- driving a 2-DSI panel whose 2 links need receive command simultaneously.
-- pinctrl-names: the pin control state names; should contain "default"
-- pinctrl-0: the default pinctrl state (active)
-- pinctrl-n: the "sleep" pinctrl state
-- ports: contains DSI controller input and output ports as children, each

Documentation/devicetree/bindings/display/msm/dsi.txt deleted +0 -4

-  containing one endpoint subnode.
-
-  DSI Endpoint properties:
-  - remote-endpoint: For port@0, set to phandle of the connected 

panel/bridge's
- input endpoint. For port@1, set to the MDP interface output. See
[2] for

Documentation/devicetree/bindings/display/msm/dsi.txt deleted +0 -3

-    device graph info.
-
-  - data-lanes: this describes how the physical DSI data lanes are 

mapped
- to the logical lanes on the given platform. The value contained
in
- index n describes what physical lane is mapped to the logical
lane n
- (DATAn, where n lies between 0 and 3). The clock lane position is
fixed
- and can't be changed. Hence, they aren't a part of the DT
bindings. See

Documentation/devicetree/bindings/display/msm/dsi.txt deleted +0 -7

-    [3] for more info on the data-lanes property.
-
-    For example:
-
-    data-lanes = <3 0 1 2>;
-
-    The above mapping describes that the logical data lane DATA0 is 

mapped to
- the physical data lane DATA3, logical DATA1 to physical DATA0,
logic DATA2

Documentation/devicetree/bindings/display/msm/dsi.txt deleted +0 -3

-    to phys DATA1 and logic DATA3 to phys DATA2.
-
-    There are only a limited number of physical to logical mappings 

possible:

Documentation/devicetree/bindings/display/msm/dsi.txt line 80

Quoted 8 lines

Documentation/devicetree/bindings/display/msm/dsi.txt deleted +0 -8

-    <0 1 2 3>
-    <1 2 3 0>
-    <2 3 0 1>
-    <3 0 1 2>
-    <0 3 2 1>
-    <1 0 3 2>
-    <2 1 0 3>
-    <3 2 1 0>

You've dropped all these?

Quoted 26 lines · Rob Herring

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml line 93

Quoted 4 lines · Krishna Manikandan

Add YAML schema for the device tree bindings for DSI

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +2 -0

+              data-lanes:
+                $ref: "/schemas/media/video-interfaces.yaml#"

Not how this reference works. Look at other examples.

Quoted 11 lines

(quoted diff) +2 -0

+                description: |
+                  This describes how the physical DSI data lanes are

mapped
+ to the logical lanes on the given platform. The
value contained in
+ index n describes what physical lane is mapped to
the logical lane n
+ (DATAn, where n lies between 0 and 3). The clock
lane position is fixed
+ and can't be changed. Hence, they aren't a part of
the DT bindings.

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml line 105

Quoted 6 lines

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml new file +6 -0

+
+                items:
+                  - const: 0
+                  - const: 1
+                  - const: 2
+                  - const: 3

Quoted 1 line

If this is the only possible value, why does it need to be in DT?

Hi Rob,
These are the possible values:

Documentation/devicetree/bindings/display/msm/dsi.txt deleted +0 -8

-    <0 1 2 3>
-    <1 2 3 0>
-    <2 3 0 1>
-    <3 0 1 2>
-    <0 3 2 1>
-    <1 0 3 2>
-    <2 1 0 3>
-    <3 2 1 0>

Shall I follow the below mentioned approach for defining these values ? oneOf:
- items:
- const: 0
- const: 1
- const: 2
- const: 3
- items:
- const: 1
- const: 2
- const: 3
- const: 0
- items:
- const: 2
- const: 3
- const: 0
- const: 1
- items:
- const: 3
- const: 0
- const: 1
- const: 2
- items:
- const: 0
- const: 3
- const: 2
- const: 1
- items:
- const: 1
- const: 0
- const: 3
- const: 2
- items:
- const: 2

- const: 1
- const: 0
- const: 3
- items:
- const: 3
- const: 2
- const: 1
- const: 0

Add YAML schema for the device tree bindings for DSI PHY.

Signed-off-by Krishna Manikandan <[email protected]>

Changes in v1:
- Merge dsi-phy.yaml and dsi-phy-10nm.yaml (Stephen Boyd)
- Remove qcom,dsi-phy-regulator-ldo-mode (Stephen Boyd)
- Add clock cells properly (Stephen Boyd)
- Remove unnecessary decription from clock names (Stephen Boyd)
- Add pin names for the supply entries for 10nm phy which is used in sc7180 and sdm845 (Stephen Boyd)
- Remove unused header files from examples (Stephen Boyd)
- Drop labels for display nodes and correct node name (Stephen Boyd)

Changes in v2:
- Drop maxItems for clock (Stephen Boyd)
- Add vdds supply pin information for sdm845 (Stephen Boyd)
- Add examples for 14nm, 20nm and 28nm phy yaml files (Stephen Boyd)
- Keep child nodes directly under soc node (Stephen Boyd)

Changes in v3:
- Use a separate yaml file to describe the common properties for all the dsi phy versions (Stephen Boyd)
- Remove soc from examples (Stephen Boyd)
- Add description for register property

Changes in v4:
- Modify the title for all the phy versions (Stephen Boyd)
- Drop description for all the phy versions (Stephen Boyd)
- Modify the description for register property (Stephen Boyd)

Changes in v5:
- Remove unused properties from common dsi phy file
- Add clock-cells and phy-cells to required property list (Stephen Boyd)

---
 .../bindings/display/msm/dsi-phy-10nm.yaml         | 68 +++++++++++++++++++++
 .../bindings/display/msm/dsi-phy-14nm.yaml         | 66 ++++++++++++++++++++
 .../bindings/display/msm/dsi-phy-20nm.yaml         | 71 ++++++++++++++++++++++
 .../bindings/display/msm/dsi-phy-28nm.yaml         | 68 +++++++++++++++++++++
 .../bindings/display/msm/dsi-phy-common.yaml       | 40 ++++++++++++
 5 files changed, 313 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
 create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
 create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml
 create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml
 create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml

Add bindings for Snapdragon DisplayPort controller driver.

Signed-off-by Chandan Uddaraju <[email protected]>

Signed-off-by Vara Reddy <[email protected]>

Signed-off-by Tanmay Shah <[email protected]>

Signed-off-by Kuogee Hsieh <[email protected]>

Signed-off-by Krishna Manikandan <[email protected]>

Changes in V2:
-Provide details about sel-gpio

Changes in V4:

(quoted diff) +0 -2

-Provide details about max dp lanes
-Change the commit text

Changes in V5:
-moved dp.txt to yaml file

Changes in v6:
- Squash all AUX LUT properties into one pattern Property
- Make aux-cfg[0-9]-settings properties optional
- Remove PLL/PHY bindings from DP controller dts
- Add DP clocks description
- Remove _clk suffix from clock names
- Rename pixel clock to stream_pixel
- Remove redundant bindings (GPIO, PHY, HDCP clock, etc..)
- Fix indentation
- Add Display Port as interface of DPU in DPU bindings and add port mapping accordingly.

Chages in v7:
- Add dp-controller.yaml file common between multiple SOC
- Rename dp-sc7180.yaml to dp-controller-sc7180.yaml
- change compatible string and add SOC name to it.
- Remove Root clock generator for pixel clock
- Add assigned-clocks and assigned-clock-parents bindings
- Remove redundant properties, descriptions and blank lines
- Add DP port in DPU bindings
- Update depends-on tag in commit message and rebase change accordingly

Changes in v8:
- Add MDSS AHB clock in bindings

Changes in v9:
- Remove redundant reg-name property
- Change assigned-clocks and assigned-clocks-parents counts to 2
- Use IRQ flags in example dts

Changes in v10:
- Change title of this patch as it does not contain PLL bindings anymore
- Remove redundant properties
- Remove use of IRQ flag
- Fix ports property

Changes in v11:
- add ports required of both #address-cells and #size-cells
- add required operating-points-v2
- add required #sound-dai-cells
- add required power-domains
- update maintainer list

Changes in v12:
- remove soc node from examples (Stephen Boyd)
- split dpu-sc7180.yaml changes to separate patch (Stephen Boyd)

Changes in v13:
- add assigned-clocks
- add assigned-clock-parents

---
 .../bindings/display/msm/dp-controller.yaml        | 162 +++++++++++++++++++++
 1 file changed, 162 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/msm/dp-controller.yaml

Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +60 -0

new file mode 100644
index 0000000..3a02c6c
@@ -0,0 +1,162 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MSM Display Port Controller
+
+maintainers:
+  - Kuogee Hsieh <[email protected]>
+
+description: |
+  Device tree bindings for DisplayPort host controller for MSM targets
+  that are compatible with VESA DisplayPort interface specification.
+
+properties:
+  compatible:
+    enum:
+      - qcom,sc7180-dp
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: AHB clock to enable register access
+      - description: Display Port AUX clock
+      - description: Display Port Link clock
+      - description: Link interface clock between DP and PHY
+      - description: Display Port Pixel clock
+
+  clock-names:
+    items:
+      - const: core_iface
+      - const: core_aux
+      - const: ctrl_link
+      - const: ctrl_link_iface
+      - const: stream_pixel
+
+  assigned-clocks:
+    items:
+      - description: link clock source
+      - description: pixel clock source
+
+  assigned-clock-parents:
+    items:
+      - description: phy 0 parent
+      - description: phy 1 parent
+
+  phys:
+    maxItems: 1
+
+  phy-names:
+    items:
+      - const: dp
+
+  operating-points-v2:

Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file +89 -0

+    properties:
+      "#address-cells":
+        const: 1
+
+      "#size-cells":
+        const: 0
+
+      port@0:
+        type: object
+        description: Input endpoint of the controller
+
+      port@1:
+        type: object
+        description: Output endpoint of the controller
+
+    required:
+      - "#address-cells"
+      - "#size-cells"
+
+    additionalProperties: false
+
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - phys
+  - phy-names
+  - "#sound-dai-cells"
+  - power-domains
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
+    #include <dt-bindings/power/qcom-aoss-qmp.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
+
+    displayport-controller@ae90000 {
+        compatible = "qcom,sc7180-dp";
+        reg = <0xae90000 0x1400>;
+        interrupt-parent = <&mdss>;
+        interrupts = <12>;
+        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+                 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+                 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+                 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+        clock-names = "core_iface", "core_aux",
+                      "ctrl_link",
+                      "ctrl_link_iface", "stream_pixel";
+
+        assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
+                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+
+        assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
+
+        phys = <&dp_phy>;
+        phy-names = "dp";
+
+        #sound-dai-cells = <0>;
+
+        power-domains = <&rpmhpd SC7180_CX>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+                endpoint {
+                    remote-endpoint = <&dpu_intf0_out>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+                endpoint {
+                    remote-endpoint = <&typec>;
+                };
+            };
+        };
+    };
+...

Signature · 1 line

2.7.4

MSM Mobile Display Subsytem (MDSS) encapsulates sub-blocks like DPU display controller, DSI etc. Add YAML schema for DPU device tree bindings.

Signed-off-by Krishna Manikandan <[email protected]>

Changes in v2:
- Changed dpu to DPU (Sam Ravnborg)
- Fixed indentation issues (Sam Ravnborg)
- Added empty line between different properties (Sam Ravnborg)
- Replaced reference txt files with their corresponding yaml files (Sam Ravnborg)
- Modified the file to use "|" only when it is necessary (Sam Ravnborg)

Changes in v3:
- Corrected the license used (Rob Herring)
- Added maxItems for properties (Rob Herring)
- Dropped generic descriptions (Rob Herring)
- Added ranges property (Rob Herring)
- Corrected the indendation (Rob Herring)
- Added additionalProperties (Rob Herring)
- Split dsi file into two, one for dsi controller and another one for dsi phy per target (Rob Herring)
- Corrected description for pinctrl-names (Rob Herring)
- Corrected the examples used in yaml file (Rob Herring)
- Delete dsi.txt and dpu.txt (Rob Herring)

Changes in v4:
- Move schema up by one level (Rob Herring)
- Add patternProperties for mdp node (Rob Herring)
- Corrected description of some properties (Rob Herring)

Changes in v5:
- Correct the indentation (Rob Herring)
- Remove unnecessary description from properties (Rob Herring)
- Correct the number of interconnect entries (Rob Herring)
- Add interconnect names for sc7180 (Rob Herring)
- Add description for ports (Rob Herring)
- Remove common properties (Rob Herring)
- Add unevalutatedProperties (Rob Herring)
- Reference existing dsi controller yaml in the common dsi controller file (Rob Herring)
- Correct the description of clock names to include only the clocks that are required (Rob Herring)
- Remove properties which are already covered under the common binding (Rob Herring)
- Add dsi phy supply nodes which are required for sc7180 and sdm845 targets (Rob Herring)
- Add type ref for syscon-sfpb (Rob Herring)

Changes in v6:
- Fixed errors during dt_binding_check (Rob Herring)
- Add maxItems for phys and phys-names (Rob Herring)
- Use unevaluatedProperties wherever required (Rob Herring)
- Removed interrupt controller from required properties for dsi controller (Rob Herring)
- Add constraints for dsi-phy reg-names based on the compatible phy version (Rob Herring)
- Add constraints for dsi-phy supply nodes based on the compatible phy version (Rob Herring)

Changes in v7:
- Add default value for qcom,mdss-mdp-transfer-time-us (Rob Herring)
- Modify the schema for data-lanes (Rob Herring)
- Split the phy schema into separate schemas based on the phy version (Rob Herring)

Changes in v8:
- Resolve merge conflicts with latest dsi.txt file
- Include dp yaml change also in the same series

Changes in v9:
- Combine target specific dsi controller yaml files to a single yaml file (Rob Herring)
- Combine target specific dsi phy yaml files into a single yaml file (Rob Herring)
- Use unevaluatedProperties and additionalProperties wherever required
- Remove duplicate properties from common yaml files

Changes in v10:
- Split the patch into separate patches for DPU, DSI and PHY (Stephen Boyd)
- Drop unnecessary fullstop (Stephen Boyd)
- Add newline whereever required (Stephen Boyd)
- Add description for clock used (Stephen Boyd)
- Modify the description for interconnect entries (Stephen Boyd)
- Drop assigned clock entries as it a generic property (Stephen Boyd)
- Correct the definition for interrupts (Stephen Boyd)
- Drop clock names from required properties (Stephen Boyd)
- Drop labels for display nodes from example (Stephen Boyd)
- Drop flags from interrupts entries (Stephen Boyd)

Changes in v11:
- Drop maxItems for clocks (Stephen Boyd)

Changes in v12:
- Add description for register property (Stephen Boyd)
- Add maxItems for interrupts (Stephen Boyd)
- Add description for iommus property (Stephen Boyd)
- Add description for interconnects (Stephen Boyd)
- Change display node name to display_controller (Stephen Boyd)

Changes in v13:
- Add maxItems for reg property (Stephen Boyd)
- Add ranges property in example (Stephen Boyd)
- Modify description for iommus property (Stephen Boyd)
- Add Dp bindings for ports in the same patch (Stephen Boyd)
- Remove soc from examples and change address and size cells accordingly (Stephen Boyd)
- Add reference for ports

Changes in v14:
- Modify title for SC7180 and SDM845 yaml files (Stephen Boyd)
- Add required list for display-controller node (Stephen Boyd)
- Rename mdss node name to display-subsytem (Stephen Boyd)

---
 .../bindings/display/msm/dpu-sc7180.yaml           | 215 +++++++++++++++++++++
 .../bindings/display/msm/dpu-sdm845.yaml           | 196 +++++++++++++++++++
 .../devicetree/bindings/display/msm/dpu.txt        | 141 --------------
 3 files changed, 411 insertions(+), 141 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
 create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
 delete mode 100644 Documentation/devicetree/bindings/display/msm/dpu.txt

Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +96 -0

new file mode 100644
index 0000000..36531a5
@@ -0,0 +1,215 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DPU dt properties for SC7180 target
+
+maintainers:
+  - Krishna Manikandan <[email protected]>
+
+description: |
+  Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
+  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
+  bindings of MDSS and DPU are mentioned for SC7180 target.
+
+properties:
+  compatible:
+    items:
+      - const: qcom,sc7180-mdss
+
+  reg:
+    maxItems: 1
+
+  reg-names:
+    const: mdss
+
+  power-domains:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Display AHB clock from gcc
+      - description: Display AHB clock from dispcc
+      - description: Display core clock
+
+  clock-names:
+    items:
+      - const: iface
+      - const: ahb
+      - const: core
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 1
+
+  iommus:
+    items:
+      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
+
+  ranges: true
+
+  interconnects:
+    items:
+      - description: Interconnect path specifying the port ids for data bus
+
+  interconnect-names:
+    const: mdp0-mem
+
+patternProperties:
+  "^display-controller@[0-9a-f]+$":
+    type: object
+    description: Node containing the properties of DPU.
+
+    properties:
+      compatible:
+        items:
+          - const: qcom,sc7180-dpu
+
+      reg:
+        items:
+          - description: Address offset and size for mdp register set
+          - description: Address offset and size for vbif register set
+
+      reg-names:
+        items:
+          - const: mdp
+          - const: vbif
+
+      clocks:
+        items:
+          - description: Display hf axi clock
+          - description: Display ahb clock
+          - description: Display rotator clock
+          - description: Display lut clock
+          - description: Display core clock
+          - description: Display vsync clock
+
+      clock-names:
+        items:
+          - const: bus
+          - const: iface

Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +10 -0

+    required:
+      - compatible
+      - reg
+      - reg-names
+      - clocks
+      - interrupts
+      - ports
+
+required:
+  - compatible

Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file +70 -0

+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
+    #include <dt-bindings/clock/qcom,gcc-sc7180.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interconnect/qcom,sdm845.h>
+
+    display-subsystem@ae00000 {
+         #address-cells = <1>;
+         #size-cells = <1>;
+         compatible = "qcom,sc7180-mdss";
+         reg = <0xae00000 0x1000>;
+         reg-names = "mdss";
+         power-domains = <&dispcc MDSS_GDSC>;
+         clocks = <&gcc GCC_DISP_AHB_CLK>,
+                  <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
+         clock-names = "iface", "ahb", "core";
+
+         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+         interrupt-controller;
+         #interrupt-cells = <1>;
+
+         interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
+         interconnect-names = "mdp0-mem";
+
+         iommus = <&apps_smmu 0x800 0x2>;
+         ranges;
+
+         display-controller@ae01000 {
+                   compatible = "qcom,sc7180-dpu";
+                   reg = <0x0ae01000 0x8f000>,
+                         <0x0aeb0000 0x2008>;
+
+                   reg-names = "mdp", "vbif";
+
+                   clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+                            <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                            <&dispcc DISP_CC_MDSS_ROT_CLK>,
+                            <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+                            <&dispcc DISP_CC_MDSS_MDP_CLK>,
+                            <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+                   clock-names = "bus", "iface", "rot", "lut", "core",
+                                 "vsync";
+
+                   interrupt-parent = <&mdss>;
+                   interrupts = <0>;
+
+                   ports {
+                           #address-cells = <1>;
+                           #size-cells = <0>;
+
+                           port@0 {
+                                   reg = <0>;
+                                   dpu_intf1_out: endpoint {
+                                                  remote-endpoint = <&dsi0_in>;
+                                   };
+                           };
+
+                            port@2 {
+                                    reg = <2>;
+                                    dpu_intf0_out: endpoint {
+                                                   remote-endpoint = <&dp_in>;
+                                    };
+                            };
+                   };
+         };
+    };
+...

Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml new file +85 -0

new file mode 100644
index 0000000..c744559
@@ -0,0 +1,196 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DPU dt properties for SDM845 target
+
+maintainers:
+  - Krishna Manikandan <[email protected]>
+
+description: |
+  Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
+  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
+  bindings of MDSS and DPU are mentioned for SDM845 target.
+
+properties:
+  compatible:
+    items:
+      - const: qcom,sdm845-mdss
+
+  reg:
+    maxItems: 1
+
+  reg-names:
+    const: mdss
+
+  power-domains:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Display AHB clock from gcc
+      - description: Display AXI clock
+      - description: Display core clock
+
+  clock-names:
+    items:
+      - const: iface
+      - const: bus
+      - const: core
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 1
+
+  iommus:
+    items:
+      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
+      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
+
+  ranges: true
+
+patternProperties:
+  "^display-controller@[0-9a-f]+$":
+    type: object
+    description: Node containing the properties of DPU.
+
+    properties:
+      compatible:
+        items:
+          - const: qcom,sdm845-dpu
+
+      reg:
+        items:
+          - description: Address offset and size for mdp register set
+          - description: Address offset and size for vbif register set
+
+      reg-names:
+        items:
+          - const: mdp
+          - const: vbif
+
+      clocks:
+        items:
+          - description: Display ahb clock
+          - description: Display axi clock
+          - description: Display core clock
+          - description: Display vsync clock
+
+      clock-names:

Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml new file +27 -0

+        $ref: /schemas/graph.yaml#/properties/port
+        type: object
+        description: |
+          Contains the list of output ports from DPU device. These ports
+          connect to interfaces that are external to the DPU hardware,
+          such as DSI, DP etc. Each output port contains an endpoint that
+          describes how it is connected to an external interface.
+
+        properties:
+          port@0:
+            type: object
+            description: DPU_INTF1 (DSI1)
+
+          port@1:
+            type: object
+            description: DPU_INTF2 (DSI2)
+
+    required:
+      - compatible
+      - reg
+      - reg-names
+      - clocks
+      - interrupts
+      - ports
+
+required:
+  - compatible

Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml new file +64 -0

+
+examples:
+- |
+    #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    display-subsystem@ae00000 {
+          #address-cells = <1>;
+          #size-cells = <1>;
+          compatible = "qcom,sdm845-mdss";
+          reg = <0x0ae00000 0x1000>;
+          reg-names = "mdss";
+          power-domains = <&dispcc MDSS_GDSC>;
+
+          clocks = <&gcc GCC_DISP_AHB_CLK>,
+                   <&gcc GCC_DISP_AXI_CLK>,
+                   <&dispcc DISP_CC_MDSS_MDP_CLK>;
+          clock-names = "iface", "bus", "core";
+
+          interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+          interrupt-controller;
+          #interrupt-cells = <1>;
+
+          iommus = <&apps_smmu 0x880 0x8>,
+                   <&apps_smmu 0xc80 0x8>;
+          ranges;
+
+          display-controller@ae01000 {
+                    compatible = "qcom,sdm845-dpu";
+                    reg = <0x0ae01000 0x8f000>,
+                          <0x0aeb0000 0x2008>;
+                    reg-names = "mdp", "vbif";
+
+                    clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                             <&dispcc DISP_CC_MDSS_AXI_CLK>,
+                             <&dispcc DISP_CC_MDSS_MDP_CLK>,
+                             <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+                    clock-names = "iface", "bus", "core", "vsync";
+
+                    interrupt-parent = <&mdss>;
+                    interrupts = <0>;
+
+                    ports {
+                           #address-cells = <1>;
+                           #size-cells = <0>;
+
+                           port@0 {
+                                   reg = <0>;
+                                   dpu_intf1_out: endpoint {
+                                                  remote-endpoint = <&dsi0_in>;
+                                   };
+                           };
+
+                           port@1 {
+                                   reg = <1>;
+                                   dpu_intf2_out: endpoint {
+                                                  remote-endpoint = <&dsi1_in>;
+                                   };
+                           };
+                    };
+          };
+    };
+...