Skip to contentSkip to conversation

arm64: dts: qcom: sc7280: Fixup cpufreq domain info for cpu7

PATCH In review Sibi Sankar 3 participants 3 messages Jul 20, 2021 – Jul 21, 2021

Subsystems (5)
lore
Share & tools
lore
#0 lore raw

PATCH 1/1 arm64: dts: qcom: sc7280: Fixup cpufreq domain info for cpu7

The SC7280 SoC supports a 4-Silver/3-Gold/1-Gold+ configuration and hence the cpu7 node should point to cpufreq domain 2 instead.

Fixes 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node")
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm64/boot/dts/qcom/sc7280.dtsi +1 -1
index a8c274ad74c4..188c5768a55a 100644
@@ -200,7 +200,7 @@
 					   &BIG_CPU_SLEEP_1
 					   &CLUSTER_SLEEP_0>;
 			next-level-cache = <&L2_700>;
-			qcom,freq-domain = <&cpufreq_hw 1>;
+			qcom,freq-domain = <&cpufreq_hw 2>;
 			#cooling-cells = <2>;
 			L2_700: l2-cache {
 				compatible = "cache";
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Reviewed-by on v1 1/1
#1 lore raw
Quoted 15 lines · Sibi Sankar

The SC7280 SoC supports a 4-Silver/3-Gold/1-Gold+ configuration and hence the cpu7 node should point to cpufreq domain 2 instead.

Fixes 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node")
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm64/boot/dts/qcom/sc7280.dtsi +0 -0
index a8c274ad74c4..188c5768a55a 100644

arch/arm64/boot/dts/qcom/sc7280.dtsi line 206

Quoted 8 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +1 -1
@@ -200,7 +200,7 @@
 					   &BIG_CPU_SLEEP_1
 					   &CLUSTER_SLEEP_0>;
 			next-level-cache = <&L2_700>;
-			qcom,freq-domain = <&cpufreq_hw 1>;
+			qcom,freq-domain = <&cpufreq_hw 2>;
 			#cooling-cells = <2>;
 			L2_700: l2-cache {
 				compatible = "cache";