arm64: dts: qcom: sc7280: Fixup cpufreq domain info for cpu7
Subsystems (5)
Stable branch Device tree bindings Arm Qualcomm mailing list Arm Qualcomm support +1 more subsystems
PATCH 1/1 arm64: dts: qcom: sc7280: Fixup cpufreq domain info for cpu7
The SC7280 SoC supports a 4-Silver/3-Gold/1-Gold+ configuration and hence the cpu7 node should point to cpufreq domain 2 instead.
Fixes 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node")
Signed-off-by Sibi Sankar <[email protected]>
--- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm64/boot/dts/qcom/sc7280.dtsi +1 -1
@@ -200,7 +200,7 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_700>; - qcom,freq-domain = <&cpufreq_hw 1>; + qcom,freq-domain = <&cpufreq_hw 2>; #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache";
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Quoted 15 lines · Sibi Sankar
The SC7280 SoC supports a 4-Silver/3-Gold/1-Gold+ configuration and hence the cpu7 node should point to cpufreq domain 2 instead.
Fixes 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node")Signed-off-by Sibi Sankar <[email protected]>--- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)arch/arm64/boot/dts/qcom/sc7280.dtsi +0
-0
arch/arm64/boot/dts/qcom/sc7280.dtsi line 206
Quoted 8 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +1
-1@@ -200,7 +200,7 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_700>; - qcom,freq-domain = <&cpufreq_hw 1>; + qcom,freq-domain = <&cpufreq_hw 2>; #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache";
Reviewed-by Matthias Kaehlcke <[email protected]>
Quoting Sibi Sankar (2021-07-20 10:09:13)
Quoted 7 lines
The SC7280 SoC supports a 4-Silver/3-Gold/1-Gold+ configuration and hence the cpu7 node should point to cpufreq domain 2 instead.
Fixes 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node")Signed-off-by Sibi Sankar <[email protected]>---
Reviewed-by Stephen Boyd <[email protected]>