Add support for LPASS Core and Audio Clock for SC7280

PLL poll for lock detection can take more than 100us for certain type

of PLLs, thus update to 200us.

Signed-off-by Taniya Das <[email protected]>

---
 drivers/clk/qcom/clk-alpha-pll.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/clk/qcom/clk-alpha-pll.c +1 -1

index eaedcce..7cf6cfa 100644
@@ -204,7 +204,7 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
        if (ret)
                return ret;
 
-       for (count = 100; count > 0; count--) {
+       for (count = 200; count > 0; count--) {
                ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
                if (ret)

In the cases where the clock is required to be enabled before the genpd enable add support for the same.

Signed-off-by Taniya Das <[email protected]>

---
 drivers/clk/qcom/gdsc.c | 45 +++++++++++++++++++++++++++++++++++++++------
 drivers/clk/qcom/gdsc.h |  3 +++
 2 files changed, 42 insertions(+), 6 deletions(-)

drivers/clk/qcom/gdsc.c +0 -0

index 7e1dd8c..1caca32 100644
@@ -478,6 +499,18 @@ int gdsc_register(struct gdsc_desc *desc,
                        return PTR_ERR(scs[i]->rsupply);

drivers/clk/qcom/gdsc.c +4 -0

+               if (ret)
+                       return ret;
+       }
+
        data->num_domains = num;
        for (i = 0; i < num; i++) {
                if (!scs[i])

The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic properties that are needed in a device tree. Also add clock ids for LPASS core clocks and audio clock IDs for LPASS client to request for the clocks.

Signed-off-by Taniya Das <[email protected]>

---
 .../bindings/clock/qcom,sc7280-lpasscorecc.yaml    | 137 +++++++++++++++++++++
 .../dt-bindings/clock/qcom,lpassaudiocc-sc7280.h   |  43 +++++++
 .../dt-bindings/clock/qcom,lpasscorecc-sc7280.h    |  26 ++++
 3 files changed, 206 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
 create mode 100644 include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
 create mode 100644 include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h

The Low Power Audio subsystem core and audio clocks are required for Audio client to be able to request for the clocks and power domains.

Signed-off-by Taniya Das <[email protected]>

---
 drivers/clk/qcom/Kconfig               |   9 +
 drivers/clk/qcom/Makefile              |   1 +
 drivers/clk/qcom/lpassaudiocc-sc7280.c | 831 +++++++++++++++++++++++++++++++++
 drivers/clk/qcom/lpasscorecc-sc7280.c  | 491 +++++++++++++++++++
 4 files changed, 1332 insertions(+)
 create mode 100644 drivers/clk/qcom/lpassaudiocc-sc7280.c
 create mode 100644 drivers/clk/qcom/lpasscorecc-sc7280.c

drivers/clk/qcom/Kconfig +0 -0

index 74efc82..4dcabc6 100644

drivers/clk/qcom/Kconfig +6 -0

+       help
+         Support for the LPASS(Low Power Audio Subsystem) core and audio clock
+         controller on SC7280 devices.
+         Say Y if you want to use LPASS clocks and power domains of the LPASS
+         core clock controller.
+
 config SC_MSS_7180
        tristate "SC7180 Modem Clock Controller"
        select SC_GCC_7180

drivers/clk/qcom/Makefile +1 -0

index 1718c34..9e4b8e1 100644
@@ -69,6 +69,7 @@ obj-$(CONFIG_SC_GPUCC_7180) += gpucc-sc7180.o
 obj-$(CONFIG_SC_GPUCC_7280) += gpucc-sc7280.o
 obj-$(CONFIG_SC_LPASSCC_7280) += lpasscc-sc7280.o
 obj-$(CONFIG_SC_LPASS_CORECC_7180) += lpasscorecc-sc7180.o
+obj-$(CONFIG_SC_LPASS_CORECC_7280) += lpasscorecc-sc7280.o lpassaudiocc-sc7280.o
 obj-$(CONFIG_SC_MSS_7180) += mss-sc7180.o
 obj-$(CONFIG_SC_VIDEOCC_7180) += videocc-sc7180.o
 obj-$(CONFIG_SC_VIDEOCC_7280) += videocc-sc7280.o

drivers/clk/qcom/lpassaudiocc-sc7280.c new file +28 -0

new file mode 100644
index 0000000..52e7f8e
@@ -0,0 +1,831 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/pm_clock.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "common.h"
+#include "gdsc.h"
+
+enum {
+       P_BI_TCXO,

drivers/clk/qcom/lpassaudiocc-sc7280.c new file +10 -0

+       { 595200000, 3600000000, 0 },
+};
+
+/* 1128.96MHz configuration */
+static const struct alpha_pll_config lpass_audio_cc_pll_config = {
+       .l = 0x3a,
+       .alpha = 0xcccc,
+       .config_ctl_val = 0x08200920,
+       .config_ctl_hi_val = 0x05002001,
+       .config_ctl_hi1_val = 0x00000000,

drivers/clk/qcom/lpassaudiocc-sc7280.c new file +20 -0

+                       },
+                       .num_parents = 1,
+                       .ops = &clk_alpha_pll_zonda_ops,
+               },
+       },
+};
+
+static const struct clk_div_table post_div_table_lpass_audio_cc_pll_out_aux2[] = {
+       { 0x1, 2 },
+       { }
+};
+
+static struct clk_alpha_pll_postdiv lpass_audio_cc_pll_out_aux2 = {
+       .offset = 0x0,
+       .post_div_shift = 8,
+       .post_div_table = post_div_table_lpass_audio_cc_pll_out_aux2,
+       .num_post_div = ARRAY_SIZE(post_div_table_lpass_audio_cc_pll_out_aux2),
+       .width = 2,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
+       .clkr.hw.init = &(struct clk_init_data){

drivers/clk/qcom/lpassaudiocc-sc7280.c new file +3 -0

+       { 249600000, 2000000000, 0 },
+};
+

drivers/clk/qcom/lpasscorecc-sc7280.c new file +20 -0

new file mode 100644
index 0000000..812d9bd
@@ -0,0 +1,491 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/pm_clock.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"

drivers/clk/qcom/lpasscorecc-sc7280.c new file +50 -0

+       .gdscr = 0x0,
+       .pd = {
+               .name = "lpass_core_cc_lpass_core_hm_gdsc",
+       },
+       .pwrsts = PWRSTS_OFF_ON,
+       .flags = RETAIN_FF_ENABLE,
+       .clk_name = "iface",
+};
+
+static struct clk_regmap *lpass_core_cc_sc7280_clocks[] = {
+       [LPASS_CORE_CC_CORE_CLK] = &lpass_core_cc_core_clk.clkr,
+       [LPASS_CORE_CC_CORE_CLK_SRC] = &lpass_core_cc_core_clk_src.clkr,
+       [LPASS_CORE_CC_DIG_PLL] = &lpass_core_cc_dig_pll.clkr,
+       [LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC] =
+               &lpass_core_cc_dig_pll_out_main_div_clk_src.clkr,
+       [LPASS_CORE_CC_DIG_PLL_OUT_ODD] = &lpass_core_cc_dig_pll_out_odd.clkr,
+       [LPASS_CORE_CC_EXT_IF0_CLK_SRC] = &lpass_core_cc_ext_if0_clk_src.clkr,
+       [LPASS_CORE_CC_EXT_IF0_IBIT_CLK] = &lpass_core_cc_ext_if0_ibit_clk.clkr,
+       [LPASS_CORE_CC_EXT_IF1_CLK_SRC] = &lpass_core_cc_ext_if1_clk_src.clkr,
+       [LPASS_CORE_CC_EXT_IF1_IBIT_CLK] = &lpass_core_cc_ext_if1_ibit_clk.clkr,
+       [LPASS_CORE_CC_LPM_CORE_CLK] = &lpass_core_cc_lpm_core_clk.clkr,
+       [LPASS_CORE_CC_LPM_MEM0_CORE_CLK] = &lpass_core_cc_lpm_mem0_core_clk.clkr,
+       [LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK] = &lpass_core_cc_sysnoc_mport_core_clk.clkr,
+};
+
+static struct regmap_config lpass_core_cc_sc7280_regmap_config = {
+       .reg_bits = 32,
+       .reg_stride = 4,
+       .val_bits = 32,
+       .fast_io = true,
+};
+
+static const struct qcom_cc_desc lpass_core_cc_sc7280_desc = {
+       .config = &lpass_core_cc_sc7280_regmap_config,
+       .clks = lpass_core_cc_sc7280_clocks,
+       .num_clks = ARRAY_SIZE(lpass_core_cc_sc7280_clocks),
+};
+
+static const struct of_device_id lpass_core_cc_sc7280_match_table[] = {
+       { .compatible = "qcom,sc7280-lpasscorecc" },
+       { }
+};
+MODULE_DEVICE_TABLE(of, lpass_core_cc_sc7280_match_table);
+
+static struct gdsc *lpass_core_hm_sc7280_gdscs[] = {
+       [LPASS_CORE_CC_LPASS_CORE_HM_GDSC] = &lpass_core_cc_lpass_core_hm_gdsc,
+};
+
+static const struct qcom_cc_desc lpass_core_hm_sc7280_desc = {
+       .config = &lpass_core_cc_sc7280_regmap_config,

drivers/clk/qcom/lpasscorecc-sc7280.c new file +76 -0

+{
+       pm_clk_destroy(data);
+}
+
+static int lpass_create_pm_clks(struct platform_device *pdev)
+{
+       int ret;
+
+       pm_runtime_use_autosuspend(&pdev->dev);
+       pm_runtime_set_autosuspend_delay(&pdev->dev, 100);
+       pm_runtime_enable(&pdev->dev);
+
+       ret = devm_add_action_or_reset(&pdev->dev, lpass_pm_runtime_disable, &pdev->dev);
+       if (ret)
+               return ret;
+
+       ret = pm_clk_create(&pdev->dev);
+       if (ret)
+               return ret;
+       ret = devm_add_action_or_reset(&pdev->dev, lpass_pm_clk_destroy, &pdev->dev);
+       if (ret)
+               return ret;
+
+       ret = pm_clk_add(&pdev->dev, "iface");
+       if (ret < 0)
+               dev_err(&pdev->dev, "failed to acquire iface clock\n");
+
+       return ret;
+}
+
+static int lpass_core_cc_sc7280_probe(struct platform_device *pdev)
+{
+       struct regmap *regmap;
+       int ret;
+
+       ret = lpass_create_pm_clks(pdev);
+       if (ret)
+               return ret;
+
+       regmap = qcom_cc_map(pdev, &lpass_core_cc_sc7280_desc);
+       if (IS_ERR(regmap))
+               return PTR_ERR(regmap);
+
+       clk_lucid_pll_configure(&lpass_core_cc_dig_pll, regmap, &lpass_core_cc_dig_pll_config);
+
+       ret = qcom_cc_really_probe(pdev, &lpass_core_cc_sc7280_desc, regmap);
+       if (ret) {
+               dev_err(&pdev->dev, "Failed to register LPASS CORE CC clocks\n");
+               return ret;
+       }
+
+       pm_runtime_mark_last_busy(&pdev->dev);
+       pm_runtime_put_autosuspend(&pdev->dev);
+
+       return ret;
+}
+
+static const struct dev_pm_ops lpass_core_cc_pm_ops = {
+       SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
+};
+
+static struct platform_driver lpass_core_cc_sc7280_driver = {
+       .probe = lpass_core_cc_sc7280_probe,
+       .driver = {
+               .name = "lpass_core_cc-sc7280",
+               .of_match_table = lpass_core_cc_sc7280_match_table,
+               .pm = &lpass_core_cc_pm_ops,
+       },
+};
+
+static int lpass_hm_core_probe(struct platform_device *pdev)
+{
+       const struct qcom_cc_desc *desc;
+       int ret;
+
+       lpass_core_cc_sc7280_regmap_config.name = "lpass_hm_core";

drivers/clk/qcom/lpasscorecc-sc7280.c new file +4 -0

+       { }
+};
+MODULE_DEVICE_TABLE(of, lpass_hm_sc7280_match_table);
+