memory: tegra: Add MC channels and error logging
v7 cover memory: tegra: Add MC channels and error logging
From tegra186 onward, memory controllers support multiple channels. Add memory controller channels in device tree and add support to map address spaces of these channels in tegra MC driver.
When memory controller interrupt occurs, registers from these channels are required to be read in order to get error information. Add error logging support from tegra186 onward for memory controller interrupts.
Ashish Mhetre (4):
memory: tegra: Add memory controller channels support
memory: tegra: Add MC error logging on tegra186 onward
dt-bindings: memory: Update reg/reg-names validation
arm64: tegra: Add memory controller channels
---
Changes in v7:
- Updated reg-names as per comments on v6
- Removed use of of_property_count_elems_of_size() and used broadcast reg for checking whether old or new DTS is getting used
- Updated variable names as per comments on v6
- Added helper function for getting global_intstatus bit from channel
- Used to_platform_device() instead of passing pdev pointer to map_regs()
- Allocated ch_regs at runtime
- Updated DT binding documentation to add validation for reg-names
Changes in v6:
- Added reg-names for each reg item of memory controller node
- Added logging for interrupts on multiple memory controller channels
- Added clearing interrupt support for global intstatus
- Updated DT binding documentation to work with existing DTS as well
- Updated function to get MC channels
- Updated variable names
Changes in v5:
- Updated patch sequence such that driver patches are before DT patches
- Fixed DT ABI break from v4
- Fixed smatch bug
- Updated description in DT binding documentation
- Updated variable names
Changes in v4:
- Added memory controller channels support
- Added newlines after every break statement of all switch cases
- Fixed compile error with W=1 build
- Fixed the interrupt mask bit logic
Changes in v3:
- Removed unnecessary ifdefs
- Grouped newly added MC registers with existing MC registers
- Removed unnecessary initialization of variables
- Updated code to use newly added field 'has_addr_hi_reg' instead of ifdefs
Changes in v2:
- Updated patch subject and commit message
- Removed separate irq handlers
- Updated tegra30_mc_handle_irq to be used for tegra186 onwards as well
.../nvidia,tegra186-mc.yaml | 80 +++++++++- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 8 +- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 24 ++- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 24 ++- drivers/memory/tegra/mc.c | 140 ++++++++++++++++-- drivers/memory/tegra/mc.h | 37 ++++- drivers/memory/tegra/tegra186.c | 47 ++++++ drivers/memory/tegra/tegra194.c | 9 ++ drivers/memory/tegra/tegra234.c | 8 + include/soc/tegra/mc.h | 7 + 10 files changed, 354 insertions(+), 30 deletions(-)
Signature · 1 line
2.17.1
PATCH v7 1/4 memory: tegra: Add memory controller channels support
From tegra186 onwards, memory controller support multiple channels. Add support for mapping address spaces of these channels. Make sure that number of channels are as expected on each SOC. During error interrupts from memory controller, appropriate registers from these channels need to be accessed for logging error info.
--- drivers/memory/tegra/mc.c | 6 ++++++ drivers/memory/tegra/tegra186.c | 33 +++++++++++++++++++++++++++++++++ drivers/memory/tegra/tegra194.c | 1 + drivers/memory/tegra/tegra234.c | 1 + include/soc/tegra/mc.h | 4 ++++ 5 files changed, 45 insertions(+)
drivers/memory/tegra/mc.c +6 -0
@@ -749,6 +749,12 @@ static int tegra_mc_probe(struct platform_device *pdev)if (IS_ERR (mc->regs))return PTR_ERR (mc->regs); +if (mc->soc->ops && mc->soc->ops->map_regs) { + err = mc->soc->ops->map_regs (mc); +if (err <0 ) +return err; + } + mc->debugfs.root =debugfs_create_dir ("mc" ,NULL );if (mc->soc->ops && mc->soc->ops->probe) {
drivers/memory/tegra/tegra186.c +33 -0
@@ -139,11 +139,43 @@ static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)return 0 ; } +static int tegra186_mc_map_regs (struct tegra_mc *mc) +{ +struct platform_device *pdev =to_platform_device (mc->dev); +int i; + + mc->bcast_ch_regs =devm_platform_ioremap_resource_byname (pdev,"broadcast" ); +if (IS_ERR (mc->bcast_ch_regs)) { +if (PTR_ERR (mc->bcast_ch_regs) == -EINVAL ) { +dev_warn (&pdev->dev,"Broadcast channel is missing, please update your device-tree\n" ); +return 0 ; + } +return PTR_ERR (mc->bcast_ch_regs); + } + + mc->ch_regs =devm_kcalloc (mc->dev, mc->soc->num_channels, +sizeof (void __iomem *),GFP_KERNEL ); +if (!mc->ch_regs) +return -ENOMEM ; + +for (i =0 ; i < mc->soc->num_channels; i++) { +char name[4 ]; + +sprintf (name,"ch%u" , i); + mc->ch_regs[i] =devm_platform_ioremap_resource_byname (pdev, name); +if (IS_ERR (mc->ch_regs[i])) +return PTR_ERR (mc->ch_regs[i]); + } + +return 0 ; +} +const struct tegra_mc_ops tegra186_mc_ops = { .probe = tegra186_mc_probe, .remove = tegra186_mc_remove, .resume = tegra186_mc_resume, .probe_device = tegra186_mc_probe_device, + .map_regs = tegra186_mc_map_regs, };#if defined(CONFIG_ARCH_TEGRA_186_SOC )
@@ -875,6 +907,7 @@ const struct tegra_mc_soc tegra186_mc_soc = { .num_clients = ARRAY_SIZE(tegra186_mc_clients), .clients = tegra186_mc_clients, .num_address_bits = 40, + .num_channels = 4, .ops = &tegra186_mc_ops, };#endif
drivers/memory/tegra/tegra194.c +1 -0
@@ -1347,5 +1347,6 @@ const struct tegra_mc_soc tegra194_mc_soc = { .num_clients = ARRAY_SIZE(tegra194_mc_clients), .clients = tegra194_mc_clients, .num_address_bits = 40, + .num_channels = 16, .ops = &tegra186_mc_ops, };
drivers/memory/tegra/tegra234.c +1 -0
@@ -97,5 +97,6 @@ const struct tegra_mc_soc tegra234_mc_soc = { .num_clients = ARRAY_SIZE(tegra234_mc_clients), .clients = tegra234_mc_clients, .num_address_bits = 40, + .num_channels = 16, .ops = &tegra186_mc_ops, };
include/soc/tegra/mc.h +4 -0
@@ -181,6 +181,7 @@ struct tegra_mc_ops {int (*resume)(struct tegra_mc *mc);irqreturn_t (*handle_irq)(int irq,void *data);int (*probe_device)(struct tegra_mc *mc,struct device *dev); +int (*map_regs)(struct tegra_mc *mc); };struct tegra_mc_soc {
@@ -194,6 +195,7 @@ struct tegra_mc_soc {unsigned int atom_size;u8 client_id_mask; +u8 num_channels;const struct tegra_smmu_soc *smmu;
@@ -212,6 +214,8 @@ struct tegra_mc {struct tegra_smmu *smmu;struct gart_device *gart;void __iomem *regs; +void __iomem *bcast_ch_regs; +void __iomem **ch_regs;struct clk *clk;int irq;
Signature · 1 line
2.17.1
Re: [Patch v7 1/4] memory: tegra: Add memory controller channels support
drivers/memory/tegra/tegra186.c static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev) · line 150
Quoted 9 lines · Ashish Mhetre
drivers/memory/tegra/tegra186.c +9
-0+static int tegra186_mc_map_regs (struct tegra_mc *mc) +{ +struct platform_device *pdev =to_platform_device (mc->dev); +int i; + + mc->bcast_ch_regs =devm_platform_ioremap_resource_byname (pdev,"broadcast" ); +if (IS_ERR (mc->bcast_ch_regs)) { +if (PTR_ERR (mc->bcast_ch_regs) == -EINVAL ) { +dev_warn (&pdev->dev,"Broadcast channel is missing, please update your device-tree\n" );
Set mc->bcast_ch_regs=NULL on error.
Re: [Patch v7 1/4] memory: tegra: Add memory controller channels support
Quoted 4 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
On 4/13/22 12:40, Ashish Mhetre wrote:
Quoted 11 lines
drivers/memory/tegra/tegra186.c static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev) · line 150
Quoted 9 lines
drivers/memory/tegra/tegra186.c +9
-0+static int tegra186_mc_map_regs (struct tegra_mc *mc) +{ +struct platform_device *pdev =to_platform_device (mc->dev); +int i; + + mc->bcast_ch_regs =devm_platform_ioremap_resource_byname (pdev,"broadcast" ); +if (IS_ERR (mc->bcast_ch_regs)) { +if (PTR_ERR (mc->bcast_ch_regs) == -EINVAL ) { +dev_warn (&pdev->dev,"Broadcast channel is missing, please update your device-tree\n" );Set mc->bcast_ch_regs=NULL on error.
It's not really necessary. If mc->bcast_ch_regs == -EINVAL, then interrupts won't occur at all. I have added explanation in patch 2.
Re: [Patch v7 1/4] memory: tegra: Add memory controller channels support
In reply to Ashish MhetreQuoted 14 lines · Ashish Mhetre
drivers/memory/tegra/tegra186.c +13
-0+static int tegra186_mc_map_regs (struct tegra_mc *mc) +{ +struct platform_device *pdev =to_platform_device (mc->dev); +int i; + + mc->bcast_ch_regs =devm_platform_ioremap_resource_byname (pdev,"broadcast" ); +if (IS_ERR (mc->bcast_ch_regs)) { +if (PTR_ERR (mc->bcast_ch_regs) == -EINVAL ) { +dev_warn (&pdev->dev,"Broadcast channel is missing, please update your device-tree\n" ); +return 0 ; + } +return PTR_ERR (mc->bcast_ch_regs); + }
drivers/memory/tegra/tegra186.c static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev) · line 164
Quoted 10 lines
drivers/memory/tegra/tegra186.c +10
-0+ + mc->ch_regs =devm_kcalloc (mc->dev, mc->soc->num_channels, +sizeof (void __iomem *),GFP_KERNEL ); +if (!mc->ch_regs) +return -ENOMEM ; + +for (i =0 ; i < mc->soc->num_channels; i++) { +char name[4 ]; + +sprintf (name,"ch%u" , i);
name[5], otherwise you corrupting stack. Use snprintf(name, sizeof(name)).
PATCH v7 2/4 memory: tegra: Add MC error logging on tegra186 onward
In reply to Ashish MhetreAdd support for reading MC_GLOBAL_INTSTATUS register which points to the memory controller channels on which interrupts have occurred. Add helper function 'global_intstatus_to_channel' which returns the channel which should be used to get the information of interrupts. Remove static from tegra30_mc_handle_irq and use it as interrupt handler for MC interrupts on tegra186, tegra194 and tegra234 to log the errors. Add error specific MC status and address register bits and use them on tegra186, tegra194 and tegra234.
Add error logging for generalized carveout interrupt on tegra186, tegra194 and tegra234.
Add error logging for route sanity interrupt on tegra194 an tegra234. Add register for higher bits of error address which is available on tegra194 and tegra234.
Add a boolean variable 'has_addr_hi_reg' in tegra_mc_soc struture which will be true if soc has register for higher bits of memory controller error address. Set it true for tegra194 and tegra234.
Add helper function 'mc_channel_to_global_intstatus' which returns the bit of MC_GLOBAL_INSTATUS corresponding to channel of which interrupts are logged and use it to clear that interrupt channel.
--- drivers/memory/tegra/mc.c | 134 ++++++++++++++++++++++++++++---- drivers/memory/tegra/mc.h | 37 ++++++++- drivers/memory/tegra/tegra186.c | 9 +++ drivers/memory/tegra/tegra194.c | 8 ++ drivers/memory/tegra/tegra234.c | 7 ++ include/soc/tegra/mc.h | 3 + 6 files changed, 181 insertions(+), 17 deletions(-)
drivers/memory/tegra/mc.c +118 -16
@@ -508,14 +508,54 @@ int tegra30_mc_probe(struct tegra_mc *mc)return 0 ; } -static irqreturn_t tegra30_mc_handle_irq (int irq,void *data) +const struct tegra_mc_ops tegra30_mc_ops = { + .probe = tegra30_mc_probe, + .handle_irq = tegra30_mc_handle_irq, +}; +#endif + +static int global_intstatus_to_channel (const struct tegra_mc *mc,u32 status, +unsigned int *mc_channel) +{ +if ((status & mc->soc->ch_intmask) ==0 ) +return -EINVAL ; + + *mc_channel =__ffs ((status & mc->soc->ch_intmask) >> + mc->soc->global_intstatus_channel_shift); + +return 0 ; +} + +static u32 mc_channel_to_global_intstatus (const struct tegra_mc *mc, +unsigned int channel) +{ +return BIT (channel) << mc->soc->global_intstatus_channel_shift; +} + +irqreturn_t tegra30_mc_handle_irq (int irq,void *data) {struct tegra_mc *mc = data; +unsigned int bit, channel;unsigned long status; -unsigned int bit; -/* mask all interrupts to avoid flooding */ - status =mc_readl (mc,MC_INTSTATUS ) & mc->soc->intmask; +if (mc->soc->num_channels) { +u32 global_status; +int err; + + global_status =mc_ch_readl (mc,MC_BROADCAST_CHANNEL ,MC_GLOBAL_INTSTATUS ); + err =global_intstatus_to_channel (mc, global_status, &channel); +if (err <0 ) { +dev_err_ratelimited (mc->dev,"unknown interrupt channel 0x%08x\n" , + global_status); +return IRQ_NONE ; + } + +/* mask all interrupts to avoid flooding */ + status =mc_ch_readl (mc, channel,MC_INTSTATUS ) & mc->soc->intmask; + }else { + status =mc_readl (mc,MC_INTSTATUS ) & mc->soc->intmask; + } +if (!status)return IRQ_NONE ;
@@ -523,18 +563,70 @@ static irqreturn_t tegra30_mc_handle_irq(int irq, void *data)const char *error = tegra_mc_status_names[bit] ?:"unknown" ;const char *client ="unknown" , *desc;const char *direction, *secure; +u32 status_reg, addr_reg; +u32 intmask =BIT (bit);phys_addr_t addr =0 ; +#ifdef CONFIG_PHYS_ADDR_T_64BIT +u32 addr_hi_reg =0 ; +#endif unsigned int i;char perm[7 ];u8 id, type;u32 value; - value =mc_readl (mc,MC_ERR_STATUS ); +switch (intmask) { +case MC_INT_DECERR_VPR : + status_reg =MC_ERR_VPR_STATUS ; + addr_reg =MC_ERR_VPR_ADR ; +break ; + +case MC_INT_SECERR_SEC : + status_reg =MC_ERR_SEC_STATUS ; + addr_reg =MC_ERR_SEC_ADR ; +break ; + +case MC_INT_DECERR_MTS : + status_reg =MC_ERR_MTS_STATUS ; + addr_reg =MC_ERR_MTS_ADR ; +break ; + +case MC_INT_DECERR_GENERALIZED_CARVEOUT : + status_reg =MC_ERR_GENERALIZED_CARVEOUT_STATUS ; + addr_reg =MC_ERR_GENERALIZED_CARVEOUT_ADR ; +break ; + +case MC_INT_DECERR_ROUTE_SANITY : + status_reg =MC_ERR_ROUTE_SANITY_STATUS ; + addr_reg =MC_ERR_ROUTE_SANITY_ADR ; +break ; + +default : + status_reg =MC_ERR_STATUS ; + addr_reg =MC_ERR_ADR ; + +#ifdef CONFIG_PHYS_ADDR_T_64BIT +if (mc->soc->has_addr_hi_reg) + addr_hi_reg =MC_ERR_ADR_HI ; +#endif +break ; + } + +if (mc->soc->num_channels) + value =mc_ch_readl (mc, channel, status_reg); +else + value =mc_readl (mc, status_reg);#ifdef CONFIG_PHYS_ADDR_T_64BIT if (mc->soc->num_address_bits >32 ) { - addr = ((value >>MC_ERR_STATUS_ADR_HI_SHIFT ) & -MC_ERR_STATUS_ADR_HI_MASK ); +if (addr_hi_reg) { +if (mc->soc->num_channels) + addr =mc_ch_readl (mc, channel, addr_hi_reg); +else + addr =mc_readl (mc, addr_hi_reg); + }else { + addr = ((value >>MC_ERR_STATUS_ADR_HI_SHIFT ) & +MC_ERR_STATUS_ADR_HI_MASK ); + } addr <<=32 ; }#endif
@@ -591,7 +683,10 @@ static irqreturn_t tegra30_mc_handle_irq(int irq, void *data)break ; } - value =mc_readl (mc,MC_ERR_ADR ); +if (mc->soc->num_channels) + value =mc_ch_readl (mc, channel, addr_reg); +else + value =mc_readl (mc, addr_reg); addr |= value; dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n",
@@ -600,17 +695,18 @@ static irqreturn_t tegra30_mc_handle_irq(int irq, void *data) }/* clear interrupts */ -mc_writel (mc, status,MC_INTSTATUS ); +if (mc->soc->num_channels) { +mc_ch_writel (mc, channel, status,MC_INTSTATUS ); +mc_ch_writel (mc,MC_BROADCAST_CHANNEL , +mc_channel_to_global_intstatus (mc, channel), +MC_GLOBAL_INTSTATUS ); + }else { +mc_writel (mc, status,MC_INTSTATUS ); + }return IRQ_HANDLED ; } -const struct tegra_mc_ops tegra30_mc_ops = { - .probe = tegra30_mc_probe, - .handle_irq = tegra30_mc_handle_irq, -}; -#endif -const char *const tegra_mc_status_names[32 ] = { [1 ] ="External interrupt" , [6 ] ="EMEM address decode error" ,
@@ -622,6 +718,8 @@ const char *const tegra_mc_status_names[32] = { [12] = "VPR violation", [13] = "Secure carveout violation", [16] = "MTS carveout violation", + [17] = "Generalized carveout violation", + [20] = "Route Sanity error", };const char *const tegra_mc_error_names[8 ] = {
@@ -770,7 +868,11 @@ static int tegra_mc_probe(struct platform_device *pdev)WARN (!mc->soc->client_id_mask,"missing client ID mask for this SoC\n" ); -mc_writel (mc, mc->soc->intmask,MC_INTMASK ); +if (mc->soc->num_channels && !IS_ERR (mc->bcast_ch_regs)) +mc_ch_writel (mc,MC_BROADCAST_CHANNEL , mc->soc->intmask, +MC_INTMASK ); +else +mc_writel (mc, mc->soc->intmask,MC_INTMASK ); err =devm_request_irq (&pdev->dev, mc->irq, mc->soc->ops->handle_irq,0 ,dev_name (&pdev->dev), mc);
drivers/memory/tegra/mc.h +36 -1
@@ -43,7 +43,21 @@#define MC_EMEM_ARB_OVERRIDE 0xe8#define MC_TIMING_CONTROL_DBG 0xf8#define MC_TIMING_CONTROL 0xfc - +#define MC_ERR_VPR_STATUS 0x654 +#define MC_ERR_VPR_ADR 0x658 +#define MC_ERR_SEC_STATUS 0x67c +#define MC_ERR_SEC_ADR 0x680 +#define MC_ERR_MTS_STATUS 0x9b0 +#define MC_ERR_MTS_ADR 0x9b4 +#define MC_ERR_ROUTE_SANITY_STATUS 0x9c0 +#define MC_ERR_ROUTE_SANITY_ADR 0x9c4 +#define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00 +#define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04 +#define MC_GLOBAL_INTSTATUS 0xf24 +#define MC_ERR_ADR_HI 0x11fc + +#define MC_INT_DECERR_ROUTE_SANITY BIT(20) +#define MC_INT_DECERR_GENERALIZED_CARVEOUT BIT(17)#define MC_INT_DECERR_MTS BIT(16)#define MC_INT_SECERR_SEC BIT(13)#define MC_INT_DECERR_VPR BIT(12)
@@ -78,6 +92,8 @@#define MC_TIMING_UPDATE BIT(0) +#define MC_BROADCAST_CHANNEL ~0 +static inline u32 tegra_mc_scale_percents (u64 val,unsigned int percents) { val = val * percents;
@@ -92,6 +108,24 @@ icc_provider_to_tegra_mc(struct icc_provider *provider) return container_of(provider, struct tegra_mc, provider); } +static inline u32 mc_ch_readl (const struct tegra_mc *mc,int ch, +unsigned long offset) +{ +if (ch ==MC_BROADCAST_CHANNEL ) +return readl_relaxed (mc->bcast_ch_regs + offset); + +return readl_relaxed (mc->ch_regs[ch] + offset); +} + +static inline void mc_ch_writel (const struct tegra_mc *mc,int ch, +u32 value,unsigned long offset) +{ +if (ch ==MC_BROADCAST_CHANNEL ) +writel_relaxed (value, mc->bcast_ch_regs + offset); +else +writel_relaxed (value, mc->ch_regs[ch] + offset); +} +static inline u32 mc_readl (const struct tegra_mc *mc,unsigned long offset) {return readl_relaxed (mc->regs + offset);
@@ -156,6 +190,7 @@ extern const struct tegra_mc_ops tegra30_mc_ops;extern const struct tegra_mc_ops tegra186_mc_ops;#endif +irqreturn_t tegra30_mc_handle_irq (int irq,void *data);extern const char *const tegra_mc_status_names[32 ];extern const char *const tegra_mc_error_names[8 ];
drivers/memory/tegra/tegra186.c +9 -0
@@ -16,6 +16,8 @@#include <dt-bindings/memory/tegra186-mc.h> #endif +#include "mc.h" +#define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0)#define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16)#define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8)
@@ -176,6 +178,7 @@ const struct tegra_mc_ops tegra186_mc_ops = { .resume = tegra186_mc_resume, .probe_device = tegra186_mc_probe_device, .map_regs = tegra186_mc_map_regs, + .handle_irq = tegra30_mc_handle_irq, };#if defined(CONFIG_ARCH_TEGRA_186_SOC )
@@ -908,6 +911,12 @@ const struct tegra_mc_soc tegra186_mc_soc = { .clients = tegra186_mc_clients, .num_address_bits = 40, .num_channels = 4, + .client_id_mask = 0xff, + .intmask =MC_INT_DECERR_GENERALIZED_CARVEOUT |MC_INT_DECERR_MTS | +MC_INT_SECERR_SEC |MC_INT_DECERR_VPR | + MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, .ops = &tegra186_mc_ops, + .ch_intmask = 0x0000000f, + .global_intstatus_channel_shift = 0, };#endif
drivers/memory/tegra/tegra194.c +8 -0
@@ -1348,5 +1348,13 @@ const struct tegra_mc_soc tegra194_mc_soc = { .clients = tegra194_mc_clients, .num_address_bits = 40, .num_channels = 16, + .client_id_mask = 0xff, + .intmask =MC_INT_DECERR_ROUTE_SANITY | +MC_INT_DECERR_GENERALIZED_CARVEOUT |MC_INT_DECERR_MTS | +MC_INT_SECERR_SEC |MC_INT_DECERR_VPR | + MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, + .has_addr_hi_reg = true, .ops = &tegra186_mc_ops, + .ch_intmask = 0x00000f00, + .global_intstatus_channel_shift = 8, };
drivers/memory/tegra/tegra234.c +7 -0
@@ -98,5 +98,12 @@ const struct tegra_mc_soc tegra234_mc_soc = { .clients = tegra234_mc_clients, .num_address_bits = 40, .num_channels = 16, + .intmask =MC_INT_DECERR_ROUTE_SANITY | +MC_INT_DECERR_GENERALIZED_CARVEOUT |MC_INT_DECERR_MTS | +MC_INT_SECERR_SEC |MC_INT_DECERR_VPR | + MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, + .has_addr_hi_reg = true, .ops = &tegra186_mc_ops, + .ch_intmask = 0x0000ff00, + .global_intstatus_channel_shift = 8, };
include/soc/tegra/mc.h +3 -0
@@ -200,6 +200,9 @@ struct tegra_mc_soc {const struct tegra_smmu_soc *smmu;u32 intmask; +u32 ch_intmask; +u32 global_intstatus_channel_shift; +bool has_addr_hi_reg;const struct tegra_mc_reset_ops *reset_ops;const struct tegra_mc_reset *resets;
Signature · 1 line
2.17.1
Re: [Patch v7 2/4] memory: tegra: Add MC error logging on tegra186 onward
Quoted 4 lines · Ashish Mhetre
drivers/memory/tegra/mc.c +2
-0+irqreturn_t tegra30_mc_handle_irq (int irq,void *data) {struct tegra_mc *mc = data; +unsigned int bit, channel;
drivers/memory/tegra/mc.c int tegra30_mc_probe(struct tegra_mc *mc) · line 545
Quoted 10 lines
drivers/memory/tegra/mc.c +5
-3unsigned long status; -unsigned int bit; -/* mask all interrupts to avoid flooding */ - status =mc_readl (mc,MC_INTSTATUS ) & mc->soc->intmask; +if (mc->soc->num_channels) { +u32 global_status; +int err; + + global_status =mc_ch_readl (mc,MC_BROADCAST_CHANNEL ,MC_GLOBAL_INTSTATUS );
This will crash if mc->bcast_ch_regs = ERR_PTR(-EINVAL) for older dtbs.
Re: [Patch v7 2/4] memory: tegra: Add MC error logging on tegra186 onward
Quoted 11 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
Quoted 7 lines · Ashish Mhetre
drivers/memory/tegra/mc.c +2
-1+irqreturn_t tegra30_mc_handle_irq (int irq,void *data) {struct tegra_mc *mc = data; +unsigned int bit, channel;unsigned long status; -unsigned int bit;
Quoted 9 lines
drivers/memory/tegra/mc.c int tegra30_mc_probe(struct tegra_mc *mc) · line 545
Quoted 7 lines
drivers/memory/tegra/mc.c +5
-2-/* mask all interrupts to avoid flooding */ - status =mc_readl (mc,MC_INTSTATUS ) & mc->soc->intmask; +if (mc->soc->num_channels) { +u32 global_status; +int err; + + global_status =mc_ch_readl (mc,MC_BROADCAST_CHANNEL ,MC_GLOBAL_INTSTATUS );This will crash if
mc->bcast_ch_regs=ERR_PTR(-EINVAL)for older dtbs.
Actually interrupts won't occur till we write MC_INTMASK register from broadcast channel with appropriate intmask value. I have added check in tegra_mc_probe() while registering irq which will write MC_INTMASK from broadcast only when mc->bcast_ch_regs is initialized i.e. !IS_ERR(mc->bcast_ch_regs).
So interrupt handler won't be triggered at all if mc->bcast_ch_regs = ERR_PTR(-EINVAL).
Re: [Patch v7 2/4] memory: tegra: Add MC error logging on tegra186 onward
Quoted 25 lines · Ashish Mhetre
Quoted 11 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
Quoted 7 lines · Ashish Mhetre
+irqreturn_t
tegra30_mc_handle_irq(int irq, void *data){
structtegra_mc*mc = data;
+ unsigned int bit, channel;
unsigned long status;
- unsigned int bit;Quoted 10 lines
Quoted 8 lines
- /* mask all interrupts to avoid flooding */
- status =mc_readl(mc, MC_INTSTATUS)&mc->soc->intmask; + if (mc->soc->num_channels) {
+ u32global_status;
+ int err;
+
+global_status=mc_ch_readl(mc, MC_BROADCAST_CHANNEL, MC_GLOBAL_INTSTATUS);This will crash if
mc->bcast_ch_regs=ERR_PTR(-EINVAL)for older dtbs.
Quoted 8 lines
Actually interrupts won't occur till we write
MC_INTMASKregister from broadcast channel with appropriate intmask value. I have added check integra_mc_probe()while registering irq which will writeMC_INTMASKfrom broadcast only whenmc->bcast_ch_regsis initialized i.e. !IS_ERR(mc->bcast_ch_regs).
So interrupt handler won't be triggered at all ifmc->bcast_ch_regs=ERR_PTR(-EINVAL).
Should be cleaner to set mc->bcast_ch_regs to NULL anyways. The ERR_PTR doesn't add much value and only makes code less readable.
Re: [Patch v7 2/4] memory: tegra: Add MC error logging on tegra186 onward
In reply to Ashish Mhetredrivers/memory/tegra/mc.h icc_provider_to_tegra_mc(struct icc_provider *provider) · line 113
Quoted 3 lines · Ashish Mhetre
drivers/memory/tegra/mc.h +3
-0+static inline u32 mc_ch_readl (const struct tegra_mc *mc,int ch, +unsigned long offset) +{
return 0 if mc->bcast_ch_regs==NULL
drivers/memory/tegra/mc.h icc_provider_to_tegra_mc(struct icc_provider *provider) · line 122
Quoted 9 lines
drivers/memory/tegra/mc.h +9
-0+if (ch ==MC_BROADCAST_CHANNEL ) +return readl_relaxed (mc->bcast_ch_regs + offset); + +return readl_relaxed (mc->ch_regs[ch] + offset); +} + +static inline void mc_ch_writel (const struct tegra_mc *mc,int ch, +u32 value,unsigned long offset) +{
return if mc->bcast_ch_regs==NULL
Quoted 5 lines
drivers/memory/tegra/mc.h +5
-0+if (ch ==MC_BROADCAST_CHANNEL ) +writel_relaxed (value, mc->bcast_ch_regs + offset); +else +writel_relaxed (value, mc->ch_regs[ch] + offset); +}
Re: [Patch v7 2/4] memory: tegra: Add MC error logging on tegra186 onward
In reply to Ashish Mhetredrivers/memory/tegra/mc.c int tegra30_mc_probe(struct tegra_mc *mc) · line 518
Quoted 2 lines · Ashish Mhetre
drivers/memory/tegra/mc.c +2
-0+static int global_intstatus_to_channel (const struct tegra_mc *mc,u32 status, +unsigned int *mc_channel)
Add "mc_" prefix
PATCH v7 3/4 dt-bindings: memory: Update reg/reg-names validation
In reply to Ashish MhetreFrom tegra186 onwards, memory controller support multiple channels. Reg items are updated with address and size of these channels. Tegra186 has overall 5 memory controller channels. Tegra194 and tegra234 have overall 17 memory controller channels each.
There is 1 reg item for memory controller stream-id registers. So update the reg maxItems to 18 in tegra186 devicetree documentation. Also update validation for reg-names added for these corresponding reg items.
--- .../nvidia,tegra186-mc.yaml | 80 +++++++++++++++++-- 1 file changed, 74 insertions(+), 6 deletions(-)
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +74 -6
@@ -34,8 +34,12 @@ properties: - nvidia,tegra234-mc reg: - minItems: 1 - maxItems: 3 + minItems: 6 + maxItems: 18 + + reg-names: + minItems: 6 + maxItems: 18 interrupts: items:
@@ -142,7 +146,18 @@ allOf: then: properties: reg: - maxItems: 1 + maxItems: 6 + description: 5 memory controller channels and 1 for stream-id registers + + reg-names: + maxItems: 6 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 - if: properties:
@@ -151,7 +166,30 @@ allOf: then: properties: reg: - minItems: 3 + minItems: 18 + description: 17 memory controller channels and 1 for stream-id registers + + reg-names: + minItems: 18 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + - const: ch8 + - const: ch9 + - const: ch10 + - const: ch11 + - const: ch12 + - const: ch13 + - const: ch14 + - const: ch15 - if: properties:
@@ -160,13 +198,37 @@ allOf: then: properties: reg: - minItems: 3 + minItems: 18 + description: 17 memory controller channels and 1 for stream-id registers + + reg-names: + minItems: 18 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + - const: ch8 + - const: ch9 + - const: ch10 + - const: ch11 + - const: ch12 + - const: ch13 + - const: ch14 + - const: ch15 additionalProperties: false required: - compatible - reg + - reg-names - interrupts - "#address-cells" - "#size-cells"
@@ -182,7 +244,13 @@ examples: memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <2>;
Signature · 1 line
2.17.1
Rob Herring
maintainerRe: [Patch v7 3/4] dt-bindings: memory: Update reg/reg-names validation
Quoted 1 line · Ashish Mhetre
Running 'make dtbs_check' with the schema in this patch gives the following warnings. Consider if they are expected or the schema is incorrect. These may not be new warnings.
Note that it is not yet a requirement to have 0 warnings for dtbs_check. This will change in the future.
Full log is available here: https://patchwork.ozlabs.org/patch/
memory-controller@2c00000: reg: [[0, 46137344, 0, 720896]] is too short
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dtb arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dtb arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dtb arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dtb
memory-controller@2c00000: reg: [[46137344, 1048576], [45613056, 262144], [24117248, 1048576]] is too short
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dtb arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dtb arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dtb arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dtb arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dtb arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dtb arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dtb arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dtb arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dtb arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dtb
memory-controller@2c00000: 'reg-names' is a required property
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dtb arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dtb arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dtb arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dtb arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dtb arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dtb arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dtb
Rob Herring
maintainerRe: [Patch v7 3/4] dt-bindings: memory: Update reg/reg-names validation
In reply to Ashish MhetreQuoted 8 lines · Ashish Mhetre
From tegra186 onwards, memory controller support multiple channels. Reg items are updated with address and size of these channels. Tegra186 has overall 5 memory controller channels. Tegra194 and tegra234 have overall 17 memory controller channels each.
There is 1 reg item for memory controller stream-id registers. So update the reg maxItems to 18 in tegra186 devicetree documentation. Also update validation for reg-names added for these corresponding reg items.
Somehow your subject should indicate this is for Tegra.
Quoted 11 lines
Signed-off-by Ashish Mhetre <[email protected]>--- .../nvidia,tegra186-mc.yaml | 80 +++++++++++++++++-- 1 file changed, 74 insertions(+), 6 deletions(-)Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +0
-0
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml properties: · line 37
Quoted 6 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +1
-2@@ -34,8 +34,12 @@ properties: - nvidia,tegra234-mc reg: - minItems: 1 - maxItems: 3 + minItems: 6
You just broke current users.
Quoted 86 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +62
-3+ maxItems: 18 + + reg-names: + minItems: 6 + maxItems: 18 interrupts: items:@@ -142,7 +146,18 @@ allOf: then: properties: reg: - maxItems: 1 + maxItems: 6 + description: 5 memory controller channels and 1 for stream-id registers + + reg-names: + maxItems: 6 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 - if: properties:@@ -151,7 +166,30 @@ allOf: then: properties: reg: - minItems: 3 + minItems: 18 + description: 17 memory controller channels and 1 for stream-id registers + + reg-names: + minItems: 18 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + - const: ch8 + - const: ch9 + - const: ch10 + - const: ch11 + - const: ch12 + - const: ch13 + - const: ch14 + - const: ch15 - if: properties:@@ -160,13 +198,37 @@ allOf: then: properties: reg: - minItems: 3 + minItems: 18 + description: 17 memory controller channels and 1 for stream-id registers + + reg-names: + minItems: 18 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + - const: ch8 + - const: ch9 + - const: ch10 + - const: ch11 + - const: ch12
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml allOf: · line 231
Quoted 10 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +4
-0+ - const: ch13 + - const: ch14 + - const: ch15 additionalProperties: false required: - compatible - reg + - reg-names
New, added properties cannot be required. That's an ABI break.
Quoted 21 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +7
-1- interrupts - "#address-cells" - "#size-cells"@@ -182,7 +244,13 @@ examples: memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <2>;Signature · 1 line
2.17.1
Re: [Patch v7 3/4] dt-bindings: memory: Update reg/reg-names validation
Quoted 148 lines · Rob Herring
Quoted 8 lines · Ashish Mhetre
From tegra186 onwards, memory controller support multiple channels. Reg items are updated with address and size of these channels. Tegra186 has overall 5 memory controller channels. Tegra194 and tegra234 have overall 17 memory controller channels each.
There is 1 reg item for memory controller stream-id registers. So update the reg maxItems to 18 in tegra186 devicetree documentation. Also update validation for reg-names added for these corresponding reg items.Somehow your subject should indicate this is for Tegra.
Quoted 11 lines
Signed-off-by Ashish Mhetre <[email protected]>--- .../nvidia,tegra186-mc.yaml | 80 +++++++++++++++++-- 1 file changed, 74 insertions(+), 6 deletions(-)Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +0
-0Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml properties: · line 37
Quoted 6 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +1
-2@@ -34,8 +34,12 @@ properties: - nvidia,tegra234-mc reg: - minItems: 1 - maxItems: 3 + minItems: 6You just broke current users.
Quoted 86 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +62
-3+ maxItems: 18 + + reg-names: + minItems: 6 + maxItems: 18 interrupts: items:@@ -142,7 +146,18 @@ allOf: then: properties: reg: - maxItems: 1 + maxItems: 6 + description: 5 memory controller channels and 1 for stream-id registers + + reg-names: + maxItems: 6 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 - if: properties:@@ -151,7 +166,30 @@ allOf: then: properties: reg: - minItems: 3 + minItems: 18 + description: 17 memory controller channels and 1 for stream-id registers + + reg-names: + minItems: 18 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + - const: ch8 + - const: ch9 + - const: ch10 + - const: ch11 + - const: ch12 + - const: ch13 + - const: ch14 + - const: ch15 - if: properties:@@ -160,13 +198,37 @@ allOf: then: properties: reg: - minItems: 3 + minItems: 18 + description: 17 memory controller channels and 1 for stream-id registers + + reg-names: + minItems: 18 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + - const: ch8 + - const: ch9 + - const: ch10 + - const: ch11 + - const: ch12Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml allOf: · line 231
Quoted 10 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +4
-0+ - const: ch13 + - const: ch14 + - const: ch15 additionalProperties: false required: - compatible - reg + - reg-namesNew, added properties cannot be required. That's an ABI break.
Quoted 17 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +7
-1- interrupts - "#address-cells" - "#size-cells"@@ -182,7 +244,13 @@ examples: memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
Quoted 4 lines
Quoted 4 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +0
-0#address-cells = <2>;Signature · 1 line
2.17.1
Oh, wait.. I didn't notice that the new reg ranges are only splitting up the old ranges. Previously it appeared to me that these are the new ranges.
Ashish, in this case you don't need to change the regs in the DT at all. Instead, you need to specify the per-channel reg-base offsets in the driver code.
Re: [Patch v7 3/4] dt-bindings: memory: Update reg/reg-names validation
Quoted 159 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
Quoted 148 lines · Rob Herring
Quoted 8 lines · Ashish Mhetre
From tegra186 onwards, memory controller support multiple channels.
Reg items are updated with address and size of these channels. Tegra186 has overall 5 memory controller channels. Tegra194 and tegra234 have overall 17 memory controller channels each.
There is 1 reg item for memory controller stream-id registers. So update the reg maxItems to 18 in tegra186 devicetree documentation. Also update validation for reg-names added for these corresponding reg items.Somehow your subject should indicate this is for Tegra.
Quoted 11 lines
Signed-off-by Ashish Mhetre <[email protected]>--- .../nvidia,tegra186-mc.yaml | 80 +++++++++++++++++-- 1 file changed, 74 insertions(+), 6 deletions(-)Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +0
-0Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml properties: · line 37
Quoted 6 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +1
-2@@ -34,8 +34,12 @@ properties: - nvidia,tegra234-mc reg: - minItems: 1 - maxItems: 3 + minItems: 6You just broke current users.
Quoted 86 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +62
-3+ maxItems: 18 + + reg-names: + minItems: 6 + maxItems: 18 interrupts: items:@@ -142,7 +146,18 @@ allOf: then: properties: reg: - maxItems: 1 + maxItems: 6 + description: 5 memory controller channels and 1 for stream-id registers + + reg-names: + maxItems: 6 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 - if: properties:@@ -151,7 +166,30 @@ allOf: then: properties: reg: - minItems: 3 + minItems: 18 + description: 17 memory controller channels and 1 for stream-id registers + + reg-names: + minItems: 18 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + - const: ch8 + - const: ch9 + - const: ch10 + - const: ch11 + - const: ch12 + - const: ch13 + - const: ch14 + - const: ch15 - if: properties:@@ -160,13 +198,37 @@ allOf: then: properties: reg: - minItems: 3 + minItems: 18 + description: 17 memory controller channels and 1 for stream-id registers + + reg-names: + minItems: 18 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + - const: ch8 + - const: ch9 + - const: ch10 + - const: ch11 + - const: ch12Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml allOf: · line 231
Quoted 10 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +4
-0+ - const: ch13 + - const: ch14 + - const: ch15 additionalProperties: false required: - compatible - reg + - reg-namesNew, added properties cannot be required. That's an ABI break.
Quoted 17 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +7
-1- interrupts - "#address-cells" - "#size-cells"@@ -182,7 +244,13 @@ examples: memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;Quoted 4 lines
Quoted 4 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +0
-1#address-cells = <2>; --2.17.1
Oh, wait.. I didn't notice that the new reg ranges are only splitting up the old ranges. Previously it appeared to me that these are the new ranges.
Quoted 3 lines
Quoted 1 line
Ashish, in this case you don't need to change the regs in the DT at all.
Instead, you need to specify the per-channel reg-base offsets in the driver code.
Yes, it's kind of splitting up the old ranges and straight forward for Tegra186. But on Tegra194 and Tegra234 the old address is not in single range. It's already split across 3 ranges. We have to choose right range and add channel offsets to that range in order to read interrupts. So I went with the approach of splitting the regs in DT itself as per the channels because that way they can be mapped in a single loop and used easily.
If we want to specify per-channel reg-base offsets then that would be per-SOC. Also we would need to choose correct reg-range for Tegra194 and Tegra234 and have a way to maintain offsets of channels from those respective reg-ranges.
Re: [Patch v7 3/4] dt-bindings: memory: Update reg/reg-names validation
Quoted 182 lines · Ashish Mhetre
Quoted 166 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
Quoted 162 lines · Rob Herring
Quoted 9 lines · Ashish Mhetre
From tegra186 onwards, memory controller support multiple channels. Reg items are updated with address and size of these channels. Tegra186 has overall 5 memory controller channels. Tegra194 and tegra234
have overall 17 memory controller channels each.
There is 1 reg item for memory controller stream-id registers. So update the reg maxItems to 18 in tegra186 devicetree documentation. Also update validation for reg-names added for these corresponding reg items.Somehow your subject should indicate this is for Tegra.
Quoted 21 lines
Signed-off-by Ashish Mhetre <[email protected]>---
.../nvidia,tegra186-mc.yaml | 80
+++++++++++++++++--1 file changed, 74 insertions(+), 6 deletions(-)diff --git
a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yamlb/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yamlindex
13c4c82fd0d3..c7cfa6c2cd81100644
---a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml+++
b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml(quoted diff) +0
-0@@ -34,8 +34,12 @@ properties:- nvidia,tegra234-mc
Quoted 4 lines
reg:
- minItems: 1
- maxItems: 3
+ minItems: 6You just broke current users.
Quoted 93 lines
+ maxItems: 18
+
+ reg-names:
+ minItems: 6
+ maxItems: 18interrupts:
items:(quoted diff) +0
-0@@ -142,7 +146,18 @@ allOf:then:
properties:
reg:
- maxItems: 1
+ maxItems: 6
+ description: 5 memory controller channels and 1 for stream-id registers
+
+ reg-names:
+ maxItems: 6
+ items:
+ - const: sid
+ - const: broadcast
+ - const: ch0
+ - const: ch1
+ - const: ch2
+ - const: ch3- if:
properties:(quoted diff) +0
-0@@ -151,7 +166,30 @@ allOf:then:
properties:
reg:
- minItems: 3
+ minItems: 18
+ description: 17 memory controller channels and 1 for stream-id registers
+
+ reg-names:
+ minItems: 18
+ items:
+ - const: sid
+ - const: broadcast
+ - const: ch0
+ - const: ch1
+ - const: ch2
+ - const: ch3
+ - const: ch4
+ - const: ch5
+ - const: ch6
+ - const: ch7
+ - const: ch8
+ - const: ch9
+ - const: ch10
+ - const: ch11
+ - const: ch12
+ - const: ch13
+ - const: ch14
+ - const: ch15- if:
properties:(quoted diff) +0
-0@@ -160,13 +198,37 @@ allOf:then:
properties:
reg:
- minItems: 3
+ minItems: 18
+ description: 17 memory controller channels and 1 for stream-id registers
+
+ reg-names:
+ minItems: 18
+ items:
+ - const: sid
+ - const: broadcast
+ - const: ch0
+ - const: ch1
+ - const: ch2
+ - const: ch3
+ - const: ch4
+ - const: ch5
+ - const: ch6
+ - const: ch7
+ - const: ch8
+ - const: ch9
+ - const: ch10
+ - const: ch11
+ - const: ch12
+ - const: ch13
+ - const: ch14
+ - const: ch15Quoted 6 lines
additionalProperties: false
required:
- compatible
- reg
+ - reg-namesNew, added properties cannot be required. That's an ABI break.
Quoted 19 lines
- interrupts
- "#address-cells"
- "#size-cells"Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +2
-1@@ -182,7 +244,13 @@ examples: memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcastchannel */
+ <0x00x02c200000x00x10000>, /* MC0 */ + <0x00x02c300000x00x10000>, /* MC1 */ + <0x00x02c400000x00x10000>, /* MC2 */ + <0x00x02c500000x00x10000>; /* MC3 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
interrupts = <GIC_SPI223IRQ_TYPE_LEVEL_HIGH>;Quoted 12 lines
Quoted 4 lines
Quoted 4 lines
#address-cells = <2>;
Signature · 1 line
2.17.1Oh, wait.. I didn't notice that the new reg ranges are only splitting up the old ranges. Previously it appeared to me that these are the new ranges.
> Ashish, in this case you don't need to change the regs in the DT at all.
Instead, you need to specify the per-channel reg-base offsets in the driver code.
Quoted 11 lines
Yes, it's kind of splitting up the old ranges and straight forward for Tegra186. But on Tegra194 and Tegra234 the old address is not in single range. It's already split across 3 ranges. We have to choose right range and add channel offsets to that range in order to read interrupts. So I went with the approach of splitting the regs in DT itself as per the channels because that way they can be mapped in a single loop and used easily.
If we want to specify per-channel reg-base offsets then that would be per-SOC. Also we would need to choose correct reg-range for Tegra194 and Tegra234 and have a way to maintain offsets of channels from those respective reg-ranges.
That is not nice too. Should be better to switch to the new DT scheme, since those channels weren't used by older kernels. It's okay to change the binding ABI in this case then, driver will continue to work for the older dtbs. Have you tested driver using the older dtbs?
Re: [Patch v7 3/4] dt-bindings: memory: Update reg/reg-names validation
Quoted 198 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
Quoted 182 lines · Ashish Mhetre
Quoted 174 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
Quoted 162 lines · Rob Herring
Quoted 9 lines · Ashish Mhetre
From tegra186 onwards, memory controller support multiple channels.
Reg items are updated with address and size of these channels. Tegra186 has overall 5 memory controller channels. Tegra194 and tegra234
have overall 17 memory controller channels each.
There is 1 reg item for memory controller stream-id registers. So update the reg maxItems to 18 in tegra186 devicetree documentation. Also update validation for reg-names added for these corresponding reg items.Somehow your subject should indicate this is for Tegra.
Quoted 19 lines
Signed-off-by Ashish Mhetre <[email protected]>--- .../nvidia,tegra186-mc.yaml | 80 +++++++++++++++++-- 1 file changed, 74 insertions(+), 6 deletions(-)diff --git
a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yamlb/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yamlindex
13c4c82fd0d3..c7cfa6c2cd81100644
---a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml+++
b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yamlDocumentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml properties: · line 37
Quoted 6 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +1
-2@@ -34,8 +34,12 @@ properties: - nvidia,tegra234-mc reg: - minItems: 1 - maxItems: 3 + minItems: 6You just broke current users.
Quoted 89 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +7
-1+ maxItems: 18 + + reg-names: + minItems: 6 + maxItems: 18 interrupts: items:@@ -142,7 +146,18 @@ allOf: then: properties: reg: - maxItems: 1 + maxItems: 6 + description: 5 memory controller channels and 1 forstream-id registers
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +12
-1+ + reg-names: + maxItems: 6 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 - if: properties:@@ -151,7 +166,30 @@ allOf: then: properties: reg: - minItems: 3 + minItems: 18 + description: 17 memory controller channels and 1 forstream-id registers
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +24
-1+ + reg-names: + minItems: 18 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + - const: ch8 + - const: ch9 + - const: ch10 + - const: ch11 + - const: ch12 + - const: ch13 + - const: ch14 + - const: ch15 - if: properties:@@ -160,13 +198,37 @@ allOf: then: properties: reg: - minItems: 3 + minItems: 18 + description: 17 memory controller channels and 1 forstream-id registers
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +19
-0+ + reg-names: + minItems: 18 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + - const: ch8 + - const: ch9 + - const: ch10 + - const: ch11 + - const: ch12Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml allOf: · line 231
Quoted 10 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +4
-0+ - const: ch13 + - const: ch14 + - const: ch15 additionalProperties: false required: - compatible - reg + - reg-namesNew, added properties cannot be required. That's an ABI break.
Quoted 19 lines
- interrupts
- "#address-cells"
- "#size-cells"Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +2
-1@@ -182,7 +244,13 @@ examples: memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcastchannel */
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +5
-0+ <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2","ch3"; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;Quoted 4 lines
Quoted 4 lines
#address-cells = <2>;--
2.17.1Oh, wait.. I didn't notice that the new reg ranges are only splitting up the old ranges. Previously it appeared to me that these are the new ranges.
Quoted 4 lines
Quoted 1 line
Ashish, in this case you don't need to change the regs in the DT at
all.
Instead, you need to specify the per-channel reg-base offsets in the driver code.Quoted 11 lines
Yes, it's kind of splitting up the old ranges and straight forward for Tegra186. But on Tegra194 and Tegra234 the old address is not in single range. It's already split across 3 ranges. We have to choose right range and add channel offsets to that range in order to read interrupts. So I went with the approach of splitting the regs in DT itself as per the channels because that way they can be mapped in a single loop and used easily.
If we want to specify per-channel reg-base offsets then that would be per-SOC. Also we would need to choose correct reg-range for Tegra194 and Tegra234 and have a way to maintain offsets of channels from those respective reg-ranges.
Quoted 4 lines
That is not nice too. Should be better to switch to the new DT scheme, since those channels weren't used by older kernels. It's okay to change the binding ABI in this case then, driver will continue to work for the older dtbs.
So the current DTS and binding changes are fine?
Quoted 1 line
Have you tested driver using the older dtbs?
Yes, the driver is tested with old dtb and it's working fine.
Re: [Patch v7 3/4] dt-bindings: memory: Update reg/reg-names validation
Quoted 208 lines · Ashish Mhetre
Quoted 205 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
Quoted 200 lines · Ashish Mhetre
Quoted 172 lines · Dmitry Osipenko
External email: Use caution opening links or attachments
Quoted 168 lines · Rob Herring
Quoted 11 lines · Ashish Mhetre
From tegra186 onwards, memory controller support multiple channels. Reg items are updated with address and size of these channels. Tegra186 has overall 5 memory controller channels. Tegra194 and tegra234
have overall 17 memory controller channels each.
There is 1 reg item for memory controller stream-id registers. So update the reg maxItems to 18 in tegra186 devicetree documentation.
Also update validation for reg-names added for these corresponding reg
items.Somehow your subject should indicate this is for Tegra.
Quoted 25 lines
Signed-off-by Ashish Mhetre <[email protected]>---
.../nvidia,tegra186-mc.yaml | 80
+++++++++++++++++--1 file changed, 74 insertions(+), 6 deletions(-)diff --git
a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yamlindex
13c4c82fd0d3..c7cfa6c2cd81100644
---a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml+++
b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml(quoted diff) +0
-0@@ -34,8 +34,12 @@ properties:- nvidia,tegra234-mc
Quoted 4 lines
reg:
- minItems: 1
- maxItems: 3
+ minItems: 6You just broke current users.
Quoted 93 lines
+ maxItems: 18
+
+ reg-names:
+ minItems: 6
+ maxItems: 18interrupts:
items:(quoted diff) +0
-0@@ -142,7 +146,18 @@ allOf:then:
properties:
reg:
- maxItems: 1
+ maxItems: 6
+ description: 5 memory controller channels and 1 for stream-id registers
+
+ reg-names:
+ maxItems: 6
+ items:
+ - const: sid
+ - const: broadcast
+ - const: ch0
+ - const: ch1
+ - const: ch2
+ - const: ch3- if:
properties:(quoted diff) +0
-0@@ -151,7 +166,30 @@ allOf:then:
properties:
reg:
- minItems: 3
+ minItems: 18
+ description: 17 memory controller channels and 1 for stream-id registers
+
+ reg-names:
+ minItems: 18
+ items:
+ - const: sid
+ - const: broadcast
+ - const: ch0
+ - const: ch1
+ - const: ch2
+ - const: ch3
+ - const: ch4
+ - const: ch5
+ - const: ch6
+ - const: ch7
+ - const: ch8
+ - const: ch9
+ - const: ch10
+ - const: ch11
+ - const: ch12
+ - const: ch13
+ - const: ch14
+ - const: ch15- if:
properties:(quoted diff) +0
-0@@ -160,13 +198,37 @@ allOf:then:
properties:
reg:
- minItems: 3
+ minItems: 18
+ description: 17 memory controller channels and 1 for stream-id registers
+
+ reg-names:
+ minItems: 18
+ items:
+ - const: sid
+ - const: broadcast
+ - const: ch0
+ - const: ch1
+ - const: ch2
+ - const: ch3
+ - const: ch4
+ - const: ch5
+ - const: ch6
+ - const: ch7
+ - const: ch8
+ - const: ch9
+ - const: ch10
+ - const: ch11
+ - const: ch12
+ - const: ch13
+ - const: ch14
+ - const: ch15Quoted 6 lines
additionalProperties: false
required:
- compatible
- reg
+ - reg-namesNew, added properties cannot be required. That's an ABI break.
Quoted 19 lines
- interrupts
- "#address-cells"
- "#size-cells"Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +2
-1@@ -182,7 +244,13 @@ examples: memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcastchannel */
+ <0x00x02c200000x00x10000>, /* MC0 */ + <0x00x02c300000x00x10000>, /* MC1 */ + <0x00x02c400000x00x10000>, /* MC2 */ + <0x00x02c500000x00x10000>; /* MC3 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
interrupts = <GIC_SPI223IRQ_TYPE_LEVEL_HIGH>;Quoted 13 lines
Quoted 4 lines
Quoted 4 lines
#address-cells = <2>;
Signature · 1 line
2.17.1Oh, wait.. I didn't notice that the new reg ranges are only splitting up
the old ranges. Previously it appeared to me that these are the new ranges.
> Ashish, in this case you don't need to change the regs in the DT at all.
Instead, you need to specify the per-channel reg-base offsets in the driver code.Yes, it's kind of splitting up the old ranges and straight forward for Tegra186. But on Tegra194 and Tegra234 the old address is not in single range. It's already split across 3 ranges. We have to choose right range and add channel offsets to that range in order to read interrupts. So I went with the approach of splitting the regs in DT itself as per the channels because that way they can be mapped in a single loop and used easily.
If we want to specify per-channel reg-base offsets then that would be per-SOC. Also we would need to choose correct reg-range for Tegra194 and Tegra234 and have a way to maintain offsets of channels from those respective reg-ranges.
Quoted 6 lines
Quoted 4 lines
That is not nice too. Should be better to switch to the new DT scheme, since those channels weren't used by older kernels. It's okay to change the binding ABI in this case then, driver will continue to work for the older dtbs.
So the current DTS and binding changes are fine?
It's fine to me. Doesn't hurt to explain in the commit message that the ABI change is intended and it's compatible with the previous ABI.
Quoted 3 lines
Quoted 1 line
Have you tested driver using the older dtbs?
Yes, the driver is tested with old dtb and it's working fine.
Ok
Re: [Patch v7 3/4] dt-bindings: memory: Update reg/reg-names validation
In reply to Rob HerringQuoted 13 lines · Rob Herring
External email: Use caution opening links or attachments
Quoted 8 lines · Ashish Mhetre
From tegra186 onwards, memory controller support multiple channels.
Reg items are updated with address and size of these channels. Tegra186 has overall 5 memory controller channels. Tegra194 and tegra234 have overall 17 memory controller channels each.
There is 1 reg item for memory controller stream-id registers. So update the reg maxItems to 18 in tegra186 devicetree documentation. Also update validation for reg-names added for these corresponding reg items.
Quoted 2 lines
Somehow your subject should indicate this is for Tegra.
Okay, I'll update the subject.
Quoted 13 lines
Quoted 13 lines
Signed-off-by Ashish Mhetre <[email protected]>--- .../nvidia,tegra186-mc.yaml | 80 +++++++++++++++++-- 1 file changed, 74 insertions(+), 6 deletions(-)Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +0
-0@@ -34,8 +34,12 @@ properties: - nvidia,tegra234-mc
Quoted 7 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml properties: · line 37
Quoted 4 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +1
-2reg: - minItems: 1 - maxItems: 3 + minItems: 6You just broke current users.
The DTS changes are handled in driver. The driver is compatible with older DTS as well. dt bindings check will fail but that will request the users to switch to new DTS. Will that be fine?
Quoted 90 lines
Quoted 90 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +65
-3+ maxItems: 18 + + reg-names: + minItems: 6 + maxItems: 18 interrupts: items:@@ -142,7 +146,18 @@ allOf: then: properties: reg: - maxItems: 1 + maxItems: 6 + description: 5 memory controller channels and 1 for stream-id registers + + reg-names: + maxItems: 6 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 - if: properties:@@ -151,7 +166,30 @@ allOf: then: properties: reg: - minItems: 3 + minItems: 18 + description: 17 memory controller channels and 1 for stream-id registers + + reg-names: + minItems: 18 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + - const: ch8 + - const: ch9 + - const: ch10 + - const: ch11 + - const: ch12 + - const: ch13 + - const: ch14 + - const: ch15 - if: properties:@@ -160,13 +198,37 @@ allOf: then: properties: reg: - minItems: 3 + minItems: 18 + description: 17 memory controller channels and 1 for stream-id registers + + reg-names: + minItems: 18 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + - const: ch8 + - const: ch9 + - const: ch10 + - const: ch11 + - const: ch12 + - const: ch13 + - const: ch14 + - const: ch15
Quoted 9 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml allOf: · line 231
Quoted 6 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +1
-0additionalProperties: false required: - compatible - reg + - reg-namesNew, added properties cannot be required. That's an ABI break.
This is handled in driver code to make sure driver works with old dts as well. So is this bindings change fine or shall I change it such that dt bindings check shall pass with older dts as well?
Or as mentioned by Dmitry, I can update the commit message to reflect that ABI change is intended and driver is compatible with older DTBs as well.
Quoted 21 lines
Quoted 21 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +7
-2- interrupts - "#address-cells" - "#size-cells"@@ -182,7 +244,13 @@ examples: memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <2>; --2.17.1
Re: [Patch v7 3/4] dt-bindings: memory: Update reg/reg-names validation
Quoted 151 lines · Ashish Mhetre
Quoted 13 lines · Rob Herring
External email: Use caution opening links or attachments
Quoted 8 lines · Ashish Mhetre
From tegra186 onwards, memory controller support multiple channels. Reg items are updated with address and size of these channels. Tegra186 has overall 5 memory controller channels. Tegra194 and tegra234 have overall 17 memory controller channels each.
There is 1 reg item for memory controller stream-id registers. So update the reg maxItems to 18 in tegra186 devicetree documentation. Also update validation for reg-names added for these corresponding reg items.Quoted 2 lines
Somehow your subject should indicate this is for Tegra.
Okay, I'll update the subject.
Quoted 18 lines
Quoted 18 lines
Signed-off-by Ashish Mhetre <[email protected]>---
.../nvidia,tegra186-mc.yaml | 80 +++++++++++++++++--1 file changed, 74 insertions(+), 6 deletions(-)Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +0
-0index
13c4c82fd0d3..c7cfa6c2cd81100644
---a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml+++
b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yamlDocumentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +0
-0@@ -34,8 +34,12 @@ properties:- nvidia,tegra234-mc
Quoted 7 lines
Quoted 4 lines
reg:
- minItems: 1
- maxItems: 3
+ minItems: 6You just broke current users.
The DTS changes are handled in driver. The driver is compatible with older DTS as well. dt bindings check will fail but that will request the users to switch to new DTS. Will that be fine?
Quoted 93 lines
Quoted 93 lines
+ maxItems: 18
+
+ reg-names:
+ minItems: 6
+ maxItems: 18interrupts:
items:Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +0
-0@@ -142,7 +146,18 @@ allOf:then:
properties:
reg:
- maxItems: 1
+ maxItems: 6
+ description: 5 memory controller channels and 1 for stream-id registers
+
+ reg-names:
+ maxItems: 6
+ items:
+ - const: sid
+ - const: broadcast
+ - const: ch0
+ - const: ch1
+ - const: ch2
+ - const: ch3- if:
properties:Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +0
-0@@ -151,7 +166,30 @@ allOf:then:
properties:
reg:
- minItems: 3
+ minItems: 18
+ description: 17 memory controller channels and 1 for stream-id registers
+
+ reg-names:
+ minItems: 18
+ items:
+ - const: sid
+ - const: broadcast
+ - const: ch0
+ - const: ch1
+ - const: ch2
+ - const: ch3
+ - const: ch4
+ - const: ch5
+ - const: ch6
+ - const: ch7
+ - const: ch8
+ - const: ch9
+ - const: ch10
+ - const: ch11
+ - const: ch12
+ - const: ch13
+ - const: ch14
+ - const: ch15- if:
properties:Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +0
-0@@ -160,13 +198,37 @@ allOf:then:
properties:
reg:
- minItems: 3
+ minItems: 18
+ description: 17 memory controller channels and 1 for stream-id registers
+
+ reg-names:
+ minItems: 18
+ items:
+ - const: sid
+ - const: broadcast
+ - const: ch0
+ - const: ch1
+ - const: ch2
+ - const: ch3
+ - const: ch4
+ - const: ch5
+ - const: ch6
+ - const: ch7
+ - const: ch8
+ - const: ch9
+ - const: ch10
+ - const: ch11
+ - const: ch12
+ - const: ch13
+ - const: ch14
+ - const: ch15Quoted 9 lines
Quoted 6 lines
additionalProperties: false
required:
- compatible
- reg
+ - reg-namesNew, added properties cannot be required. That's an ABI break.
Quoted 7 lines
This is handled in driver code to make sure driver works with old dts as well. So is this bindings change fine or shall I change it such that dt bindings check shall pass with older dts as well?
Or as mentioned by Dmitry, I can update the commit message to reflect that ABI change is intended and driver is compatible with older DTBs as well.
Hi Rob,
Can you please confirm how shall I go in next version?
Is it fine for dt bindings check to fail if driver is compatible with old as well as new dts? Or dt bindings check shall pass with old as well as new dts?
Quoted 22 lines
Quoted 22 lines
Quoted 22 lines
- interrupts
- "#address-cells"
- "#size-cells"Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +2
-1@@ -182,7 +244,13 @@ examples: memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcastchannel */
+ <0x00x02c200000x00x10000>, /* MC0 */ + <0x00x02c300000x00x10000>, /* MC1 */ + <0x00x02c400000x00x10000>, /* MC2 */ + <0x00x02c500000x00x10000>; /* MC3 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; interrupts = <GIC_SPI223IRQ_TYPE_LEVEL_HIGH>;#address-cells = <2>;
Signature · 1 line
2.17.1
Re: [Patch v7 3/4] dt-bindings: memory: Update reg/reg-names validation
Quoted 10 lines · Ashish Mhetre
Quoted 10 lines
Quoted 3 lines
New, added properties cannot be required. That's an ABI break.
This is handled in driver code to make sure driver works with old dts as well. So is this bindings change fine or shall I change it such that dt bindings check shall pass with older dts as well?
Or as mentioned by Dmitry, I can update the commit message to reflect that ABI change is intended and driver is compatible with older DTBs as well.
Quoted 5 lines
Hi Rob,
Can you please confirm how shall I go in next version?
Is it fine for dt bindings check to fail if driver is compatible with old as well as new dts? Or dt bindings check shall pass with old as well as new dts?
The driver works fine without reg-names and accepts old DTB, right? In such case, just mention this in commit msg, that the bindings require reg-names but backwards compatibility will be preserved in the driver. I think it's fine to alter bindings such way.
Best regards,
Krzysztof
Re: [Patch v7 3/4] dt-bindings: memory: Update reg/reg-names validation
Quoted 19 lines · Krzysztof Kozlowski
External email: Use caution opening links or attachments
Quoted 10 lines · Ashish Mhetre
Quoted 10 lines
Quoted 3 lines
New, added properties cannot be required. That's an ABI break.
This is handled in driver code to make sure driver works with old dts as well. So is this bindings change fine or shall I change it such that dt bindings check shall pass with older dts as well?
Or as mentioned by Dmitry, I can update the commit message to reflect that ABI change is intended and driver is compatible with older DTBs as well.Quoted 5 lines
Hi Rob,
Can you please confirm how shall I go in next version?
Is it fine for dt bindings check to fail if driver is compatible with old as well as new dts? Or dt bindings check shall pass with old as well as new dts?
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The driver works fine without reg-names and accepts old DTB, right? In such case, just mention this in commit msg, that the bindings require reg-names but backwards compatibility will be preserved in the driver. I think it's fine to alter bindings such way.
Thanks for confirming Krzysztof. I'll send v8 with this information.
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Best regards,
Krzysztof
PATCH v7 4/4 arm64: tegra: Add memory controller channels
In reply to Ashish MhetreFrom tegra186 onwards, memory controller support multiple channels. During the error interrupts from memory controller, corresponding channels need to be accessed for logging error info and clearing the interrupt.
So add address and size of these channels in device tree node of tegra186, tegra194 and tegra234 memory controller. Also add reg-names for each of these reg items which are used by driver for mapping.
--- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 8 +++++++- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 24 +++++++++++++++++++++--- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 24 +++++++++++++++++++++--- 3 files changed, 49 insertions(+), 7 deletions(-)
arch/arm64/boot/dts/nvidia/tegra186.dtsi +7 -1
@@ -521,7 +521,13 @@ mc: memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; status = "disabled";
arch/arm64/boot/dts/nvidia/tegra194.dtsi +21 -3
@@ -604,9 +604,27 @@ mc: memory-controller@2c00000 { compatible = "nvidia,tegra194-mc"; - reg = <0x02c00000 0x100000>, - <0x02b80000 0x040000>, - <0x01700000 0x100000>; + reg = <0x02c00000 0x10000>, /* MC-SID */ + <0x02c10000 0x10000>, /* MC Broadcast*/ + <0x02c20000 0x10000>, /* MC0 */ + <0x02c30000 0x10000>, /* MC1 */ + <0x02c40000 0x10000>, /* MC2 */ + <0x02c50000 0x10000>, /* MC3 */ + <0x02b80000 0x10000>, /* MC4 */ + <0x02b90000 0x10000>, /* MC5 */ + <0x02ba0000 0x10000>, /* MC6 */ + <0x02bb0000 0x10000>, /* MC7 */ + <0x01700000 0x10000>, /* MC8 */ + <0x01710000 0x10000>, /* MC9 */ + <0x01720000 0x10000>, /* MC10 */ + <0x01730000 0x10000>, /* MC11 */ + <0x01740000 0x10000>, /* MC12 */ + <0x01750000 0x10000>, /* MC13 */ + <0x01760000 0x10000>, /* MC14 */ + <0x01770000 0x10000>; /* MC15 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", + "ch11", "ch12", "ch13", "ch14", "ch15"; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; #interconnect-cells = <1>; status = "disabled";
arch/arm64/boot/dts/nvidia/tegra234.dtsi +21 -3
@@ -507,9 +507,27 @@ mc: memory-controller@2c00000 { compatible = "nvidia,tegra234-mc"; - reg = <0x02c00000 0x100000>, - <0x02b80000 0x040000>, - <0x01700000 0x100000>; + reg = <0x02c00000 0x10000>, /* MC-SID */ + <0x02c10000 0x10000>, /* MC Broadcast*/ + <0x02c20000 0x10000>, /* MC0 */ + <0x02c30000 0x10000>, /* MC1 */ + <0x02c40000 0x10000>, /* MC2 */ + <0x02c50000 0x10000>, /* MC3 */ + <0x02b80000 0x10000>, /* MC4 */ + <0x02b90000 0x10000>, /* MC5 */ + <0x02ba0000 0x10000>, /* MC6 */ + <0x02bb0000 0x10000>, /* MC7 */ + <0x01700000 0x10000>, /* MC8 */ + <0x01710000 0x10000>, /* MC9 */ + <0x01720000 0x10000>, /* MC10 */ + <0x01730000 0x10000>, /* MC11 */ + <0x01740000 0x10000>, /* MC12 */ + <0x01750000 0x10000>, /* MC13 */ + <0x01760000 0x10000>, /* MC14 */ + <0x01770000 0x10000>; /* MC15 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", + "ch11", "ch12", "ch13", "ch14", "ch15"; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; #interconnect-cells = <1>; status = "okay";
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2.17.1