Skip to contentSkip to conversation

16K page size in 32 bit kernel

PATCH In review Dajie Tan 3 participants 6 messages Jul 31, 2007 – Aug 1, 2007 MIPS

lore
Share & tools
lore

Dajie Tan

author
#0 lore raw

PATCH 1/1 16K page size in 32 bit kernel

32-bit Kernel for loongson2e currently use 16KB page size to avoid cache alias problem.So, the definiton of PGDIR_SHIFT muse be 12+14.

Using 22 in 16K page size do not lead to a serious problem but the number of pages allocated for page table is more than previous. (cat /proc/vmstat | grep nr_page_table_pages)

It's been tested on FuLong mini PC(loongson2e inside).

---
 include/asm-mips/pgtable-32.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
include/asm-mips/pgtable-32.h +1 -1
index 2fbd47e..8d34ebf 100644
@@ -46,7 +46,7 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
 #ifdef CONFIG_64BIT_PHYS_ADDR
 #define PGDIR_SHIFT	21
 #else
-#define PGDIR_SHIFT	22
+#define PGDIR_SHIFT	(PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 2))
 #endif
 #define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
 #define PGDIR_MASK	(~(PGDIR_SIZE-1))
#1 lore raw

Thanks Dajie:)

With 22 PGDIR_SHIFT, 15 extra page tables is populated when a whole 64M address space is accessed, the patch can save memory quite a bit:)

Quoted 33 lines · Dajie Tan

32-bit Kernel for loongson2e currently use 16KB page size to avoid cache alias problem.So, the definiton of PGDIR_SHIFT muse be 12+14.

Using 22 in 16K page size do not lead to a serious problem but the number of pages allocated for page table is more than previous. (cat /proc/vmstat | grep nr_page_table_pages)

It's been tested on FuLong mini PC(loongson2e inside).

---
 include/asm-mips/pgtable-32.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
include/asm-mips/pgtable-32.h +1 -1
index 2fbd47e..8d34ebf 100644
@@ -46,7 +46,7 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
 #ifdef CONFIG_64BIT_PHYS_ADDR
 #define PGDIR_SHIFT	21
 #else
-#define PGDIR_SHIFT	22
+#define PGDIR_SHIFT	(PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 2))
 #endif
 #define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
 #define PGDIR_MASK	(~(PGDIR_SIZE-1))
#2 lore raw
In reply to Dajie Tan
Quoted 8 lines · Dajie Tan

32-bit Kernel for loongson2e currently use 16KB page size to avoid cache alias problem.So, the definiton of PGDIR_SHIFT muse be 12+14.

Using 22 in 16K page size do not lead to a serious problem but the number of pages allocated for page table is more than previous. (cat /proc/vmstat | grep nr_page_table_pages)

It's been tested on FuLong mini PC(loongson2e inside).

Looking good, applied. Thanks!

Did by coincidence any of you try 64K pages with a 32-bit kernel?

Ralf

#3 lore raw
Quoted 10 lines · Ralf Baechle
Quoted 7 lines · Dajie Tan

32-bit Kernel for loongson2e currently use 16KB page size to avoid cache alias problem.So, the definiton of PGDIR_SHIFT muse be 12+14.

Using 22 in 16K page size do not lead to a serious problem but the number of pages allocated for page table is more than previous. (cat /proc/vmstat | grep nr_page_table_pages)

Quoted 12 lines
Quoted 2 lines

It's been tested on FuLong mini PC(loongson2e inside).

Looking good, applied. Thanks!

Did by coincidence any of you try 64K pages with a 32-bit kernel?

Ralf

I think the following is more complete?

#ifdef CONFIG_64BIT_PHYS_ADDR
-#define PGDIR_SHIFT 21
+#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3))
#else
-#define PGDIR_SHIFT 22
+#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 2))
#endif

#4 lore raw
Quoted 9 lines · Songmao Tian

I think the following is more complete?

#ifdef CONFIG_64BIT_PHYS_ADDR

(quoted diff) +1 -1
-#define PGDIR_SHIFT    21
+#define PGDIR_SHIFT    (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3))

#else

(quoted diff) +1 -1
-#define PGDIR_SHIFT    22
+#define PGDIR_SHIFT    (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 2))

#endif

Better suggestion :-)

Ralf

include/asm-mips/pgtable-32.h +1 -5
index 2fbd47e..ff29485 100644
@@ -43,11 +43,7 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
  */
 
 /* PGDIR_SHIFT determines what a third-level page table entry can map */
-#ifdef CONFIG_64BIT_PHYS_ADDR
-#define PGDIR_SHIFT	21
-#else
-#define PGDIR_SHIFT	22
-#endif
+#define PGDIR_SHIFT	(2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2)
 #define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
 #define PGDIR_MASK	(~(PGDIR_SIZE-1))
 
#5 lore raw
Quoted 30 lines · Ralf Baechle
Quoted 10 lines · Songmao Tian

I think the following is more complete?

#ifdef CONFIG_64BIT_PHYS_ADDR

(quoted diff) +1 -1
-#define PGDIR_SHIFT    21
+#define PGDIR_SHIFT    (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3))

#else

(quoted diff) +1 -1
-#define PGDIR_SHIFT    22
+#define PGDIR_SHIFT    (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 2))

#endif

Better suggestion :-)

Ralf

include/asm-mips/pgtable-32.h +0 -0
index 2fbd47e..ff29485 100644
@@ -43,11 +43,7 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
  */
 

include/asm-mips/pgtable-32.h extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, · line 49

Quoted 10 lines
include/asm-mips/pgtable-32.h +1 -5
 /* PGDIR_SHIFT determines what a third-level page table entry can map */
-#ifdef CONFIG_64BIT_PHYS_ADDR
-#define PGDIR_SHIFT	21
-#else
-#define PGDIR_SHIFT	22
-#endif
+#define PGDIR_SHIFT	(2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2)
 #define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
 #define PGDIR_MASK	(~(PGDIR_SIZE-1))
 

Sure:)

Tian