16K page size in 32 bit kernel
PATCH 1/1 16K page size in 32 bit kernel
32-bit Kernel for loongson2e currently use 16KB page size to avoid cache alias problem.So, the definiton of PGDIR_SHIFT muse be 12+14.
Using 22 in 16K page size do not lead to a serious problem but the number of pages allocated for page table is more than previous. (cat /proc/vmstat | grep nr_page_table_pages)
It's been tested on FuLong mini PC(loongson2e inside).
--- include/asm-mips/pgtable-32.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
include/asm-mips/pgtable-32.h +1 -1
@@ -46,7 +46,7 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,#ifdef CONFIG_64BIT_PHYS_ADDR #define PGDIR_SHIFT 21#else -#define PGDIR_SHIFT 22 +#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 2))#endif #define PGDIR_SIZE (1UL << PGDIR_SHIFT)#define PGDIR_MASK (~(PGDIR_SIZE-1))
Thanks Dajie:)
With 22 PGDIR_SHIFT, 15 extra page tables is populated when a whole 64M address space is accessed, the patch can save memory quite a bit:)
Quoted 33 lines · Dajie Tan
32-bit Kernel for loongson2e currently use 16KB page size to avoid cache alias problem.So, the definiton of
PGDIR_SHIFTmuse be 12+14.Using 22 in 16K page size do not lead to a serious problem but the number of pages allocated for page table is more than previous. (cat
/proc/vmstat| grepnr_page_table_pages)It's been tested on FuLong mini PC(loongson2e inside).
Signed-off-by Dajie Tan <[email protected]>--- include/asm-mips/pgtable-32.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)include/asm-mips/pgtable-32.h +1
-1@@ -46,7 +46,7 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,#ifdef CONFIG_64BIT_PHYS_ADDR #define PGDIR_SHIFT 21#else -#define PGDIR_SHIFT 22 +#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 2))#endif #define PGDIR_SIZE (1UL << PGDIR_SHIFT)#define PGDIR_MASK (~(PGDIR_SIZE-1))
Quoted 8 lines · Dajie Tan
32-bit Kernel for loongson2e currently use 16KB page size to avoid cache alias problem.So, the definiton of
PGDIR_SHIFTmuse be 12+14.Using 22 in 16K page size do not lead to a serious problem but the number of pages allocated for page table is more than previous. (cat
/proc/vmstat| grepnr_page_table_pages)It's been tested on FuLong mini PC(loongson2e inside).
Looking good, applied. Thanks!
Did by coincidence any of you try 64K pages with a 32-bit kernel?
Ralf
Quoted 10 lines · Ralf Baechle
Quoted 7 lines · Dajie Tan
32-bit Kernel for loongson2e currently use 16KB page size to avoid cache alias problem.So, the definiton of
PGDIR_SHIFTmuse be 12+14.Using 22 in 16K page size do not lead to a serious problem but the number of pages allocated for page table is more than previous. (cat
/proc/vmstat| grepnr_page_table_pages)
Quoted 12 lines
Quoted 2 lines
It's been tested on FuLong mini PC(loongson2e inside).
Looking good, applied. Thanks!
Did by coincidence any of you try 64K pages with a 32-bit kernel?
Ralf
I think the following is more complete?
#ifdef CONFIG_64BIT_PHYS_ADDR
-#define PGDIR_SHIFT 21
+#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3))
#else
-#define PGDIR_SHIFT 22
+#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 2))
#endif
Quoted 9 lines · Songmao Tian
I think the following is more complete?
#ifdef
CONFIG_64BIT_PHYS_ADDR(quoted diff) +1
-1-#define PGDIR_SHIFT 21 +#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3))#else
(quoted diff) +1
-1-#define PGDIR_SHIFT 22 +#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 2))#endif
Better suggestion :-)
Ralf
include/asm-mips/pgtable-32.h +1 -5
@@ -43,11 +43,7 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,*/ /* PGDIR_SHIFT determines what a third-level page table entry can map */ -#ifdef CONFIG_64BIT_PHYS_ADDR -#define PGDIR_SHIFT 21 -#else -#define PGDIR_SHIFT 22 -#endif +#define PGDIR_SHIFT (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2)#define PGDIR_SIZE (1UL << PGDIR_SHIFT)#define PGDIR_MASK (~(PGDIR_SIZE-1))
Quoted 30 lines · Ralf Baechle
Quoted 10 lines · Songmao Tian
I think the following is more complete?
#ifdef
CONFIG_64BIT_PHYS_ADDR(quoted diff) +1
-1-#define PGDIR_SHIFT 21 +#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3))#else
(quoted diff) +1
-1-#define PGDIR_SHIFT 22 +#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 2))#endif
Better suggestion :-)
Ralf
Signed-off-by Ralf Baechle <[email protected]>include/asm-mips/pgtable-32.h +0
-0@@ -43,11 +43,7 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,*/
include/asm-mips/pgtable-32.h extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, · line 49
Quoted 10 lines
include/asm-mips/pgtable-32.h +1
-5/* PGDIR_SHIFT determines what a third-level page table entry can map */ -#ifdef CONFIG_64BIT_PHYS_ADDR -#define PGDIR_SHIFT 21 -#else -#define PGDIR_SHIFT 22 -#endif +#define PGDIR_SHIFT (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2)#define PGDIR_SIZE (1UL << PGDIR_SHIFT)#define PGDIR_MASK (~(PGDIR_SIZE-1))
Sure:)
Tian