Add code to determine the L2 cache size on Sibyte 1250/112x processors.
PATCH 1/1 Add code to determine the L2 cache size on Sibyte 1250/112x processors.
Resend with an actual from header in the email.
Stupid git-send-email...grmbl
Add code to determine the L2 cache size on Sibyte 1250/112x processors.
Signed-off-by Andrew Sharp <[email protected]>
--- arch/mips/mm/c-sb1.c | 70 ++++++++++++++++++++++++++++++++++ include/asm-mips/sibyte/sb1250_l2c.h | 4 ++ 2 files changed, 74 insertions(+), 0 deletions(-)
arch/mips/mm/c-sb1.c +70 -0
@@ -28,6 +28,9 @@#include <asm/mipsregs.h> #include <asm/mmu_context.h> #include <asm/uaccess.h> +#include <asm/sibyte/sb1250.h> +#include <asm/sibyte/sb1250_regs.h> +#include <asm/sibyte/sb1250_l2c.h> extern void sb1_dma_init (void );
@@ -423,6 +426,68 @@ static unsigned int decode_cache_line_size(unsigned int config_field) }/* +* each bit in the 4-bit way-enable field indicates an enabled way +*/ + +static int +decode_l2_ways (u64 l2_misc) +{ +int ways; +int size; + + ways =G_L2C_MISC_NO_WAY (l2_misc) ^0xf ; +if (ways) { +int i; + + size =L2C_NUM_WAYS ; +for (i =0 ; i <4 ; i++) { +if (ways &1 ) { + size -=1 ; + } + ways = ways >>1 ; + } + ways = size; + }else { + ways =L2C_NUM_WAYS ; + } + +return ways; +} + +/* +* 0 = full size: 512KiB on 1250, 256 on 112x +* 1 || 2 = 256KiB +* 5, 6, 9, a = 128 KiB +*/ +static int +decode_l2_size (u64 l2_misc) +{ +int size =0 ; +int ways; + + ways =decode_l2_ways (l2_misc); + + switch _SB_GETVALUE(l2_misc, 4, _SB_MAKEMASK(4, 4)) { +case 0 : +/* line size is 32 bytes on l2 cache */ + size = (L2C_ENTRIES_PER_WAY * ways *32 ) /1024 ; +break ; +case 1 : +case 2 : + size =256 ; +break ; +case 5 : +case 6 : +case 9 : +case 0xa : + size =128 ; +break ; + } + +return size; +} + +/* * Relevant bits of the config1 register format (from the MIPS32/MIPS64 specs) * * 24:22 Icache sets per way
@@ -441,6 +506,7 @@ static char *way_string[] = {static __init void probe_cache_sizes (void ) {u32 config1; +u64 l2_misc; config1 =read_c0_config1 (); icache_line_size =decode_cache_line_size ((config1 >>19 ) &0x7 );
@@ -469,6 +535,10 @@ static __init void probe_cache_sizes(void)printk ("Primary data cache %ldkB, %s, linesize %d bytes.\n" , dcache_size >>10 , way_string[dcache_assoc -1 ], dcache_line_size); + + l2_misc =__raw_readq (IOADDR (A_L2_READ_MISC )); +printk ("Secondary cache %dkB, %s, linesize %d bytes.\n" , +decode_l2_size (l2_misc), way_string[decode_l2_ways (l2_misc) -1 ],32 ); }/*
include/asm-mips/sibyte/sb1250_l2c.h +4 -0
@@ -102,7 +102,11 @@#define A_L2C_MGMT_TAG_BASE 0x00D0000000 +#ifndef CONFIG_SIBYTE_BCM112X #define L2C_ENTRIES_PER_WAY 4096 +#else +#define L2C_ENTRIES_PER_WAY 2048 +#endif #define L2C_NUM_WAYS 4
Signature · 1 line
1.4.4.4
Quoted 1 line · Andrew Sharp
arch/mips/mm/c-sb1.c | 70 ++++++++++++++++++++++++++++++++++
c-sb1.c does no longer exist. The functionality was folded into c-r4k.c and at the same time alot of insanity aka pass 1 workarounds dropped.
Ralf
Quoted 8 lines · On Mon, 3 Dec 2007 19:20:10 +0000 Ralf Baechle <[email protected]> wrote:
Quoted 2 lines · Andrew Sharp
arch/mips/mm/c-sb1.c | 70++++++++++++++++++++++++++++++++++
c-sb1.cdoes no longer exist. The functionality was folded intoc-r4k.cand at the same time alot of insanity aka pass 1 workarounds dropped.
Doh. I knew that, too. Mindlessly trying to clear my patch backlog...