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OMAP clock/powerdomain/SDRC patches for post-2.6.30

PATCH In review Paul Walmsley 4 participants 20 messages May 26, 2009 – Jun 23, 2009

Subsystems (4)
Arm (32-bit) Arm sub-architectures OMAP2+ support OMAP clock framework support
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Paul Walmsley

author maintainer
#0 lore raw

cover OMAP clock/powerdomain/SDRC patches for post-2.6.30

Hello Russell,

here is the next set of OMAP clock patches for review for the post-2.6.30 merge window. They apply on top of the previous set ("OMAP clock/SDRC patches on v2.6.30-rc5"). If you're happy with these patches, Tony will queue them up into his for-next branch.

This series completes basic support for OMAP3 CORE DVFS. A few other minor bugs are fixed by the off-by-one patch and the GPIO debounce clock patch.

regards,

- Paul

---

Paul Walmsley (8):
OMAP3 clock: GPIO de-bounce clocks don't affect module idle state OMAP3 SDRC: set FIXEDDELAY when disabling SDRC DLL
OMAP3 SRAM: convert SRAM code to use macros rather than magic numbers OMAP3 SRAM: add more comments on the SRAM code
OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change OMAP3 clock: add a short delay when lowering CORE clk rate OMAP3 clock: initialize SDRC timings at kernel start OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize

Roel Kluin (1):
OMAP2 clock/powerdomain: off by 1 error in loop timeout comparisons

Tero Kristo (1):
OMAP3: Add support for DPLL3 divisor values higher than 2

 arch/arm/mach-omap2/clock.c            |    2 
 arch/arm/mach-omap2/clock34xx.c        |   42 ++++++++--
 arch/arm/mach-omap2/clock34xx.h        |   12 +--
 arch/arm/mach-omap2/io.c               |   38 +++++++++
 arch/arm/mach-omap2/powerdomain.c      |    2 
 arch/arm/mach-omap2/sram34xx.S         |  129 +++++++++++++++++++++-----------
 arch/arm/plat-omap/include/mach/sram.h |    6 +
 arch/arm/plat-omap/sram.c              |    8 +-
 8 files changed, 171 insertions(+), 68 deletions(-)
author maintainer
#1 lore raw

PATCH 1/10 OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize

The original CDP kernel that this code comes from waited for 0x800 loops after switching the CORE DPLL M2 divider. This does not appear to be necessary.

Signed-off-by Paul Walmsley <[email protected]>
---
 arch/arm/mach-omap2/sram34xx.S |    3 ---
 1 files changed, 0 insertions(+), 3 deletions(-)
arch/arm/mach-omap2/sram34xx.S +0 -3
index c080c82..84781a6 100644
@@ -102,9 +102,6 @@ configure_core_dpll:
 	orr	r12, r12, r3, lsl #0x1B	@ r3 contains the M2 val
 	str	r12, [r11]
 	ldr	r12, [r11]		@ posted-write barrier for CM
-	mov 	r12, #0x800		@ wait for the clock to stabilise
-	cmp	r3, #2
-	bne	wait_clk_stable
 	bx	lr
 wait_clk_stable:
 	subs 	r12, r12, #1
author maintainer
#2 lore raw

PATCH 2/10 OMAP3 clock: initialize SDRC timings at kernel start

In reply to Paul Walmsley

On the OMAP3, initialize SDRC timings when the kernel boots. This ensures that the kernel is running with known, optimized SDRC timings, rather than whatever was configured by the bootloader.

Signed-off-by Paul Walmsley <[email protected]>
---
 arch/arm/mach-omap2/clock34xx.c |    3 ---
 arch/arm/mach-omap2/io.c        |   38 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 38 insertions(+), 3 deletions(-)
arch/arm/mach-omap2/clock34xx.c +0 -3
index 62092f2..a62e326 100644
@@ -715,9 +715,6 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 	if (clk != &dpll3_m2_ck)
 		return -EINVAL;
 
-	if (rate == clk->rate)
-		return 0;
-
 	validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
 	if (validrate != rate)
 		return -EINVAL;
arch/arm/mach-omap2/io.c +38 -0
index 916fcd3..2756f49 100644
@@ -19,6 +19,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/clk.h>
 
 #include <asm/tlb.h>
 

@@ -195,6 +196,40 @@ void __init omap2_map_common_io(void)
 	omapfb_reserve_sdram();
 }
 
+/*
+ * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
+ *
+ * Sets the CORE DPLL3 M2 divider to the same value that it's at
+ * currently.  This has the effect of setting the SDRC SDRAM AC timing
+ * registers to the values currently defined by the kernel.  Currently
+ * only defined for OMAP3; will return 0 if called on OMAP2.  Returns
+ * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
+ * or passes along the return value of clk_set_rate().
+ */
+static int __init _omap2_init_reprogram_sdrc(void)
+{
+	struct clk *dpll3_m2_ck;
+	int v = -EINVAL;
+	long rate;
+
+	if (!cpu_is_omap34xx())
+		return 0;
+
+	dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
+	if (!dpll3_m2_ck)
+		return -EINVAL;
+
+	rate = clk_get_rate(dpll3_m2_ck);
+	pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
+	v = clk_set_rate(dpll3_m2_ck, rate);
+	if (v)
+		pr_err("dpll3_m2_clk rate change failed: %d\n", v);
+
+	clk_put(dpll3_m2_ck);
+
+	return v;
+}
+
 void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
 {
 	omap2_mux_init();

@@ -202,5 +237,8 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
 	clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
 	omap2_clk_init();
 	omap2_sdrc_init(sp);
+
+	_omap2_init_reprogram_sdrc();
+
 	gpmc_init();
 }
author maintainer
#3 lore raw

PATCH 3/10 OMAP3 clock: add a short delay when lowering CORE clk rate

In reply to Paul Walmsley

When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2 divider, add a short delay before returning to SDRAM to allow the SDRC time to stabilize. Without this delay, the system is prone to random panics upon re-entering SDRAM.

This time delay varies based on MPU frequency. At 500MHz MPU frequency at room temperature, 64 loops seems to work okay; so add another 32 loops for environmental and process variation.

Signed-off-by Paul Walmsley <[email protected]>
---
 arch/arm/mach-omap2/clock34xx.c        |   30 ++++++++++++++++++++++++++++--
 arch/arm/mach-omap2/sram34xx.S         |   20 +++++++++-----------
 arch/arm/plat-omap/include/mach/sram.h |    4 ++--
 arch/arm/plat-omap/sram.c              |    8 +++++---
 4 files changed, 44 insertions(+), 18 deletions(-)
arch/arm/mach-omap2/clock34xx.c +28 -2
index a62e326..29d0f07 100644
@@ -283,6 +283,20 @@ static struct omap_clk omap34xx_clks[] = {
 
 #define MIN_SDRC_DLL_LOCK_FREQ		83000000
 
+#define CYCLES_PER_MHZ			1000000
+
+/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
+#define SDRC_MPURATE_SCALE		8
+
+/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
+#define SDRC_MPURATE_BASE_SHIFT		9
+
+/*
+ * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
+ * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
+ */
+#define SDRC_MPURATE_LOOPS		96
+
 /**
  * omap3_dpll_recalc - recalculate DPLL rate
  * @clk: DPLL struct clk

@@ -706,7 +720,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 {
 	u32 new_div = 0;
 	u32 unlock_dll = 0;
-	unsigned long validrate, sdrcrate;
+	u32 c;
+	unsigned long validrate, sdrcrate, mpurate;
 	struct omap_sdrc_params *sp;
 
 	if (!clk || !rate)

@@ -734,6 +749,17 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 		unlock_dll = 1;
 	}
 
+	/*
+	 * XXX This only needs to be done when the CPU frequency changes
+	 */
+	mpurate = arm_fck.rate / CYCLES_PER_MHZ;
+	c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
+	c += 1;  /* for safety */
+	c *= SDRC_MPURATE_LOOPS;
+	c >>= SDRC_MPURATE_SCALE;
+	if (c == 0)
+		c = 1;
+
 	pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
 		 validrate);
 	pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",

@@ -744,7 +770,7 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 
 	/* REVISIT: Add SDRC_MR changing to this code also */
 	omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
-				  sp->actim_ctrlb, new_div, unlock_dll);
+				  sp->actim_ctrlb, new_div, unlock_dll, c);
 
 	return 0;
 }
arch/arm/mach-omap2/sram34xx.S +9 -11
index 84781a6..8d4a88c 100644
@@ -42,10 +42,14 @@
  * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
  * r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for
  *      SDRC rates < 83MHz
+ * r5 = number of MPU cycles to wait for SDRC to stabilize after
+ *      reprogramming the SDRC when switching to a slower MPU speed
+ *
  */
 ENTRY(omap3_sram_configure_core_dpll)
 	stmfd	sp!, {r1-r12, lr}	@ store regs to stack
 	ldr	r4, [sp, #52]		@ pull extra args off the stack
+	ldr	r5, [sp, #56]		@ load extra args from the stack
 	dsb				@ flush buffered writes to interconnect
 	cmp	r3, #0x2
 	blne	configure_sdrc

@@ -59,7 +63,11 @@ ENTRY(omap3_sram_configure_core_dpll)
 	bleq	wait_dll_unlock
 	blne	wait_dll_lock
 	cmp	r3, #0x1
-	blne	configure_sdrc
+	beq	return_to_sdram
+	bl	configure_sdrc
+	mov	r12, r5			@ if slowing, wait for SDRC to stabilize
+	bl	wait_clk_stable
+return_to_sdram:
 	isb				@ prevent speculative exec past here
 	mov 	r0, #0 			@ return value
 	ldmfd	sp!, {r1-r12, pc}	@ restore regs and return

@@ -106,16 +114,6 @@ configure_core_dpll:
 wait_clk_stable:
 	subs 	r12, r12, #1
 	bne	wait_clk_stable
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
 	bx	lr
 enable_sdrc:
 	ldr 	r11, omap3_cm_iclken1_core
arch/arm/plat-omap/include/mach/sram.h +2 -2
index dca7c16..c32fa0a 100644
@@ -24,7 +24,7 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
 				     u32 sdrc_actim_ctrla,
 				     u32 sdrc_actim_ctrlb, u32 m2,
-				     u32 unlock_dll);
+				     u32 unlock_dll, u32 f);
 
 /* Do not use these */
 extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);

@@ -62,7 +62,7 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz;
 extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
 					  u32 sdrc_actim_ctrla,
 					  u32 sdrc_actim_ctrlb, u32 m2,
-					  u32 unlock_dll);
+					  u32 unlock_dll, u32 f);
 extern unsigned long omap3_sram_configure_core_dpll_sz;
 
 #endif
arch/arm/plat-omap/sram.c +5 -3
index 876f5a7..ae3627a 100644
@@ -365,9 +365,11 @@ static inline int omap243x_sram_init(void)
 static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
 					      u32 sdrc_actim_ctrla,
 					      u32 sdrc_actim_ctrlb,
-					      u32 m2, u32 unlock_dll);
+					      u32 m2, u32 unlock_dll,
+					      u32 f);
 u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
-			      u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll)
+			      u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
+			      u32 f)
 {
 	if (!_omap3_sram_configure_core_dpll)
 		omap_sram_error();

@@ -375,7 +377,7 @@ u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
 	return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
 					       sdrc_actim_ctrla,
 					       sdrc_actim_ctrlb, m2,
-					       unlock_dll);
+					       unlock_dll, f);
 }
 
 /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
author maintainer
#4 lore raw

PATCH 4/10 OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change

In reply to Paul Walmsley

Program the SDRC_MR_0 register as well during SDRC clock changes. This register allows selection of the memory CAS latency. Some SDRAM chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency at lower clock rates.

Signed-off-by Paul Walmsley <[email protected]>
---
 arch/arm/mach-omap2/clock34xx.c        |    4 ++--
 arch/arm/mach-omap2/sram34xx.S         |    8 +++++++-
 arch/arm/plat-omap/include/mach/sram.h |    4 ++--
 arch/arm/plat-omap/sram.c              |    6 +++---
 4 files changed, 14 insertions(+), 8 deletions(-)
arch/arm/mach-omap2/clock34xx.c +2 -2
index 29d0f07..5d57047 100644
@@ -768,9 +768,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 	/* REVISIT: SRAM code doesn't support other M2 divisors yet */
 	WARN_ON(new_div != 1 && new_div != 2);
 
-	/* REVISIT: Add SDRC_MR changing to this code also */
 	omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
-				  sp->actim_ctrlb, new_div, unlock_dll, c);
+				  sp->actim_ctrlb, new_div, unlock_dll, c,
+				  sp->mr);
 
 	return 0;
 }
arch/arm/mach-omap2/sram34xx.S +7 -1
index 8d4a88c..d13f1cc 100644
@@ -44,12 +44,14 @@
  *      SDRC rates < 83MHz
  * r5 = number of MPU cycles to wait for SDRC to stabilize after
  *      reprogramming the SDRC when switching to a slower MPU speed
+ * r6 = SDRC_MR_0 register value
  *
  */
 ENTRY(omap3_sram_configure_core_dpll)
 	stmfd	sp!, {r1-r12, lr}	@ store regs to stack
 	ldr	r4, [sp, #52]		@ pull extra args off the stack
 	ldr	r5, [sp, #56]		@ load extra args from the stack
+	ldr	r6, [sp, #60]		@ load extra args from the stack
 	dsb				@ flush buffered writes to interconnect
 	cmp	r3, #0x2
 	blne	configure_sdrc

@@ -151,7 +153,9 @@ configure_sdrc:
 	str	r1, [r11]
 	ldr	r11, omap3_sdrc_actim_ctrlb
 	str	r2, [r11]
-	ldr	r2, [r11]		@ posted-write barrier for SDRC
+	ldr	r11, omap3_sdrc_mr_0
+	str	r6, [r11]
+	ldr	r6, [r11]		@ posted-write barrier for SDRC
 	bx	lr
 
 omap3_sdrc_power:

@@ -168,6 +172,8 @@ omap3_sdrc_actim_ctrla:
 	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
 omap3_sdrc_actim_ctrlb:
 	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
+omap3_sdrc_mr_0:
+	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
 omap3_sdrc_dlla_status:
 	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
 omap3_sdrc_dlla_ctrl:
arch/arm/plat-omap/include/mach/sram.h +2 -2
index c32fa0a..4f87056 100644
@@ -24,7 +24,7 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
 				     u32 sdrc_actim_ctrla,
 				     u32 sdrc_actim_ctrlb, u32 m2,
-				     u32 unlock_dll, u32 f);
+				     u32 unlock_dll, u32 f, u32 sdrc_mr);
 
 /* Do not use these */
 extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);

@@ -62,7 +62,7 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz;
 extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
 					  u32 sdrc_actim_ctrla,
 					  u32 sdrc_actim_ctrlb, u32 m2,
-					  u32 unlock_dll, u32 f);
+					  u32 unlock_dll, u32 f, u32 sdrc_mr);
 extern unsigned long omap3_sram_configure_core_dpll_sz;
 
 #endif
arch/arm/plat-omap/sram.c +3 -3
index ae3627a..81048b3 100644
@@ -366,10 +366,10 @@ static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
 					      u32 sdrc_actim_ctrla,
 					      u32 sdrc_actim_ctrlb,
 					      u32 m2, u32 unlock_dll,
-					      u32 f);
+					      u32 f, u32 sdrc_mr);
 u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
 			      u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
-			      u32 f)
+			      u32 f, u32 sdrc_mr)
 {
 	if (!_omap3_sram_configure_core_dpll)
 		omap_sram_error();

@@ -377,7 +377,7 @@ u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
 	return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
 					       sdrc_actim_ctrla,
 					       sdrc_actim_ctrlb, m2,
-					       unlock_dll, f);
+					       unlock_dll, f, sdrc_mr);
 }
 
 /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
author maintainer
#5 lore raw

PATCH 5/10 OMAP3 SRAM: add more comments on the SRAM code

In reply to Paul Walmsley

Clean up comments and copyrights on the CORE DPLL3 M2 divider change code.

Signed-off-by Paul Walmsley <[email protected]>
---
 arch/arm/mach-omap2/sram34xx.S |   45 +++++++++++++++++++++-------------------
 1 files changed, 24 insertions(+), 21 deletions(-)
arch/arm/mach-omap2/sram34xx.S +24 -21
index d13f1cc..37a1e1f 100644
@@ -3,13 +3,12 @@
  *
  * Omap3 specific functions that need to be run in internal SRAM
  *
- * (C) Copyright 2007
- * Texas Instruments Inc.
- * Rajendra Nayak <[email protected]>
+ * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
+ * Copyright (C) 2008 Nokia Corporation
  *
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
+ * Rajendra Nayak <[email protected]>
  * Richard Woodruff <[email protected]>
+ * Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as

@@ -38,13 +37,16 @@
 	.text
 
 /*
- * Change frequency of core dpll
- * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
- * r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for
+ * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
+ * r0 = new SDRC_RFR_CTRL register contents
+ * r1 = new SDRC_ACTIM_CTRLA register contents
+ * r2 = new SDRC_ACTIM_CTRLB register contents
+ * r3 = new M2 divider setting (only 1 and 2 supported right now)
+ * r4 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
  *      SDRC rates < 83MHz
  * r5 = number of MPU cycles to wait for SDRC to stabilize after
  *      reprogramming the SDRC when switching to a slower MPU speed
- * r6 = SDRC_MR_0 register value
+ * r6 = new SDRC_MR_0 register value
  *
  */
 ENTRY(omap3_sram_configure_core_dpll)

@@ -53,22 +55,22 @@ ENTRY(omap3_sram_configure_core_dpll)
 	ldr	r5, [sp, #56]		@ load extra args from the stack
 	ldr	r6, [sp, #60]		@ load extra args from the stack
 	dsb				@ flush buffered writes to interconnect
-	cmp	r3, #0x2
-	blne	configure_sdrc
-	cmp	r4, #0x1
+	cmp	r3, #0x2		@ if increasing SDRC clk rate,
+	blne	configure_sdrc		@ program the SDRC regs early (for RFR)
+	cmp	r4, #0x1		@ set the intended DLL state
 	bleq	unlock_dll
 	blne	lock_dll
-	bl	sdram_in_selfrefresh	@ put the SDRAM in self refresh
-	bl 	configure_core_dpll
-	bl	enable_sdrc
-	cmp	r4, #0x1
+	bl	sdram_in_selfrefresh	@ put SDRAM in self refresh, idle SDRC
+	bl 	configure_core_dpll	@ change the DPLL3 M2 divider
+	bl	enable_sdrc		@ take SDRC out of idle
+	cmp	r4, #0x1		@ wait for DLL status to change
 	bleq	wait_dll_unlock
 	blne	wait_dll_lock
-	cmp	r3, #0x1
-	beq	return_to_sdram
-	bl	configure_sdrc
-	mov	r12, r5			@ if slowing, wait for SDRC to stabilize
-	bl	wait_clk_stable
+	cmp	r3, #0x1		@ if increasing SDRC clk rate,
+	beq	return_to_sdram		@ return to SDRAM code, otherwise,
+	bl	configure_sdrc		@ reprogram SDRC regs now
+	mov	r12, r5
+	bl	wait_clk_stable		@ wait for SDRC to stabilize
 return_to_sdram:
 	isb				@ prevent speculative exec past here
 	mov 	r0, #0 			@ return value

@@ -93,6 +95,7 @@ sdram_in_selfrefresh:
 	bic 	r12, r12, #0x4		@ clear PWDENA
 	str 	r12, [r11]		@ write back to SDRC_POWER register
 	ldr	r12, [r11]		@ posted-write barrier for SDRC
+idle_sdrc:
 	ldr	r11, omap3_cm_iclken1_core	@ read the CM_ICLKEN1_CORE reg
 	ldr	r12, [r11]
 	bic	r12, r12, #0x2		@ disable iclk bit for SDRC
author maintainer
#6 lore raw

PATCH 6/10 OMAP3 SRAM: convert SRAM code to use macros rather than magic numbers

In reply to Paul Walmsley

Convert omap3_sram_configure_core_dpll() to use macros rather than magic numbers.

Signed-off-by Paul Walmsley <[email protected]>
---
 arch/arm/mach-omap2/sram34xx.S |   53 +++++++++++++++++++++++++++++-----------
 1 files changed, 38 insertions(+), 15 deletions(-)
arch/arm/mach-omap2/sram34xx.S +38 -15
index 37a1e1f..16eb4ef 100644
@@ -36,6 +36,29 @@
 
 	.text
 
+/* r4 parameters */
+#define SDRC_NO_UNLOCK_DLL		0x0
+#define SDRC_UNLOCK_DLL			0x1
+
+/* SDRC_DLLA_CTRL bit settings */
+#define DLLIDLE_MASK			0x4
+
+/* SDRC_DLLA_STATUS bit settings */
+#define LOCKSTATUS_MASK			0x4
+
+/* SDRC_POWER bit settings */
+#define SRFRONIDLEREQ_MASK		0x40
+#define PWDENA_MASK			0x4
+
+/* CM_IDLEST1_CORE bit settings */
+#define ST_SDRC_MASK			0x2
+
+/* CM_ICLKEN1_CORE bit settings */
+#define EN_SDRC_MASK			0x2
+
+/* CM_CLKSEL1_PLL bit settings */
+#define CORE_DPLL_CLKOUT_DIV_SHIFT	0x1b
+
 /*
  * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
  * r0 = new SDRC_RFR_CTRL register contents

@@ -57,13 +80,13 @@ ENTRY(omap3_sram_configure_core_dpll)
 	dsb				@ flush buffered writes to interconnect
 	cmp	r3, #0x2		@ if increasing SDRC clk rate,
 	blne	configure_sdrc		@ program the SDRC regs early (for RFR)
-	cmp	r4, #0x1		@ set the intended DLL state
+	cmp	r4, #SDRC_UNLOCK_DLL	@ set the intended DLL state
 	bleq	unlock_dll
 	blne	lock_dll
 	bl	sdram_in_selfrefresh	@ put SDRAM in self refresh, idle SDRC
 	bl 	configure_core_dpll	@ change the DPLL3 M2 divider
 	bl	enable_sdrc		@ take SDRC out of idle
-	cmp	r4, #0x1		@ wait for DLL status to change
+	cmp	r4, #SDRC_UNLOCK_DLL	@ wait for DLL status to change
 	bleq	wait_dll_unlock
 	blne	wait_dll_lock
 	cmp	r3, #0x1		@ if increasing SDRC clk rate,

@@ -78,33 +101,33 @@ return_to_sdram:
 unlock_dll:
 	ldr	r11, omap3_sdrc_dlla_ctrl
 	ldr	r12, [r11]
-	orr	r12, r12, #0x4
+	orr	r12, r12, #DLLIDLE_MASK
 	str	r12, [r11]		@ (no OCP barrier needed)
 	bx	lr
 lock_dll:
 	ldr	r11, omap3_sdrc_dlla_ctrl
 	ldr	r12, [r11]
-	bic	r12, r12, #0x4
+	bic	r12, r12, #DLLIDLE_MASK
 	str	r12, [r11]		@ (no OCP barrier needed)
 	bx	lr
 sdram_in_selfrefresh:
 	ldr	r11, omap3_sdrc_power	@ read the SDRC_POWER register
 	ldr	r12, [r11]		@ read the contents of SDRC_POWER
 	mov	r9, r12			@ keep a copy of SDRC_POWER bits
-	orr 	r12, r12, #0x40		@ enable self refresh on idle req
-	bic 	r12, r12, #0x4		@ clear PWDENA
+	orr 	r12, r12, #SRFRONIDLEREQ_MASK	@ enable self refresh on idle
+	bic 	r12, r12, #PWDENA_MASK	@ clear PWDENA
 	str 	r12, [r11]		@ write back to SDRC_POWER register
 	ldr	r12, [r11]		@ posted-write barrier for SDRC
 idle_sdrc:
 	ldr	r11, omap3_cm_iclken1_core	@ read the CM_ICLKEN1_CORE reg
 	ldr	r12, [r11]
-	bic	r12, r12, #0x2		@ disable iclk bit for SDRC
+	bic	r12, r12, #EN_SDRC_MASK		@ disable iclk bit for SDRC
 	str 	r12, [r11]
 wait_sdrc_idle:
 	ldr 	r11, omap3_cm_idlest1_core
 	ldr 	r12, [r11]
-	and 	r12, r12, #0x2		@ check for SDRC idle
-	cmp 	r12, #2
+	and 	r12, r12, #ST_SDRC_MASK		@ check for SDRC idle
+	cmp 	r12, #ST_SDRC_MASK
 	bne 	wait_sdrc_idle
 	bx 	lr
 configure_core_dpll:

@@ -112,7 +135,7 @@ configure_core_dpll:
 	ldr	r12, [r11]
 	ldr	r10, core_m2_mask_val	@ modify m2 for core dpll
 	and	r12, r12, r10
-	orr	r12, r12, r3, lsl #0x1B	@ r3 contains the M2 val
+	orr	r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
 	str	r12, [r11]
 	ldr	r12, [r11]		@ posted-write barrier for CM
 	bx	lr

@@ -123,12 +146,12 @@ wait_clk_stable:
 enable_sdrc:
 	ldr 	r11, omap3_cm_iclken1_core
 	ldr	r12, [r11]
-	orr 	r12, r12, #0x2		@ enable iclk bit for SDRC
+	orr 	r12, r12, #EN_SDRC_MASK		@ enable iclk bit for SDRC
 	str 	r12, [r11]
 wait_sdrc_idle1:
 	ldr 	r11, omap3_cm_idlest1_core
 	ldr	r12, [r11]
-	and 	r12, r12, #0x2
+	and 	r12, r12, #ST_SDRC_MASK
 	cmp	r12, #0
 	bne	wait_sdrc_idle1
 restore_sdrc_power_val:

@@ -138,14 +161,14 @@ restore_sdrc_power_val:
 wait_dll_lock:
 	ldr	r11, omap3_sdrc_dlla_status
 	ldr	r12, [r11]
-	and 	r12, r12, #0x4
-	cmp	r12, #0x4
+	and 	r12, r12, #LOCKSTATUS_MASK
+	cmp	r12, #LOCKSTATUS_MASK
 	bne	wait_dll_lock
 	bx	lr
 wait_dll_unlock:
 	ldr	r11, omap3_sdrc_dlla_status
 	ldr	r12, [r11]
-	and	r12, r12, #0x4
+	and	r12, r12, #LOCKSTATUS_MASK
 	cmp	r12, #0x0
 	bne	wait_dll_unlock
 	bx	lr
author maintainer
#7 lore raw

PATCH 7/10 OMAP3: Add support for DPLL3 divisor values higher than 2

In reply to Paul Walmsley

From: Tero Kristo <[email protected]>

Previously only 1 and 2 was supported. This is needed for DVFS VDD2 control.

Signed-off-by Tero Kristo <[email protected]>
---
 arch/arm/mach-omap2/clock34xx.c        |    9 +++------
 arch/arm/mach-omap2/sram34xx.S         |    8 +++++---
 arch/arm/plat-omap/include/mach/sram.h |    6 ++++--
 arch/arm/plat-omap/sram.c              |    6 +++---
 4 files changed, 15 insertions(+), 14 deletions(-)
arch/arm/mach-omap2/clock34xx.c +3 -6
index 5d57047..718a557 100644
@@ -736,9 +736,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 
 	sdrcrate = sdrc_ick.rate;
 	if (rate > clk->rate)
-		sdrcrate <<= ((rate / clk->rate) - 1);
+		sdrcrate <<= ((rate / clk->rate) >> 1);
 	else
-		sdrcrate >>= ((clk->rate / rate) - 1);
+		sdrcrate >>= ((clk->rate / rate) >> 1);
 
 	sp = omap2_sdrc_get_params(sdrcrate);
 	if (!sp)

@@ -765,12 +765,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 	pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
 		 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
 
-	/* REVISIT: SRAM code doesn't support other M2 divisors yet */
-	WARN_ON(new_div != 1 && new_div != 2);
-
 	omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
 				  sp->actim_ctrlb, new_div, unlock_dll, c,
-				  sp->mr);
+				  sp->mr, rate > clk->rate);
 
 	return 0;
 }
arch/arm/mach-omap2/sram34xx.S +5 -3
index 16eb4ef..487fa86 100644
@@ -70,6 +70,7 @@
  * r5 = number of MPU cycles to wait for SDRC to stabilize after
  *      reprogramming the SDRC when switching to a slower MPU speed
  * r6 = new SDRC_MR_0 register value
+ * r7 = increasing SDRC rate? (1 = yes, 0 = no)
  *
  */
 ENTRY(omap3_sram_configure_core_dpll)

@@ -77,9 +78,10 @@ ENTRY(omap3_sram_configure_core_dpll)
 	ldr	r4, [sp, #52]		@ pull extra args off the stack
 	ldr	r5, [sp, #56]		@ load extra args from the stack
 	ldr	r6, [sp, #60]		@ load extra args from the stack
+	ldr	r7, [sp, #64]		@ load extra args from the stack
 	dsb				@ flush buffered writes to interconnect
-	cmp	r3, #0x2		@ if increasing SDRC clk rate,
-	blne	configure_sdrc		@ program the SDRC regs early (for RFR)
+	cmp	r7, #1			@ if increasing SDRC clk rate,
+	bleq	configure_sdrc		@ program the SDRC regs early (for RFR)
 	cmp	r4, #SDRC_UNLOCK_DLL	@ set the intended DLL state
 	bleq	unlock_dll
 	blne	lock_dll

@@ -89,7 +91,7 @@ ENTRY(omap3_sram_configure_core_dpll)
 	cmp	r4, #SDRC_UNLOCK_DLL	@ wait for DLL status to change
 	bleq	wait_dll_unlock
 	blne	wait_dll_lock
-	cmp	r3, #0x1		@ if increasing SDRC clk rate,
+	cmp	r7, #1			@ if increasing SDRC clk rate,
 	beq	return_to_sdram		@ return to SDRAM code, otherwise,
 	bl	configure_sdrc		@ reprogram SDRC regs now
 	mov	r12, r5
arch/arm/plat-omap/include/mach/sram.h +4 -2
index 4f87056..4d53cc5 100644
@@ -24,7 +24,8 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
 				     u32 sdrc_actim_ctrla,
 				     u32 sdrc_actim_ctrlb, u32 m2,
-				     u32 unlock_dll, u32 f, u32 sdrc_mr);
+				     u32 unlock_dll, u32 f, u32 sdrc_mr,
+				     u32 inc);
 
 /* Do not use these */
 extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);

@@ -62,7 +63,8 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz;
 extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
 					  u32 sdrc_actim_ctrla,
 					  u32 sdrc_actim_ctrlb, u32 m2,
-					  u32 unlock_dll, u32 f, u32 sdrc_mr);
+					  u32 unlock_dll, u32 f, u32 sdrc_mr,
+					  u32 inc);
 extern unsigned long omap3_sram_configure_core_dpll_sz;
 
 #endif
arch/arm/plat-omap/sram.c +3 -3
index 81048b3..8ee6cc9 100644
@@ -366,10 +366,10 @@ static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
 					      u32 sdrc_actim_ctrla,
 					      u32 sdrc_actim_ctrlb,
 					      u32 m2, u32 unlock_dll,
-					      u32 f, u32 sdrc_mr);
+					      u32 f, u32 sdrc_mr, u32 inc);
 u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
 			      u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
-			      u32 f, u32 sdrc_mr)
+			      u32 f, u32 sdrc_mr, u32 inc)
 {
 	if (!_omap3_sram_configure_core_dpll)
 		omap_sram_error();

@@ -377,7 +377,7 @@ u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
 	return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
 					       sdrc_actim_ctrla,
 					       sdrc_actim_ctrlb, m2,
-					       unlock_dll, f, sdrc_mr);
+					       unlock_dll, f, sdrc_mr, inc);
 }
 
 /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
author maintainer
#8 lore raw

PATCH 8/10 OMAP3 SDRC: set FIXEDDELAY when disabling SDRC DLL

In reply to Paul Walmsley

Correspondence with the TI OMAP hardware team indicates that SDRC_DLLA_CTRL.FIXEDDELAY should be initialized to 0x0f. This number was apparently derived from process validation. This is only used when the SDRC DLL is unlocked (e.g., SDRC clock frequency less than 83MHz).

Signed-off-by Paul Walmsley <[email protected]>
---
 arch/arm/mach-omap2/sram34xx.S |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)
arch/arm/mach-omap2/sram34xx.S +12 -0
index 487fa86..f41f8d9 100644
@@ -41,8 +41,18 @@
 #define SDRC_UNLOCK_DLL			0x1
 
 /* SDRC_DLLA_CTRL bit settings */
+#define FIXEDDELAY_SHIFT		24
+#define FIXEDDELAY_MASK			(0xff << FIXEDDELAY_SHIFT)
 #define DLLIDLE_MASK			0x4
 
+/*
+ * SDRC_DLLA_CTRL default values: TI hardware team indicates that
+ * FIXEDDELAY should be initialized to 0xf.  This apparently was
+ * empirically determined during process testing, so no derivation
+ * was provided.
+ */
+#define FIXEDDELAY_DEFAULT		(0x0f << FIXEDDELAY_SHIFT)
+
 /* SDRC_DLLA_STATUS bit settings */
 #define LOCKSTATUS_MASK			0x4
 

@@ -103,6 +113,8 @@ return_to_sdram:
 unlock_dll:
 	ldr	r11, omap3_sdrc_dlla_ctrl
 	ldr	r12, [r11]
+	and	r12, r12, #FIXEDDELAY_MASK
+	orr	r12, r12, #FIXEDDELAY_DEFAULT
 	orr	r12, r12, #DLLIDLE_MASK
 	str	r12, [r11]		@ (no OCP barrier needed)
 	bx	lr
author maintainer
#9 lore raw

PATCH 9/10 OMAP3 clock: GPIO de-bounce clocks don't affect module idle state

In reply to Paul Walmsley

GPIO de-bounce clocks don't have any impact on the module idle state, so the clock code should not wait for the module to enable after the de-bounce clocks are enabled.

Problem found by Kevin Hilman <[email protected]>.

Signed-off-by Paul Walmsley <[email protected]>
Signed-off-by Kevin Hilman <[email protected]>
---
 arch/arm/mach-omap2/clock34xx.h |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)
arch/arm/mach-omap2/clock34xx.h +6 -6
index 6763b8f..017a30e 100644
@@ -2182,7 +2182,7 @@ static struct clk wkup_32k_fck = {
 
 static struct clk gpio1_dbck = {
 	.name		= "gpio1_dbck",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_dflt,
 	.parent		= &wkup_32k_fck,
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO1_SHIFT,

@@ -2427,7 +2427,7 @@ static struct clk per_32k_alwon_fck = {
 
 static struct clk gpio6_dbck = {
 	.name		= "gpio6_dbck",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_dflt,
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO6_SHIFT,

@@ -2437,7 +2437,7 @@ static struct clk gpio6_dbck = {
 
 static struct clk gpio5_dbck = {
 	.name		= "gpio5_dbck",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_dflt,
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO5_SHIFT,

@@ -2447,7 +2447,7 @@ static struct clk gpio5_dbck = {
 
 static struct clk gpio4_dbck = {
 	.name		= "gpio4_dbck",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_dflt,
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO4_SHIFT,

@@ -2457,7 +2457,7 @@ static struct clk gpio4_dbck = {
 
 static struct clk gpio3_dbck = {
 	.name		= "gpio3_dbck",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_dflt,
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO3_SHIFT,

@@ -2467,7 +2467,7 @@ static struct clk gpio3_dbck = {
 
 static struct clk gpio2_dbck = {
 	.name		= "gpio2_dbck",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_dflt,
 	.parent		= &per_32k_alwon_fck,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_GPIO2_SHIFT,
author maintainer
#10 lore raw

PATCH 10/10 OMAP2 clock/powerdomain: off by 1 error in loop timeout comparisons

In reply to Paul Walmsley

From: Roel Kluin <[email protected]>

with while (i++ < MAX_CLOCK_ENABLE_WAIT); i can reach MAX_CLOCK_ENABLE_WAIT + 1 after the loop, so if (i == MAX_CLOCK_ENABLE_WAIT) that's still success.

Signed-off-by Roel Kluin <[email protected]>
Signed-off-by Paul Walmsley <[email protected]>
---
 arch/arm/mach-omap2/clock.c       |    2 +-
 arch/arm/mach-omap2/powerdomain.c |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/mach-omap2/clock.c +1 -1
index 076f0a7..3c70c33 100644
@@ -302,7 +302,7 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
 		udelay(1);
 	}
 
-	if (i < MAX_CLOCK_ENABLE_WAIT)
+	if (i <= MAX_CLOCK_ENABLE_WAIT)
 		pr_debug("Clock %s stable after %d loops\n", name, i);
 	else
 		printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
arch/arm/mach-omap2/powerdomain.c +1 -1
index 73e2971..983f1cb 100644
@@ -1099,7 +1099,7 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm)
 	       (c++ < PWRDM_TRANSITION_BAILOUT))
 		udelay(1);
 
-	if (c >= PWRDM_TRANSITION_BAILOUT) {
+	if (c > PWRDM_TRANSITION_BAILOUT) {
 		printk(KERN_ERR "powerdomain: waited too long for "
 		       "powerdomain %s to complete transition\n", pwrdm->name);
 		return -EAGAIN;
maintainer
#11 lore raw
In reply to Paul Walmsley
Quoted 6 lines · Paul Walmsley

Hello Russell,

here is the next set of OMAP clock patches for review for the post-2.6.30 merge window. They apply on top of the previous set ("OMAP clock/SDRC patches on v2.6.30-rc5"). If you're happy with these patches, Tony will queue them up into his for-next branch.

Looks like Russell now has all the omap for-next merged to his devel branch. Only this series is missing and the omap4 SMP patches.

Paul, can you please reply with the output from git request-pull for Russell to pull these in too?

AFAIK, there should not be any need to rebase this series, it should merge clean from v2.6.30-rc7 to Russell's devel branch.

Regards,

Tony

Quoted 42 lines

This series completes basic support for OMAP3 CORE DVFS. A few other minor bugs are fixed by the off-by-one patch and the GPIO debounce clock patch.

regards,

- Paul

---

Paul Walmsley (8):
OMAP3 clock: GPIO de-bounce clocks don't affect module idle state OMAP3 SDRC: set FIXEDDELAY when disabling SDRC DLL
OMAP3 SRAM: convert SRAM code to use macros rather than magic numbers OMAP3 SRAM: add more comments on the SRAM code
OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change OMAP3 clock: add a short delay when lowering CORE clk rate OMAP3 clock: initialize SDRC timings at kernel start OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize

Roel Kluin (1):
OMAP2 clock/powerdomain: off by 1 error in loop timeout comparisons

Tero Kristo (1):
OMAP3: Add support for DPLL3 divisor values higher than 2

 arch/arm/mach-omap2/clock.c            |    2 
 arch/arm/mach-omap2/clock34xx.c        |   42 ++++++++--
 arch/arm/mach-omap2/clock34xx.h        |   12 +--
 arch/arm/mach-omap2/io.c               |   38 +++++++++
 arch/arm/mach-omap2/powerdomain.c      |    2 
 arch/arm/mach-omap2/sram34xx.S         |  129 +++++++++++++++++++++-----------
 arch/arm/plat-omap/include/mach/sram.h |    6 +
 arch/arm/plat-omap/sram.c              |    8 +-
 8 files changed, 171 insertions(+), 68 deletions(-)

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#12 lore raw
Quoted 10 lines · Tony Lindgren
Quoted 6 lines · Paul Walmsley

Hello Russell,

here is the next set of OMAP clock patches for review for the post-2.6.30 merge window. They apply on top of the previous set ("OMAP clock/SDRC patches on v2.6.30-rc5"). If you're happy with these patches, Tony will queue them up into his for-next branch.

Looks like Russell now has all the omap for-next merged to his devel branch. Only this series is missing and the omap4 SMP patches.

This series I've avoided looking at due to lack of time. I only just got around to sorting through your patches from the last two weeks last Thursday/Friday, and I've spent Sunday evening and today boot testing and debugging what's been merged on my LDP platform.

It'll be a week or so before I look at OMAP again.

maintainer
#13 lore raw
Quoted 9 lines · Russell King - ARM Linux
Quoted 8 lines · Tony Lindgren
Quoted 6 lines · Paul Walmsley

Hello Russell,

here is the next set of OMAP clock patches for review for the post-2.6.30 merge window. They apply on top of the previous set ("OMAP clock/SDRC patches on v2.6.30-rc5"). If you're happy with these patches, Tony will queue them up into his for-next branch.

Quoted 7 lines
Quoted 2 lines

Looks like Russell now has all the omap for-next merged to his devel branch. Only this series is missing and the omap4 SMP patches.

This series I've avoided looking at due to lack of time. I only just got around to sorting through your patches from the last two weeks last Thursday/Friday, and I've spent Sunday evening and today boot testing and debugging what's been merged on my LDP platform.

Yeah it's been busy with omap patches again. The good news is that after 2.6.30 we should be able to have linux-omap tree just contain patches for the upcoming merge windows!

Quoted 1 line

It'll be a week or so before I look at OMAP again.

Thanks for the update. Sounds like we still have some time to deal with the remaining two patch sets.

Regards,

Tony

author maintainer
#14 lore raw
In reply to Paul Walmsley

Hello Russell,

Quoted 8 lines · Paul Walmsley

here is the next set of OMAP clock patches for review for the post-2.6.30 merge window. They apply on top of the previous set ("OMAP clock/SDRC patches on v2.6.30-rc5"). If you're happy with these patches, Tony will queue them up into his for-next branch.

This series completes basic support for OMAP3 CORE DVFS. A few other minor bugs are fixed by the off-by-one patch and the GPIO debounce clock patch.

Any comments on these patches?

- Paul

maintainer
#15 lore raw
Quoted 9 lines · Paul Walmsley

Hello Russell,

Quoted 5 lines · Paul Walmsley

here is the next set of OMAP clock patches for review for the post-2.6.30 merge window. They apply on top of the previous set ("OMAP clock/SDRC patches on v2.6.30-rc5"). If you're happy with these patches, Tony will queue them up into his for-next branch.

Quoted 5 lines
Quoted 3 lines

This series completes basic support for OMAP3 CORE DVFS. A few other minor bugs are fixed by the off-by-one patch and the GPIO debounce clock patch.

Any comments on these patches?

Paul, can you please post a git pull request for Russell on these? I think these should still go in if possible.

Russell, if you think it's too late, I'll pile them up into omap for-next branch.

Regards,

Tony

#16 lore raw
Quoted 5 lines · Tony Lindgren

Paul, can you please post a git pull request for Russell on these? I think these should still go in if possible.

Russell, if you think it's too late, I'll pile them up into omap for-next branch.

Let's merge them.

#17 lore raw

Hi Paul, Russell, Tony,

Quoted 8 lines · On Friday 19 June 2009 18:23:42 Russell King - ARM Linux wrote:
Quoted 5 lines · Tony Lindgren

Paul, can you please post a git pull request for Russell on these? I think these should still go in if possible.

Russell, if you think it's too late, I'll pile them up into omap for-next branch.

Let's merge them.

Also, can you look at '[PATCH 0/2] Allows the SDRAM self refresh to work with 2 chip selects' which apply on top of Paul's SDRC patches?

Regards,
Jean

Quoted 5 lines

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author maintainer
#18 lore raw

Hello Jean,

Quoted 11 lines · Jean Pihet
Quoted 8 lines · On Friday 19 June 2009 18:23:42 Russell King - ARM Linux wrote:
Quoted 5 lines · Tony Lindgren

Paul, can you please post a git pull request for Russell on these? I think these should still go in if possible.

Russell, if you think it's too late, I'll pile them up into omap for-next branch.

Let's merge them.

Also, can you look at '[PATCH 0/2] Allows the SDRAM self refresh to work with 2 chip selects' which apply on top of Paul's SDRC patches?

I'll merge these patches into the next SDRC series for Russell and Tony.

thanks,

- Paul

author maintainer
#19 lore raw
In reply to Russell King - ARM Linux

Hello,

Quoted 8 lines · Russell King - ARM Linux
Quoted 5 lines · Tony Lindgren

Paul, can you please post a git pull request for Russell on these? I think these should still go in if possible.

Russell, if you think it's too late, I'll pile them up into omap for-next branch.

Let's merge them.

The following changes since commit cd07ecc828486e5887113c7dc4d9f9022145811b:
Tony Lindgren (1):
Merge branch 'omap4' into for-next

are available in the git repository at:

git://git.pwsan.com/linux-2.6 omap-clock-for-next

Paul Walmsley (7):
OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize OMAP3 clock: initialize SDRC timings at kernel start OMAP3 clock: add a short delay when lowering CORE clk rate OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change OMAP3 SRAM: add more comments on the SRAM code
OMAP3 SRAM: convert SRAM code to use macros rather than magic numbers OMAP3 SDRC: set FIXEDDELAY when disabling SDRC DLL

Roel Kluin (1):
OMAP2 clock/powerdomain: off by 1 error in loop timeout comparisons

Tero Kristo (1):
OMAP3: Add support for DPLL3 divisor values higher than 2

 arch/arm/mach-omap2/clock.c            |    2 +-
 arch/arm/mach-omap2/clock34xx.c        |   42 ++++++++---
 arch/arm/mach-omap2/io.c               |   36 +++++++++
 arch/arm/mach-omap2/powerdomain.c      |    2 +-
 arch/arm/mach-omap2/sram34xx.S         |  129 +++++++++++++++++++++-----------
 arch/arm/plat-omap/include/mach/sram.h |    6 +-
 arch/arm/plat-omap/sram.c              |    8 +-
 7 files changed, 163 insertions(+), 62 deletions(-)

- Paul