Support for LogicPD i.MX27-LITEKIT development board

UART hardware on i.MX27 is the same as on the i.MX31 so we just need to provide the driver with correct address of the registers.

Signed-off-by Ilya Yanok <[email protected]>

---
 drivers/serial/Makefile                        |    2 +-
 drivers/serial/{serial_mx31.c => serial_mxc.c} |   21 +++++++++++++++++++++
 include/configs/imx31_litekit.h                |    2 +-
 include/configs/imx31_phycore.h                |    2 +-
 include/configs/mx31ads.h                      |    2 +-
 include/configs/qong.h                         |    2 +-
 6 files changed, 26 insertions(+), 5 deletions(-)
 rename drivers/serial/{serial_mx31.c => serial_mxc.c} (94%)

drivers/serial/Makefile +1 -1

index 14c818d..9a572e9 100644
@@ -40,7 +40,7 @@ COBJS-$(CONFIG_IXP_SERIAL) += serial_ixp.o
 COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o
 COBJS-$(CONFIG_LPC2292_SERIAL) += serial_lpc2292.o
 COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
-COBJS-$(CONFIG_MX31_UART) += serial_mx31.o
+COBJS-$(CONFIG_MXC_UART) += serial_mxc.o
 COBJS-$(CONFIG_NETARM_SERIAL) += serial_netarm.o
 COBJS-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
 COBJS-$(CONFIG_PL011_SERIAL) += serial_pl01x.o

drivers/serial/serial_mxc.c renamed from drivers/serial/serial_mx31.c +17 -0

similarity index 94%
rename from drivers/serial/serial_mx31.c
rename to drivers/serial/serial_mxc.c
index 7c0682a..acc5b7d 100644
@@ -18,7 +18,12 @@
  */
 
 #include <common.h>
+#ifdef CONFIG_MX31
 #include <asm/arch/mx31.h>
+#else
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#endif
 
 #define __REG(x)     (*((volatile u32 *)(x)))
 

@@ -32,6 +37,18 @@
 #define UART_PHYS 0x43fb0000
 #elif defined(CONFIG_SYS_MX31_UART5)
 #define UART_PHYS 0x43fb4000
+#elif defined(CONFIG_SYS_MX27_UART1)
+#define UART_PHYS 0x1000a000
+#elif defined(CONFIG_SYS_MX27_UART2)
+#define UART_PHYS 0x1000b000
+#elif defined(CONFIG_SYS_MX27_UART3)
+#define UART_PHYS 0x1000c000
+#elif defined(CONFIG_SYS_MX27_UART4)
+#define UART_PHYS 0x1000d000
+#elif defined(CONFIG_SYS_MX27_UART5)
+#define UART_PHYS 0x1001b000
+#elif defined(CONFIG_SYS_MX27_UART6)
+#define UART_PHYS 0x1001c000
 #else
 #error "define CONFIG_SYS_MX31_UARTx to use the mx31 UART driver"
 #endif

Signed-off-by Ilya Yanok <[email protected]>

---
 cpu/arm926ejs/mx27/generic.c |   10 +
 drivers/net/Makefile         |    1 +
 drivers/net/fec_mxc.c        |  742
++++++++++++++++++++++++++++++++++++++++++
 drivers/net/fec_mxc.h        |  304 +++++++++++++++++
 include/netdev.h             |    1 +
 5 files changed, 1058 insertions(+), 0 deletions(-)
 create mode 100644 drivers/net/fec_mxc.c
 create mode 100644 drivers/net/fec_mxc.h

cpu/arm926ejs/mx27/generic.c +1 -0

index bcf7899..7f6fc69 100644
@@ -20,6 +20,7 @@
 
 #include <common.h>
 #include <div64.h>
+#include <netdev.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 

@@ -159,6 +160,15 @@ int print_cpuinfo (void)
 }
 #endif

Signed-off-by Ilya Yanok <[email protected]>

---
 cpu/arm926ejs/mx27/generic.c |   10 +
 drivers/net/Makefile         |    1 +
 drivers/net/fec_mxc.c        |  742 ++++++++++++++++++++++++++++++++++++++++++
 drivers/net/fec_mxc.h        |  304 +++++++++++++++++
 include/netdev.h             |    1 +
 5 files changed, 1058 insertions(+), 0 deletions(-)
 create mode 100644 drivers/net/fec_mxc.c
 create mode 100644 drivers/net/fec_mxc.h

Quoted 11 lines · Ilya Yanok

Signed-off-by Ilya Yanok <[email protected]>

---
 cpu/arm926ejs/mx27/generic.c |   10 +
 drivers/net/Makefile         |    1 +
 drivers/net/fec_mxc.c        |  742 ++++++++++++++++++++++++++++++++++++++++++
 drivers/net/fec_mxc.h        |  304 +++++++++++++++++
 include/netdev.h             |    1 +
 5 files changed, 1058 insertions(+), 0 deletions(-)
 create mode 100644 drivers/net/fec_mxc.c
 create mode 100644 drivers/net/fec_mxc.h

Ben ping

Best Regards,
J.

Signed-off-by Ilya Yanok <[email protected]>

---
 cpu/arm926ejs/mx27/generic.c |   10 +
 drivers/net/Makefile         |    1 +
 drivers/net/fec_mxc.c        |  742 ++++++++++++++++++++++++++++++++++++++++++
 drivers/net/fec_mxc.h        |  304 +++++++++++++++++
 include/netdev.h             |    1 +
 5 files changed, 1058 insertions(+), 0 deletions(-)
 create mode 100644 drivers/net/fec_mxc.c
 create mode 100644 drivers/net/fec_mxc.h

Driver for NFC NAND controller found on Freescale's MX2 and MX3 processors. Ported from Linux. Tested only with i.MX27 but should works with other MX2 and MX3 processors too.

Signed-off-by Ilya Yanok <[email protected]>

---
 drivers/mtd/nand/Makefile   |    1 +
 drivers/mtd/nand/mxc_nand.c |  932 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 933 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/nand/mxc_nand.c

Driver for NFC NAND controller found on Freescale's MX2 and MX3 processors. Ported from Linux. Tested only with i.MX27 but should works with other MX2 and MX3 processors too.

Signed-off-by Ilya Yanok <[email protected]>

drivers/mtd/nand/mxc_nand.c new file +8 -0

+/*
+ * This function requests the NANDFC to perform a read of the
+ * NAND device status and returns the current status.
+ */
+static uint16_t get_dev_status(struct mxc_nand_host *host)
+{
+	void __iomem *main_buf = host->regs->main_area1;
+	uint32_t store;

drivers/mtd/nand/mxc_nand.c new file +18 -0

+static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
+{
+	struct nand_chip *nand_chip = mtd->priv;
+	struct mxc_nand_host *host = nand_chip->priv;
+	uint16_t col, rd_word, ret;
+	uint16_t __iomem *p;
+
+	MTDDEBUG(MTD_DEBUG_LEVEL3,
+	      "mxc_nand_read_word(col = %d)\n", host->col_addr);
+
+	col = host->col_addr;
+	/* Adjust saved column address */
+	if (col < mtd->writesize && host->spare_only)
+		col += mtd->writesize;
+
+	if (col < mtd->writesize) {
+		p = (uint16_t __iomem *)(host->regs->main_area0 + (col >> 1));
+	} else {

drivers/mtd/nand/mxc_nand.c new file +19 -0

+/*
+ * Write data of length len to buffer buf. The data to be
+ * written on NAND Flash is first copied to RAMbuffer. After the Data Input
+ * Operation by the NFC, the data is written to NAND Flash
+ */
+static void mxc_nand_write_buf(struct mtd_info *mtd,
+				const u_char *buf, int len)
+{
+	struct nand_chip *nand_chip = mtd->priv;
+	struct mxc_nand_host *host = nand_chip->priv;
+	int n, col, i = 0;
+
+	MTDDEBUG(MTD_DEBUG_LEVEL3,
+	      "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
+	      len);
+
+	col = host->col_addr;
+
+	/* Adjust saved column address */

drivers/mtd/nand/mxc_nand.c new file +22 -0

+
+			switch (col & 3) {
+			case 0:
+				if (n) {
+					data = (data & 0xffffff00) |
+					    (buf[i++] << 0);
+					n--;
+					col++;
+				}
+			case 1:
+				if (n) {
+					data = (data & 0xffff00ff) |
+					    (buf[i++] << 8);
+					n--;
+					col++;
+				}
+			case 2:
+				if (n) {
+					data = (data & 0xff00ffff) |
+					    (buf[i++] << 16);
+					n--;
+					col++;

drivers/mtd/nand/mxc_nand.c new file +4 -0

+	case NAND_CMD_SEQIN:
+		if (column >= mtd->writesize) {
+			/*
+			 * FIXME: before send SEQIN command for write OOB,

drivers/mtd/nand/mxc_nand.c new file +10 -0

+#ifdef CONFIG_MXC_NAND_HWECC
+	this->ecc.calculate = mxc_nand_calculate_ecc;
+	this->ecc.hwctl = mxc_nand_enable_hwecc;
+	this->ecc.correct = mxc_nand_correct_data;
+	this->ecc.mode = NAND_ECC_HW;
+	this->ecc.size = 512;
+	this->ecc.bytes = 3;
+	this->ecc.layout = &nand_hw_eccoob_8;
+	tmp = readw(&host->regs->nfc_config1);
+	tmp |= NFC_ECC_EN;

Quoted 4 lines

Driver for NFC NAND controller found on Freescale's MX2 and MX3 processors. Ported from Linux. Tested only with i.MX27 but should works with other MX2 and MX3 processors too.

Review

Quoted 11 lines

Signed-off-by Ilya Yanok <[email protected]>

(quoted diff) +10 -0

+static u_char mxc_nand_read_byte(struct mtd_info *mtd)
+{
+ ? ? struct nand_chip *nand_chip = mtd->priv;
+ ? ? struct mxc_nand_host *host = nand_chip->priv;
+ ? ? uint8_t ret = 0;
+ ? ? uint16_t col, rd_word;
+ ? ? uint16_t __iomem *main_buf =
+ ? ? ? ? ? ? (uint16_t __iomem *)host->regs->main_area0;
+ ? ? uint16_t __iomem *spare_buf =
+ ? ? ? ? ? ? (uint16_t __iomem *)host->regs->spare_area0;

According to Magnus Lilja, "the nand flash controller can only handle 32 bit read/write operations, any other size will cause an abort (or something like that)". ?But now we're accessing it as 16-bit?

Hello,

I'm using the imx27lite-v2 branch for our opensource imx27 board. Right now I'm trying to get the nand to work. I'm using a Micron 2Gb x8 part (p/n MT29F2G08ABDHC). When I do "nand info" I get "Device 0: NAND 256MiB 1,8V 8-bit, sector size 128 KiB" which is correct. mtdparts returns:

device nand0 <mxc_nand.0>, # parts = 4

 #: name                size            offset          mask_flags
 0: IPL-SPL             0x00040000      0x00000000      0
 1: kernel              0x00200000      0x00040000      0
 2: rootfs              0x00b00000      0x00240000      0
 3: userfs              0x0f2c0000      0x00d40000      0

active partition: nand0,0 - (IPL-SPL) 0x00040000 @ 0x00000000

defaults:
mtdids : nor0=physmap-flash.0,nand0=mxc_nand.0 mtdparts:
mtdparts=mxc_nand.0:256k(IPL-SPL),2m(kernel),11m(rootfs),-(userfs)

But when I do other commands like fsinfo or ls I get "read_nand_cached:
error reading nand off 0x2000 size 8192 bytes" errors.

My questions are: should the current driver support this chip? Do I need to do anything else to prepare the mtd partitions? Is there a low level test I could run on the NAND?

thanks,
Paul

Please look at drivers/mtd/nand/mpc5121_nfc.c, which AFAICT is very similar hardware, and see if anything can be factored out into common code, and try to keep the rest looking the same except where the hardware actually differs.

drivers/mtd/nand/mxc_nand.c line 148

Quoted 6 lines

drivers/mtd/nand/mxc_nand.c new file +5 -0

+static struct nand_ecclayout nand_hw_eccoob_16 = {
+	.eccbytes = 5,
+	.eccpos = {6, 7, 8, 9, 10},
+	.oobfree = {{0, 6}, {12, 4}, }
+};

This implies the bad block marker is one byte at offset 11 (it's all that's left), but I don't see any override of the bad block pattern.

Quoted 5 lines

drivers/mtd/nand/mxc_nand.c new file +5 -0

+static void *mxc_nand_memcpy32(void *dest, void *source, size_t size)
+{
+	uint32_t *s = source, *d = dest;
+
+	size >>= 2;

drivers/mtd/nand/mxc_nand.c line 158

Quoted 5 lines

drivers/mtd/nand/mxc_nand.c new file +4 -0

+	while (size--)
+		*d++ = *s++;
+	return dest;
+}

This should probably be using I/O accessors (possibly raw) -- and should take uint32_t *, not void *.

Quoted 13 lines

drivers/mtd/nand/mxc_nand.c new file +13 -0

+/*
+ * This function requests the NANDFC to perform a read of the
+ * NAND device status and returns the current status.
+ */
+static uint16_t get_dev_status(struct mxc_nand_host *host)
+{
+	void __iomem *main_buf = host->regs->main_area1;
+	uint32_t store;
+	uint16_t ret, tmp;
+	/* Issue status request to NAND device */
+
+	/* store the main area1 first word, later do recovery */
+	store = readl(main_buf);

drivers/mtd/nand/mxc_nand.c line 318

Quoted 6 lines

drivers/mtd/nand/mxc_nand.c new file +5 -0

+	/*
+	 * NANDFC buffer 1 is used for device status to prevent
+	 * corruption of read/write buffer on status requests.
+	 */
+	writew(1, &host->regs->nfc_buf_addr);

But it looks like buffer 1 is used for data with large page flash.

Other drivers don't seem to have any problem with status reads clobbering the buffer...

drivers/mtd/nand/mxc_nand.c line 341

Quoted 3 lines

drivers/mtd/nand/mxc_nand.c new file +2 -0

+/* This functions is used by upper layer to checks if device is ready */
+static int mxc_nand_dev_ready(struct mtd_info *mtd)

"This functions is"? I'd say this comment is pretty redundant with respect to the function name anyway...

Quoted 7 lines

drivers/mtd/nand/mxc_nand.c new file +7 -0

+static u_char mxc_nand_read_byte(struct mtd_info *mtd)
+{
+	struct nand_chip *nand_chip = mtd->priv;
+	struct mxc_nand_host *host = nand_chip->priv;
+	uint8_t ret = 0;
+	uint16_t col, rd_word;
+	uint16_t __iomem *main_buf =

drivers/mtd/nand/mxc_nand.c line 397

Quoted 4 lines

drivers/mtd/nand/mxc_nand.c new file +3 -0

+		(uint16_t __iomem *)host->regs->main_area0;
+	uint16_t __iomem *spare_buf =
+		(uint16_t __iomem *)host->regs->spare_area0;

According to Magnus Lilja, "the nand flash controller can only handle 32 bit read/write operations, any other size will cause an abort (or something like that)". But now we're accessing it as 16-bit?

Quoted 23 lines

drivers/mtd/nand/mxc_nand.c new file +23 -0

+static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
+{
+	struct nand_chip *nand_chip = mtd->priv;
+	struct mxc_nand_host *host = nand_chip->priv;
+	uint16_t col, rd_word, ret;
+	uint16_t __iomem *p;
+
+	MTDDEBUG(MTD_DEBUG_LEVEL3,
+	      "mxc_nand_read_word(col = %d)\n", host->col_addr);
+
+	col = host->col_addr;
+	/* Adjust saved column address */
+	if (col < mtd->writesize && host->spare_only)
+		col += mtd->writesize;
+
+	if (col < mtd->writesize) {
+		p = (uint16_t __iomem *)(host->regs->main_area0 + (col >> 1));
+	} else {
+		p = (uint16_t __iomem *)(host->regs->spare_area0 +
+				((col - mtd->writesize) >> 1));
+	}
+
+	if (col & 1) {

drivers/mtd/nand/mxc_nand.c line 451

Quoted 6 lines

drivers/mtd/nand/mxc_nand.c new file +5 -0

+		rd_word = readw(p);
+		ret = (rd_word >> 8) & 0xff;
+		rd_word = readw(&p[1]);
+		ret |= (rd_word << 8) & 0xff00;
+

col should never be odd if you're reading words.

Quoted 24 lines

drivers/mtd/nand/mxc_nand.c new file +24 -0

+/*
+ * Write data of length len to buffer buf. The data to be
+ * written on NAND Flash is first copied to RAMbuffer. After the Data Input
+ * Operation by the NFC, the data is written to NAND Flash
+ */
+static void mxc_nand_write_buf(struct mtd_info *mtd,
+				const u_char *buf, int len)
+{
+	struct nand_chip *nand_chip = mtd->priv;
+	struct mxc_nand_host *host = nand_chip->priv;
+	int n, col, i = 0;
+
+	MTDDEBUG(MTD_DEBUG_LEVEL3,
+	      "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
+	      len);
+
+	col = host->col_addr;
+
+	/* Adjust saved column address */
+	if (col < mtd->writesize && host->spare_only)
+		col += mtd->writesize;
+
+	n = mtd->writesize + mtd->oobsize - col;
+	n = min(len, n);

drivers/mtd/nand/mxc_nand.c line 490

Quoted 6 lines

drivers/mtd/nand/mxc_nand.c new file +5 -0

+
+	MTDDEBUG(MTD_DEBUG_LEVEL3,
+	      "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
+
+	while (n) {

Safer to do while (n > 0), especially when the code is this complex.

Quoted 4 lines

drivers/mtd/nand/mxc_nand.c new file +3 -0

+		void __iomem *p;
+
+		if (col < mtd->writesize) {

drivers/mtd/nand/mxc_nand.c line 503

Quoted 10 lines

drivers/mtd/nand/mxc_nand.c new file +10 -0

+			p = host->regs->main_area0 + (col & ~3);
+		} else {
+			p = host->regs->spare_area0 -
+						mtd->writesize + (col & ~3);
+		}
+
+		MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
+		      __LINE__, p);
+
+		if (((col | (int)&buf[i]) & 3) || n < 16) {

Do not cast pointers to "int". Use "uintptr_t" or "unsigned long" if you must.

Why < 16 and not < 4?

drivers/mtd/nand/mxc_nand.c line 507

Quoted 5 lines

drivers/mtd/nand/mxc_nand.c new file +4 -0

+			uint32_t data = 0;
+
+			if (col & 3 || n < 4)
+				data = readl(p);

If that condition doesn't hold, the data we use is zero?

Quoted 23 lines

drivers/mtd/nand/mxc_nand.c new file +22 -0

+
+			switch (col & 3) {
+			case 0:
+				if (n) {
+					data = (data & 0xffffff00) |
+					    (buf[i++] << 0);
+					n--;
+					col++;
+				}
+			case 1:
+				if (n) {
+					data = (data & 0xffff00ff) |
+					    (buf[i++] << 8);
+					n--;
+					col++;
+				}
+			case 2:
+				if (n) {
+					data = (data & 0xff00ffff) |
+					    (buf[i++] << 16);
+					n--;
+					col++;

drivers/mtd/nand/mxc_nand.c line 540

Quoted 10 lines

drivers/mtd/nand/mxc_nand.c new file +10 -0

+				}
+			case 3:
+				if (n) {
+					data = (data & 0x00ffffff) |
+					    (buf[i++] << 24);
+					n--;
+					col++;
+				}
+			}
+			writel(data, p);

Might I suggest this?

union {
	uint32_t word;
	uint8_t bytes[4];
} nfc_word;

nfc_word.word = readl(p);
nfc_word.bytes[col & 3] = buf[i++];
n--;
col++;

writel(nfc_word.word, p);

As a side benefit, you lose the endian dependency.

drivers/mtd/nand/mxc_nand.c line 553

Quoted 2 lines

drivers/mtd/nand/mxc_nand.c new file +1 -0

+			mxc_nand_memcpy32(p, (void *)&buf[i], m);

Unnecessary cast.

drivers/mtd/nand/mxc_nand.c line 594

Quoted 5 lines

drivers/mtd/nand/mxc_nand.c new file +4 -0

+	/* Update saved column address */
+	host->col_addr = col;
+
+}

No blank lines before the brace at the end of a block.

Quoted 5 lines

drivers/mtd/nand/mxc_nand.c new file +5 -0

+
+/*
+ * Used by the upper layer to verify the data in NAND Flash
+ * with the data in the buf.
+ */

drivers/mtd/nand/mxc_nand.c line 653

Quoted 6 lines

drivers/mtd/nand/mxc_nand.c new file +5 -0

+static int mxc_nand_verify_buf(struct mtd_info *mtd,
+				const u_char *buf, int len)
+{
+	return -EFAULT;
+}

Umm...

Quoted 11 lines

drivers/mtd/nand/mxc_nand.c new file +11 -0

+	case NAND_CMD_SEQIN:
+		if (column >= mtd->writesize) {
+			/*
+			 * FIXME: before send SEQIN command for write OOB,
+			 * We must read one page out.
+			 * For K9F1GXX has no READ1 command to set current HW
+			 * pointer to spare area, we must write the whole page
+			 * including OOB together.
+			 */
+			if (host->pagesize_2k) {
+				/* call ourself to read a page */

drivers/mtd/nand/mxc_nand.c line 748

Quoted 4 lines

drivers/mtd/nand/mxc_nand.c new file +3 -0

+				mxc_nand_command(mtd, NAND_CMD_READ0, 0,
+						page_addr);
+			}

Should this be #ifdef HWECC? And update the comment to indicate the actual problem, which is the unusual hardware ECC implementation. I don't see what the lack of a "READ1" command has to do with it.

And is this actually a FIXME if it's already being done?

Quoted 11 lines

drivers/mtd/nand/mxc_nand.c new file +10 -0

+#ifdef CONFIG_MXC_NAND_HWECC
+	this->ecc.calculate = mxc_nand_calculate_ecc;
+	this->ecc.hwctl = mxc_nand_enable_hwecc;
+	this->ecc.correct = mxc_nand_correct_data;
+	this->ecc.mode = NAND_ECC_HW;
+	this->ecc.size = 512;
+	this->ecc.bytes = 3;
+	this->ecc.layout = &nand_hw_eccoob_8;
+	tmp = readw(&host->regs->nfc_config1);
+	tmp |= NFC_ECC_EN;

drivers/mtd/nand/mxc_nand.c line 904

Quoted 10 lines

drivers/mtd/nand/mxc_nand.c new file +10 -0

+	writew(tmp, &host->regs->nfc_config1);
+#else
+	this->ecc.size = 512;
+	this->ecc.bytes = 3;
+	this->ecc.layout = &nand_hw_eccoob_8;
+	this->ecc.mode = NAND_ECC_SOFT;
+	tmp = readw(&host->regs->nfc_config1);
+	tmp &= ~NFC_ECC_EN;
+	writew(tmp, &host->regs->nfc_config1);
+#endif

Soft ECC only supports 256-byte ECC blocks (anything you set here to the contrary will just be overwritten), and you'll need a layout that accommodates that with enough ECC bytes.

Alternatively, you can implement 512-byte soft ECC if you don't want to waste those 3 extra OOB bytes. :-)

drivers/mtd/nand/mxc_nand.c line 928

Quoted 2 lines

drivers/mtd/nand/mxc_nand.c new file +1 -0

+	host->pagesize_2k = 0;

So large page is currently unsupported?

Driver for NFC NAND controller found on Freescale's MX2 and MX3 processors. Ported from Linux. Tested only with i.MX27 but should works with other MX2 and MX3 processors too.

Signed-off-by Ilya Yanok <[email protected]>

---
 drivers/mtd/nand/Makefile   |    1 +
 drivers/mtd/nand/mxc_nand.c |  902 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 903 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/nand/mxc_nand.c

drivers/mtd/nand/mxc_nand.c new file +4 -0

+/* OOB placement block for use with hardware ecc generation */
+static struct nand_ecclayout nand_hw_eccoob = {
+	.eccbytes = 5,
+	.eccpos = {6, 7, 8, 9, 10},

drivers/mtd/nand/mxc_nand.c new file +5 -0

+	/*
+	 * NANDFC buffer 1 is used for device status to prevent
+	 * corruption of read/write buffer on status requests.
+	 */
+	writew(1, &host->regs->nfc_buf_addr);

Driver for NFC NAND controller found on Freescale's MX2 and MX3 processors. Ported from Linux. Tested only with i.MX27 but should works with other MX2 and MX3 processors too.

Signed-off-by Ilya Yanok <[email protected]>

Quoted 9 lines

drivers/mtd/nand/mxc_nand.c new file +9 -0

+/* OOB placement block for use with hardware ecc generation */
+static struct nand_ecclayout nand_hw_eccoob = {
+	.eccbytes = 5,
+	.eccpos = {6, 7, 8, 9, 10},
+	.oobfree = {{0, 5}, {11, 5}, }
+};
+
+#ifndef CONFIG_MXC_NAND_HWECC
+static struct nand_ecclayout nand_hw_eccoob_soft = {

drivers/mtd/nand/mxc_nand.c line 150

Quoted 6 lines

drivers/mtd/nand/mxc_nand.c new file +5 -0

+	.eccbytes = 6,
+	.eccpos = {6, 7, 8, 9, 10, 11},
+	.oobfree = {{0, 5}, {12, 4}, }
+};
+#endif

Why is one struct #ifndef, but the other isn't #ifdef?

Quoted 6 lines

drivers/mtd/nand/mxc_nand.c new file +6 -0

+/*
+ * This function requests the NANDFC to initate the transfer
+ * of data currently in the NANDFC RAM buffer to the NAND device.
+ */
+static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
+			int spare_only)

drivers/mtd/nand/mxc_nand.c line 227

Quoted 6 lines

drivers/mtd/nand/mxc_nand.c new file +5 -0

+{
+	MTDDEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", spare_only);
+
+	/* NANDFC buffer 0 is used for page read/write */
+	writew(buf_id, &host->regs->nfc_buf_addr);

Comment does not match code.

drivers/mtd/nand/mxc_nand.c line 320

Quoted 6 lines

drivers/mtd/nand/mxc_nand.c new file +5 -0

+	/*
+	 * NANDFC buffer 1 is used for device status to prevent
+	 * corruption of read/write buffer on status requests.
+	 */
+	writew(1, &host->regs->nfc_buf_addr);

From discussion on the previous patch:

Quoted 5 lines

Quoted 3 lines

But it looks like buffer 1 is used for data with large page flash.

Well, we save first word of the buffer and then recover it.

So then there's no longer any special reason to use buffer 1 for status, and that comment is misleading...

Quoted 26 lines

drivers/mtd/nand/mxc_nand.c new file +26 -0

+static u_char mxc_nand_read_byte(struct mtd_info *mtd)
+{
+	struct nand_chip *nand_chip = mtd->priv;
+	struct mxc_nand_host *host = nand_chip->priv;
+	uint8_t ret = 0;
+	uint16_t col, rd_word;
+	uint16_t __iomem *main_buf =
+		(uint16_t __iomem *)host->regs->main_area0;
+	uint16_t __iomem *spare_buf =
+		(uint16_t __iomem *)host->regs->spare_area0;
+
+	/* Check for status request */
+	if (host->status_request)
+		return get_dev_status(host) & 0xFF;
+
+	/* Get column for 16-bit access */
+	col = host->col_addr >> 1;
+
+	/* If we are accessing the spare region */
+	if (host->spare_only)
+		rd_word = readw(&spare_buf[col]);
+	else
+		rd_word = readw(&main_buf[col]);
+
+	/* Pick upper/lower byte of word from RAM buffer */
+	if (host->col_addr & 0x1)

drivers/mtd/nand/mxc_nand.c line 418

Quoted 4 lines

drivers/mtd/nand/mxc_nand.c new file +3 -0

+		ret = (rd_word >> 8) & 0xFF;
+	else
+		ret = rd_word & 0xFF;

Use a union, as in read_buf(). Otherwise, this breaks on big-endian -- you may not care, but it's better to not have such dependencies lurking in the code that could be reused who-knows-where.

drivers/mtd/nand/mxc_nand.c line 452

Quoted 6 lines

drivers/mtd/nand/mxc_nand.c new file +5 -0

+	if (col & 1) {
+		rd_word = readw(p);
+		ret = (rd_word >> 8) & 0xff;
+		rd_word = readw(&p[1]);
+		ret |= (rd_word << 8) & 0xff00;

Again, this is unnecessary, but if you insist, use a union.

drivers/mtd/nand/mxc_nand.c line 636

Quoted 5 lines

drivers/mtd/nand/mxc_nand.c new file +4 -0

+#ifdef CONFIG_MTD_NAND_MXC_FORCE_CE
+	if (chip > 0) {
+		MTDDEBUG(MTD_DEBUG_LEVEL0,
+		      "ERROR:  Illegal chip select (chip = %d)\n", chip);

If it's an error, that's not exactly debug (especially since there's no way to propagate the error upwards)...

Quoted 7 lines

drivers/mtd/nand/mxc_nand.c new file +7 -0

+		return;
+	}
+
+	if (chip == -1) {
+		writew(readw(&host->regs->nfc_config1) & ~NFC_CE,
+				&host->regs->nfc_config1);
+		return;

drivers/mtd/nand/mxc_nand.c line 648

Quoted 6 lines

drivers/mtd/nand/mxc_nand.c new file +5 -0

+	}
+
+	writew(readw(&host->regs->nfc_config1) | NFC_CE,
+			&host->regs->nfc_config1);
+#endif

#else?

Quoted 8 lines

drivers/mtd/nand/mxc_nand.c new file +8 -0

+		if (column >= mtd->writesize) {
+			/*
+			 * before sending SEQIN command for partial write,
+			 * we need read one page out. FSL NFC does not support
+			 * partial write. It alway send out 512+ecc+512+ecc ...
+			 * for large page nand flash. But for small page nand
+			 * flash, it does support SPARE ONLY operation.
+			 */

drivers/mtd/nand/mxc_nand.c line 717

Quoted 6 lines

drivers/mtd/nand/mxc_nand.c new file +5 -0

+			if (host->pagesize_2k) {
+				/* call ourself to read a page */
+				mxc_nand_command(mtd, NAND_CMD_READ0, 0,
+						page_addr);
+			}

#ifdef CONFIG_MXC_NAND_HWECC?

drivers/mtd/nand/mxc_nand.c line 845

Quoted 3 lines

drivers/mtd/nand/mxc_nand.c new file +2 -0

+	/* 50 us command delay time */
+	this->chip_delay = 5;

5 or 50?

drivers/mtd/nand/mxc_nand.c line 899

Quoted 2 lines

drivers/mtd/nand/mxc_nand.c new file +1 -0

+	host->pagesize_2k = 0;

Make this board-configurable. Has large page been tested? If not, perhaps it should stay out for now, given how weird it is on this controller.

Quoted 7 lines

Quoted 7 lines

drivers/mtd/nand/mxc_nand.c new file +7 -0

+		return;
+	}
+
+	if (chip == -1) {
+		writew(readw(&host->regs->nfc_config1) & ~NFC_CE,
+				&host->regs->nfc_config1);
+		return;

Quoted 9 lines

drivers/mtd/nand/mxc_nand.c line 648

Quoted 6 lines

drivers/mtd/nand/mxc_nand.c new file +5 -0

+	}
+
+	writew(readw(&host->regs->nfc_config1) | NFC_CE,
+			&host->regs->nfc_config1);
+#endif

#else?

For me it just works (I've never defined CONFIG_MTD_NAND_MXC_FORCE_CE).

Quoted 8 lines

Quoted 8 lines

drivers/mtd/nand/mxc_nand.c new file +8 -0

+		if (column >= mtd->writesize) {
+			/*
+			 * before sending SEQIN command for partial write,
+			 * we need read one page out. FSL NFC does not support
+			 * partial write. It alway send out 512+ecc+512+ecc ...
+			 * for large page nand flash. But for small page nand
+			 * flash, it does support SPARE ONLY operation.
+			 */

Quoted 9 lines

drivers/mtd/nand/mxc_nand.c line 717

Quoted 6 lines

drivers/mtd/nand/mxc_nand.c new file +5 -0

+			if (host->pagesize_2k) {
+				/* call ourself to read a page */
+				mxc_nand_command(mtd, NAND_CMD_READ0, 0,
+						page_addr);
+			}

#ifdef CONFIG_MXC_NAND_HWECC?

Uh... I have to admit I don't really have clear understanding of this problem and I can't find it's description in i.MX27 Reference Manual... Maybe you can point me in some direction? For now I'm not sure if putting this under #ifdef won't break something...

Quoted 5 lines · Scott Wood

Please look at drivers/mtd/nand/mpc5121_nfc.c, which AFAICT is very similar hardware, and see if anything can be factored out into common code, and try to keep the rest looking the same except where the hardware actually differs.

Hmm... For now we just can't spend enough effort for this...

Quoted 13 lines

Quoted 13 lines

drivers/mtd/nand/mxc_nand.c new file +13 -0

+/*
+ * This function requests the NANDFC to perform a read of the
+ * NAND device status and returns the current status.
+ */
+static uint16_t get_dev_status(struct mxc_nand_host *host)
+{
+	void __iomem *main_buf = host->regs->main_area1;
+	uint32_t store;
+	uint16_t ret, tmp;
+	/* Issue status request to NAND device */
+
+	/* store the main area1 first word, later do recovery */
+	store = readl(main_buf);

Quoted 9 lines

drivers/mtd/nand/mxc_nand.c line 318

Quoted 6 lines

drivers/mtd/nand/mxc_nand.c new file +5 -0

+	/*
+	 * NANDFC buffer 1 is used for device status to prevent
+	 * corruption of read/write buffer on status requests.
+	 */
+	writew(1, &host->regs->nfc_buf_addr);

But it looks like buffer 1 is used for data with large page flash.

Well, we save first word of the buffer and then recover it.

Quoted 2 lines

Other drivers don't seem to have any problem with status reads clobbering the buffer...

Quoted 4 lines

According to Magnus Lilja, "the nand flash controller can only handle 32 bit read/write operations, any other size will cause an abort (or something like that)". But now we're accessing it as 16-bit?

16-bit accesses work quite well. Problem was with 8-bit accesses.

Quoted 2 lines

col should never be odd if you're reading words.

It can be odd if previously we've read a byte.

Quoted 5 lines

drivers/mtd/nand/mxc_nand.c line 928

Quoted 2 lines

drivers/mtd/nand/mxc_nand.c new file +1 -0

+	host->pagesize_2k = 0;

So large page is currently unsupported?

Linux driver was fixed recently and now it claims to support 2K page size... I've added all needed fixes but I can understand how this driver should detect the pagesize... Linux driver calls nand_scan_ident() itself for this... Do you think I can calls nand_scan_ident() from my board_nand_init() function?

This is a port of Linux driver for SDHC host controller hardware found on Freescale's MX2 and MX3 processors. Uses new generic MMC framework (CONFIG_GENERIC_MMC) and it looks like there are some problems with a framework (at least on LE cpus). Some of these problems are addressed in the following patches.

Signed-off-by Ilya Yanok <[email protected]>

---

This is a port of Linux driver for SDHC host controller hardware found on Freescale's MX2 and MX3 processors. Uses new generic MMC framework (CONFIG_GENERIC_MMC) and it looks like there are some problems with a framework (at least on LE cpus). Some of these problems are addressed in the following patches.

This is a port of Linux driver for SDHC host controller hardware found on Freescale's MX2 and MX3 processors. Uses new generic MMC framework (CONFIG_GENERIC_MMC) and it looks like there are some problems with a framework (at least on LE cpus). Some of these problems are addressed in the following patches.

Signed-off-by Ilya Yanok <[email protected]>

---
 cpu/arm926ejs/mx27/generic.c       |   16 ++
 drivers/mmc/Makefile               |    1 +
 drivers/mmc/mxcmmc.c               |  523 ++++++++++++++++++++++++++++++++++++
 include/asm-arm/arch-mx27/mxcmmc.h |   25 ++
 4 files changed, 565 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mmc/mxcmmc.c
 create mode 100644 include/asm-arm/arch-mx27/mxcmmc.h

Signed-off-by Ilya Yanok <[email protected]>

---
 lib_arm/board.c |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

This patch adds support for i.MX27-LITEKIT development board from LogicPD. This board uses i.MX27 SoC and has 2MB NOR flash, 64MB NAND flash, FEC ethernet controller integrated into i.MX27.

Signed-off-by Ilya Yanok <[email protected]>

---
 MAINTAINERS                             |    1 +
 MAKEALL                                 |    1 +
 Makefile                                |    3 +
 board/logicpd/imx27lite/Makefile        |   51 +++++++
 board/logicpd/imx27lite/config.mk       |    1 +
 board/logicpd/imx27lite/imx27lite.c     |   97 +++++++++++++
 board/logicpd/imx27lite/lowlevel_init.S |  223 +++++++++++++++++++++++++++++++
 board/logicpd/imx27lite/u-boot.lds      |   56 ++++++++
 include/configs/imx27lite.h             |  195 +++++++++++++++++++++++++++
 9 files changed, 628 insertions(+), 0 deletions(-)
 create mode 100644 board/logicpd/imx27lite/Makefile
 create mode 100644 board/logicpd/imx27lite/config.mk
 create mode 100644 board/logicpd/imx27lite/imx27lite.c
 create mode 100644 board/logicpd/imx27lite/lowlevel_init.S
 create mode 100644 board/logicpd/imx27lite/u-boot.lds
 create mode 100644 include/configs/imx27lite.h

MAINTAINERS +0 -0

index 3d50668..98efd69 100644

MAINTAINERS +0 -0

 	qong		i.MX31
 
 Thomas Elste <[email protected]>

MAKEALL +1 -0

index 57dd425..2aaec13 100755
@@ -504,6 +504,7 @@ LIST_ARM9="			\
 	cp926ejs		\
 	cp946es			\
 	cp966			\
+	imx27lite		\
 	lpd7a400		\
 	mx1ads			\
 	mx1fs2			\

board/logicpd/imx27lite/imx27lite.c new file +29 -0

new file mode 100644
index 0000000..7c2658c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2007 Sascha Hauer, Pengutronix
+ * Copyright (C) 2008,2009 Eric Jarrige <[email protected]>
+ * Copyright (C) 2009 Ilya Yanok <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int imx27lite_devices_init(void)
+{

board/logicpd/imx27lite/imx27lite.c new file +30 -0

+		PD8_AF_FEC_MDIO,
+		PD9_AIN_FEC_MDC | GPIO_PUEN,
+		PD10_AOUT_FEC_CRS,
+		PD11_AOUT_FEC_TX_CLK,
+		PD12_AOUT_FEC_RXD0,
+		PD13_AOUT_FEC_RX_DV,
+		PD14_AOUT_FEC_CLR,
+		PD15_AOUT_FEC_COL,
+		PD16_AIN_FEC_TX_ER,
+		PF23_AIN_FEC_TX_EN,
+		PE12_PF_UART1_TXD,
+		PE13_PF_UART1_RXD,
+		PB4_PF_SD2_D0,
+		PB5_PF_SD2_D1,
+		PB6_PF_SD2_D2,
+		PB7_PF_SD2_D3,
+		PB8_PF_SD2_CMD,
+		PB9_PF_SD2_CLK,
+	};
+
+	for (i = 0; i < ARRAY_SIZE(mode); i++)
+		imx_gpio_mode(mode[i]);
+
+	return 0;
+}
+
+int board_init (void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_IMX27LITE;
+	gd->bd->bi_boot_params = 0xa0000100;

board/logicpd/imx27lite/imx27lite.c new file +18 -0

+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1,
+			PHYS_SDRAM_1_SIZE);
+#endif
+#if ( CONFIG_NR_DRAM_BANKS > 1 )
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = get_ram_size((volatile void *)PHYS_SDRAM_2,
+			PHYS_SDRAM_2_SIZE);
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("LogicPD imx27lite\n");
+	return 0;
+}

board/logicpd/imx27lite/lowlevel_init.S new file +61 -0

new file mode 100644
index 0000000..ba02ad4
@@ -0,0 +1,223 @@
+/*
+ * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
+ * Applications Processor Reference Manual, Rev. 0.2".
+ *
+ * (C) Copyright 2008 Eric Jarrige <[email protected]>
+ * (C) Copyright 2009 Ilya Yanok <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/asm-offsets.h>
+
+#define SDRAM_ESDCFG_REGISTER_VAL(cas)	\
+		(ESDCFG_TRC(10) |	\
+		ESDCFG_TRCD(3) |	\
+		ESDCFG_TCAS(cas) |	\
+		ESDCFG_TRRD(1) |	\
+		ESDCFG_TRAS(5) |	\
+		ESDCFG_TWR |		\
+		ESDCFG_TMRD(2) |	\
+		ESDCFG_TRP(2) |		\
+		ESDCFG_TXP(3))
+
+#define SDRAM_ESDCTL_REGISTER_VAL	\
+		(ESDCTL_PRCT(0) |	\
+		 ESDCTL_BL |		\
+		 ESDCTL_PWDT(0) |	\
+		 ESDCTL_SREFR(3) |	\
+		 ESDCTL_DSIZ_32 |	\
+		 ESDCTL_COL10 |		\
+		 ESDCTL_ROW13 |		\
+		 ESDCTL_SDE)
+
+#define SDRAM_ALL_VAL		0xf00
+
+#define SDRAM_MODE_REGISTER_VAL	0x33	/* BL: 8, CAS: 3 */
+#define SDRAM_EXT_MODE_REGISTER_VAL	0x1000000
+
+#define MPCTL0_VAL	0x1ef15d5
+
+#define SPCTL0_VAL	0x043a1c09
+
+#define CSCR_VAL	0x33f08107
+

board/logicpd/imx27lite/lowlevel_init.S new file +4 -0

+
+SOC_ESDCTL_BASE_W:	.word	IMX_ESD_BASE
+SOC_SI_ID_REG_W:	.word	IMX_SYSTEM_CTL_BASE
+SDRAM_ESDCFG_T1_W:	.word	SDRAM_ESDCFG_REGISTER_VAL(0)

board/logicpd/imx27lite/lowlevel_init.S new file +42 -0

+	/*
+	 * setup AIPI1 and AIPI2
+	 */
+	writel(AIPI1_PSR0, AIPI1_PSR0_VAL)
+	writel(AIPI1_PSR1, AIPI1_PSR1_VAL)
+	writel(AIPI2_PSR0, AIPI2_PSR0_VAL)
+	writel(AIPI2_PSR1, AIPI2_PSR1_VAL)
+
+	.endm /* init_aipi */
+
+	.macro init_clock
+	ldr r0, =CSCR
+	/* disable MPLL/SPLL first */
+	ldr r1, [r0]
+	bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
+	str r1, [r0]
+
+	writel(MPCTL0, MPCTL0_VAL)
+	writel(SPCTL0, SPCTL0_VAL)
+
+	writel(CSCR, CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART)
+
+	/*
+	 * add some delay here
+	 */
+	mov r1, #0x1000
+1:	subs r1, r1, #0x1
+	bne 1b
+
+	/* peripheral clock divider */
+	writel(PCDR0, PCDR0_VAL)
+	writel(PCDR1, PCDR1_VAL)
+
+	/* Configure PCCR0 and PCCR1 */
+	writel(PCCR0, PCCR0_VAL)
+	writel(PCCR1, PCCR1_VAL)
+
+	.endm /* init_clock */
+
+	.macro sdram_init
+	ldr r0, SOC_ESDCTL_BASE_W
+	mov r2, #PHYS_SDRAM_1

board/logicpd/imx27lite/lowlevel_init.S new file +60 -0

+
+	/* Activate LPDDR iface */
+	mov r1, #ESDMISC_MDDREN
+	str r1, [r0, #ESDMISC_ROF]
+
+	/* Check The chip version TO1 or TO2 */
+	ldr r1, SOC_SI_ID_REG_W
+	ldr r1, [r1]
+	ands r1, r1, #0xF0000000
+	/* add Latency on CAS only for TO2 */
+	ldreq r1, SDRAM_ESDCFG_T2_W
+	ldrne r1, SDRAM_ESDCFG_T1_W
+	str r1, [r0, #ESDCFG0_ROF]
+
+	/* Run initialization sequence */
+	ldr r1, SDRAM_PRECHARGE_CMD_W
+	str r1, [r0, #ESDCTL0_ROF]
+	ldr r1, [r2, #SDRAM_ALL_VAL]
+
+	ldr r1, SDRAM_AUTOREF_CMD_W
+	str r1, [r0, #ESDCTL0_ROF]
+	ldr r1, [r2, #SDRAM_ALL_VAL]
+	ldr r1, [r2, #SDRAM_ALL_VAL]
+
+	ldr r1, SDRAM_LOADMODE_CMD_W
+	str r1, [r0, #ESDCTL0_ROF]
+	ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
+	add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
+	ldrb r1, [r3]
+
+	ldr r1, SDRAM_NORMAL_CMD_W
+	str r1, [r0, #ESDCTL0_ROF]
+
+#if (CONFIG_NR_DRAM_BANKS > 1)
+	/* 2nd sdram */
+	mov r2, #PHYS_SDRAM_2
+
+	/* Check The chip version TO1 or TO2 */
+	ldr r1, SOC_SI_ID_REG_W
+	ldr r1, [r1]
+	ands r1, r1, #0xF0000000
+	/* add Latency on CAS only for TO2 */
+	ldreq r1, SDRAM_ESDCFG_T2_W
+	ldrne r1, SDRAM_ESDCFG_T1_W
+	str r1, [r0, #ESDCFG1_ROF]
+
+	/* Run initialization sequence */
+	ldr r1, SDRAM_PRECHARGE_CMD_W
+	str r1, [r0, #ESDCTL1_ROF]
+	ldr r1, [r2, #SDRAM_ALL_VAL]
+
+	ldr r1, SDRAM_AUTOREF_CMD_W
+	str r1, [r0, #ESDCTL1_ROF]
+	ldr r1, [r2, #SDRAM_ALL_VAL]
+	ldr r1, [r2, #SDRAM_ALL_VAL]
+
+	ldr r1, SDRAM_LOADMODE_CMD_W
+	str r1, [r0, #ESDCTL1_ROF]
+	ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
+	add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL

include/configs/imx27lite.h new file +39 -0

new file mode 100644
index 0000000..570a94d
@@ -0,0 +1,195 @@
+/*
+ * Copyright (C) 2009 Ilya Yanok <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*===================*/
+/* SoC Configuration */
+/*===================*/
+#define CONFIG_ARM926EJS			/* arm926ejs CPU core */
+#define CONFIG_MX27
+#define CONFIG_IMX27LITE
+#define CONFIG_MX27_CLK32	32768		/* OSC32K frequency */
+#define CONFIG_SYS_HZ		1000
+
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*=============*/
+/* Memory Info */

include/configs/imx27lite.h new file +60 -0

+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX27_UART1
+#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
+#define CONFIG_BAUDRATE		115200		/* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*=====================*/
+/* Flash & Environment */
+/*=====================*/
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+/* Use buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+/* Use hardware sector protection */
+#define CONFIG_SYS_FLASH_PROTECTION		1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of flash banks */
+#define CONFIG_SYS_FLASH_SECT_SZ	0x2000	/* 8KB sect size Intel Flash */
+/* end of flash */
+#define CONFIG_ENV_OFFSET		(PHYS_FLASH_SIZE - 0x20000)
+/* CS2 Base address */
+#define PHYS_FLASH_1			0xc0000000
+/* Flash Base for U-Boot */
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+/* Flash size 2MB */
+#define PHYS_FLASH_SIZE			0x200000
+#define CONFIG_SYS_MAX_FLASH_SECT	(PHYS_FLASH_SIZE / \
+		CONFIG_SYS_FLASH_SECT_SZ)
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		0x40000		/* Reserve 256KiB */
+#define CONFIG_ENV_SECT_SIZE		0x10000		/* Env sector Size */
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+/*
+ * Ethernet
+ */
+#define CONFIG_FEC_IMX27
+#define CONFIG_MII
+#define CONFIG_NET_MULTI
+
+/*
+ * NAND
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_MXC_NAND_REGS_BASE	0xd8000000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0xd8000000
+#define CONFIG_JFFS2_NAND
+#define CONFIG_MXC_NAND_HWECC
+
+/*
+ * SD/MMC
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MXC_MMC
+#define CONFIG_MXC_MCI_REGS_BASE	0x10014000

Quoted 30 lines

This patch adds support for i.MX27-LITEKIT development board from LogicPD. This board uses i.MX27 SoC and has 2MB NOR flash, 64MB NAND flash, FEC ethernet controller integrated into i.MX27.

Signed-off-by Ilya Yanok <[email protected]>

---
 MAINTAINERS                             |    1 +
 MAKEALL                                 |    1 +
 Makefile                                |    3 +
 board/logicpd/imx27lite/Makefile        |   51 +++++++
 board/logicpd/imx27lite/config.mk       |    1 +
 board/logicpd/imx27lite/imx27lite.c     |   97 +++++++++++++
 board/logicpd/imx27lite/lowlevel_init.S |  223 +++++++++++++++++++++++++++++++
 board/logicpd/imx27lite/u-boot.lds      |   56 ++++++++
 include/configs/imx27lite.h             |  195 +++++++++++++++++++++++++++
 9 files changed, 628 insertions(+), 0 deletions(-)
 create mode 100644 board/logicpd/imx27lite/Makefile
 create mode 100644 board/logicpd/imx27lite/config.mk
 create mode 100644 board/logicpd/imx27lite/imx27lite.c
 create mode 100644 board/logicpd/imx27lite/lowlevel_init.S
 create mode 100644 board/logicpd/imx27lite/u-boot.lds
 create mode 100644 include/configs/imx27lite.h

MAINTAINERS +0 -0

index 3d50668..98efd69 100644
@@ -519,6 +519,7 @@ George G. Davis <[email protected]>
 	gcplus		SA1100
 

MAINTAINERS George G. Davis <[email protected]> · line 522

Quoted 2 lines

MAINTAINERS +1 -0

 Wolfgang Denk <[email protected]>
+	imx27lite	i.MX27

Wolfgang could you ack it?

MAINTAINERS George G. Davis <[email protected]> · line 522

Quoted 3 lines

Wolfgang Denk <[email protected]>

MAINTAINERS +1 -0

+	imx27lite	i.MX27

Wolfgang could you ack it?

Quoted 1 line

qong i.MX31

+ */

board/logicpd/imx27lite/imx27lite.c new file +33 -0

+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int imx27lite_devices_init(void)
+{
+	struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
+	int i;
+	unsigned int mode[] = {
+		PD0_AIN_FEC_TXD0,
+		PD1_AIN_FEC_TXD1,
+		PD2_AIN_FEC_TXD2,
+		PD3_AIN_FEC_TXD3,
+		PD4_AOUT_FEC_RX_ER,
+		PD5_AOUT_FEC_RXD1,
+		PD6_AOUT_FEC_RXD2,
+		PD7_AOUT_FEC_RXD3,
+		PD8_AF_FEC_MDIO,
+		PD9_AIN_FEC_MDC | GPIO_PUEN,
+		PD10_AOUT_FEC_CRS,
+		PD11_AOUT_FEC_TX_CLK,
+		PD12_AOUT_FEC_RXD0,
+		PD13_AOUT_FEC_RX_DV,
+		PD14_AOUT_FEC_CLR,
+		PD15_AOUT_FEC_COL,
+		PD16_AIN_FEC_TX_ER,
+		PF23_AIN_FEC_TX_EN,
+		PE12_PF_UART1_TXD,
+		PE13_PF_UART1_RXD,
+		PB4_PF_SD2_D0,

Quoted 30 lines

board/logicpd/imx27lite/imx27lite.c new file +30 -0

+static int imx27lite_devices_init(void)
+{
+	struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
+	int i;
+	unsigned int mode[] = {
+		PD0_AIN_FEC_TXD0,
+		PD1_AIN_FEC_TXD1,
+		PD2_AIN_FEC_TXD2,
+		PD3_AIN_FEC_TXD3,
+		PD4_AOUT_FEC_RX_ER,
+		PD5_AOUT_FEC_RXD1,
+		PD6_AOUT_FEC_RXD2,
+		PD7_AOUT_FEC_RXD3,
+		PD8_AF_FEC_MDIO,
+		PD9_AIN_FEC_MDC | GPIO_PUEN,
+		PD10_AOUT_FEC_CRS,
+		PD11_AOUT_FEC_TX_CLK,
+		PD12_AOUT_FEC_RXD0,
+		PD13_AOUT_FEC_RX_DV,
+		PD14_AOUT_FEC_CLR,
+		PD15_AOUT_FEC_COL,
+		PD16_AIN_FEC_TX_ER,
+		PF23_AIN_FEC_TX_EN,
+		PE12_PF_UART1_TXD,
+		PE13_PF_UART1_RXD,
+		PB4_PF_SD2_D0,
+		PB5_PF_SD2_D1,
+		PB6_PF_SD2_D2,
+		PB7_PF_SD2_D3,
+		PB8_PF_SD2_CMD,

board/logicpd/imx27lite/imx27lite.c line 64

Quoted 7 lines

board/logicpd/imx27lite/imx27lite.c new file +6 -0

+		PB9_PF_SD2_CLK,
+		(GPIO_PORTC | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 31),
+	};
+
+	for (i = 0; i < ARRAY_SIZE(mode); i++)
+		imx_gpio_mode(mode[i]);

you do not answer about my api comment?

do you plan to create one for device init?

Hi Jean-Christophe,

Quoted 30 lines · Jean-Christophe PLAGNIOL-VILLARD

Quoted 30 lines

board/logicpd/imx27lite/imx27lite.c new file +30 -0

+static int imx27lite_devices_init(void)
+{
+	struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
+	int i;
+	unsigned int mode[] = {
+		PD0_AIN_FEC_TXD0,
+		PD1_AIN_FEC_TXD1,
+		PD2_AIN_FEC_TXD2,
+		PD3_AIN_FEC_TXD3,
+		PD4_AOUT_FEC_RX_ER,
+		PD5_AOUT_FEC_RXD1,
+		PD6_AOUT_FEC_RXD2,
+		PD7_AOUT_FEC_RXD3,
+		PD8_AF_FEC_MDIO,
+		PD9_AIN_FEC_MDC | GPIO_PUEN,
+		PD10_AOUT_FEC_CRS,
+		PD11_AOUT_FEC_TX_CLK,
+		PD12_AOUT_FEC_RXD0,
+		PD13_AOUT_FEC_RX_DV,
+		PD14_AOUT_FEC_CLR,
+		PD15_AOUT_FEC_COL,
+		PD16_AIN_FEC_TX_ER,
+		PF23_AIN_FEC_TX_EN,
+		PE12_PF_UART1_TXD,
+		PE13_PF_UART1_RXD,
+		PB4_PF_SD2_D0,
+		PB5_PF_SD2_D1,
+		PB6_PF_SD2_D2,
+		PB7_PF_SD2_D3,
+		PB8_PF_SD2_CMD,

Quoted 9 lines

board/logicpd/imx27lite/imx27lite.c line 64

Quoted 7 lines

board/logicpd/imx27lite/imx27lite.c new file +6 -0

+		PB9_PF_SD2_CLK,
+		(GPIO_PORTC | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 31),
+	};
+
+	for (i = 0; i < ARRAY_SIZE(mode); i++)
+		imx_gpio_mode(mode[i]);

you do not answer about my api comment?

Sorry, I forgot to write a separate mail to ask you.

Quoted 2 lines

do you plan to create one for device init?

What kind of API you expect me to create here? It's just IO pins initialization...

+ * Copyright (C) 2008,2009 Eric Jarrige <[email protected]>
+ * Copyright (C) 2009 Ilya Yanok <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */

board/logicpd/imx27lite/imx27lite.c new file +65 -0

+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_MXC_UART
+static void imx27lite_uart_init()
+{
+	int i;
+	unsigned int mode[] = {
+		PE12_PF_UART1_TXD,
+		PE13_PF_UART1_RXD,
+	};
+
+	for (i = 0; i < ARRAY_SIZE(mode); i++)
+		imx_gpio_mode(mode[i]);
+
+}
+#endif /* CONFIGL_MXC_UART */
+
+#ifdef CONFIG_FEC_MXC
+static void imx27lite_fec_init()
+{
+	struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
+	int i;
+	unsigned int mode[] = {
+		PD0_AIN_FEC_TXD0,
+		PD1_AIN_FEC_TXD1,
+		PD2_AIN_FEC_TXD2,
+		PD3_AIN_FEC_TXD3,
+		PD4_AOUT_FEC_RX_ER,
+		PD5_AOUT_FEC_RXD1,
+		PD6_AOUT_FEC_RXD2,
+		PD7_AOUT_FEC_RXD3,
+		PD8_AF_FEC_MDIO,
+		PD9_AIN_FEC_MDC | GPIO_PUEN,
+		PD10_AOUT_FEC_CRS,
+		PD11_AOUT_FEC_TX_CLK,
+		PD12_AOUT_FEC_RXD0,
+		PD13_AOUT_FEC_RX_DV,
+		PD14_AOUT_FEC_CLR,
+		PD15_AOUT_FEC_COL,
+		PD16_AIN_FEC_TX_ER,
+		PF23_AIN_FEC_TX_EN,
+		(GPIO_PORTC | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 31),
+	};
+
+	for (i = 0; i < ARRAY_SIZE(mode); i++)
+		imx_gpio_mode(mode[i]);
+
+	writel(readl(&regs->port[PORTC].dr) | (1 << 31),
+				&regs->port[PORTC].dr);
+}
+#endif /* CONFIG_FEC_MXC */
+
+#ifdef CONFIG_MXC_MMC
+static void imx27lite_sd_init()
+{
+	int i;
+	unsigned int mode[] = {
+		PB4_PF_SD2_D0,
+		PB5_PF_SD2_D1,
+		PB6_PF_SD2_D2,

board/logicpd/imx27lite/imx27lite.c new file +36 -0

+
+#ifdef CONFIG_MXC_UART
+	imx27lite_uart_init();
+#endif
+#ifdef CONFIG_FEC_MXC
+	imx27lite_fec_init();
+#endif
+#ifdef CONFIG_MXC_MMC
+	imx27lite_sd_init();
+#endif
+
+	return 0;
+}
+
+int dram_init (void)
+{
+
+#if CONFIG_NR_DRAM_BANKS > 0
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1,
+			PHYS_SDRAM_1_SIZE);
+#endif
+#if CONFIG_NR_DRAM_BANKS > 1
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = get_ram_size((volatile void *)PHYS_SDRAM_2,
+			PHYS_SDRAM_2_SIZE);
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("LogicPD imx27lite\n");
+	return 0;
+}

board/logicpd/imx27lite/lowlevel_init.S new file +0 -1

new file mode 100644
index 0000000..e2cdecb
--- /dev/null

board/logicpd/imx27lite/lowlevel_init.S new file +15 -0

+
+#define SDRAM_MODE_REGISTER_VAL	0x33	/* BL: 8, CAS: 3 */
+#define SDRAM_EXT_MODE_REGISTER_VAL	0x1000000
+
+#define MPCTL0_VAL	0x1ef15d5
+
+#define SPCTL0_VAL	0x043a1c09
+
+#define CSCR_VAL	0x33f08107
+
+#define PCDR0_VAL	0x120470c3
+#define PCDR1_VAL	0x03030303
+#define PCCR0_VAL	0xffffffff
+#define PCCR1_VAL	0xfffffffc
+

board/logicpd/imx27lite/lowlevel_init.S new file +120 -0

+/* reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+/* memtest start address */
+#define CONFIG_SYS_MEMTEST_START	0xA0000000
+#define CONFIG_SYS_MEMTEST_END		0xA1000000	/* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE	(256 * 1024)	/* regular stack */
+#define PHYS_SDRAM_1		0xA0000000	/* DDR Start */
+#define PHYS_SDRAM_1_SIZE	0x08000000	/* DDR size 128MB */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX27_UART1
+#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
+#define CONFIG_BAUDRATE		115200		/* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Flash & Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+/* Use buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+/* Use hardware sector protection */
+#define CONFIG_SYS_FLASH_PROTECTION		1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of flash banks */
+#define CONFIG_SYS_FLASH_SECT_SZ	0x2000	/* 8KB sect size Intel Flash */
+/* end of flash */
+#define CONFIG_ENV_OFFSET		(PHYS_FLASH_SIZE - 0x20000)
+/* CS2 Base address */
+#define PHYS_FLASH_1			0xc0000000
+/* Flash Base for U-Boot */
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+/* Flash size 2MB */
+#define PHYS_FLASH_SIZE			0x200000
+#define CONFIG_SYS_MAX_FLASH_SECT	(PHYS_FLASH_SIZE / \
+		CONFIG_SYS_FLASH_SECT_SZ)
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		0x40000		/* Reserve 256KiB */
+#define CONFIG_ENV_SECT_SIZE		0x10000		/* Env sector Size */
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+/*
+ * Ethernet
+ */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR		0x1f
+#define CONFIG_MII
+#define CONFIG_NET_MULTI
+
+/*
+ * MTD
+ */
+#define CONFIG_MTD_DEVICE
+
+/*
+ * NAND
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_MXC_NAND_REGS_BASE	0xd8000000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0xd8000000
+#define CONFIG_JFFS2_NAND
+#define CONFIG_MXC_NAND_HWECC
+
+/*
+ * SD/MMC
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MXC_MMC
+#define CONFIG_MXC_MCI_REGS_BASE	0x10014000
+#define CONFIG_DOS_PARTITION
+
+/*
+ * MTD partitions
+ */
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT		"nor0=physmap-flash.0,nand0=mxc_nand.0"
+#define MTDPARTS_DEFAULT			\
+	"mtdparts="				\
+		"physmap-flash.0:"		\
+			"256k(U-Boot),"		\
+			"1664k(user),"		\
+			"64k(env1),"		\
+			"64k(env2);"		\
+		"mxc_nand.0:"			\
+			"128k(IPL-SPL),"	\
+			"4m(kernel),"		\
+			"22m(rootfs),"		\
+			"-(userfs)"
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
+#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size  */
+/* Print buffer sz */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+		sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BDI