ppc/85xx: Added PCIe support for P1 P2 RDB
PATCH 1/1 ppc/85xx: Added PCIe support for P1 P2 RDB
* Added PCIe support for P1 P2 RDB
* Calls the fsl_pci_init_port function to initialize all the PCIe ports on the board.
---
- applies on git.denx.de/u-boot-mpc85xx.git branch->next
board/freescale/p1_p2_rdb/Makefile | 1 + board/freescale/p1_p2_rdb/pci.c | 112 ++++++++++++++++++++++++++++++++++++ include/configs/P1_P2_RDB.h | 6 ++ 3 files changed, 119 insertions(+), 0 deletions(-) create mode 100644 board/freescale/p1_p2_rdb/pci.c
board/freescale/p1_p2_rdb/Makefile +1 -0
@@ -27,6 +27,7 @@ LIB = $(obj)lib$(BOARD).a COBJS-y += $(BOARD).o COBJS-y += law.o COBJS-y += tlb.o +COBJS-$(CONFIG_PCI) += pci.o COBJS-y += ddr.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
board/freescale/p1_p2_rdb/pci.c new file +112 -0
112 lines not on this page · raw message
include/configs/P1_P2_RDB.h +6 -0
@@ -35,6 +35,12 @@#define CONFIG_E500 1/* BOOKE e500 family */ #define CONFIG_MPC85xx 1/* MPC8540/60/55/41/48/P1020/P2020,etc*/ #define CONFIG_FSL_ELBC 1/* Enable eLBC Support */ +#define CONFIG_PCI 1/* Enable PCI/PCIE */ +#define CONFIG_PCIE1 1/* PCIE controler 1 (slot 1) */ +#define CONFIG_PCIE2 1/* PCIE controler 2 (slot 2) */ +#define CONFIG_FSL_PCI_INIT 1/* Use common FSL init code */ +#define CONFIG_FSL_PCIE_RESET 1/* need PCIe reset errata */ +#define CONFIG_SYS_PCI_64BIT 1/* enable 64-bit PCI resources */ #define CONFIG_FSL_LAW 1/* Use common FSL init code */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE
Signature · 1 line
1.5.6.5
PATCH 1/1 ppc/85xx: Added PCIe support for P1 P2 RDB
Dear Poonam Aggrwal,
Quoted 19 lines · In message <[email protected]>…
* Added PCIe support for P1 P2 RDB
* Calls thefsl_pci_init_portfunction to initialize all the PCIe ports on the board.Signed-off-by Poonam Aggrwal <[email protected]>Signed-off-by Kumar Gala <[email protected]>---
- applies on git.denx.de/u-boot-mpc85xx.gitbranch->nextboard/freescale/p1_p2_rdb/Makefile | 1 + board/freescale/p1_p2_rdb/pci.c | 112 ++++++++++++++++++++++++++++++++++++ include/configs/P1_P2_RDB.h | 6 ++ 3 files changed, 119 insertions(+), 0 deletions(-) create mode 100644 board/freescale/p1_p2_rdb/pci.cboard/freescale/p1_p2_rdb/Makefile +0
-0
board/freescale/p1_p2_rdb/Makefile LIB = $(obj)lib$(BOARD).a · line 31
Quoted 5 lines
board/freescale/p1_p2_rdb/Makefile +1
-0@@ -27,6 +27,7 @@ LIB = $(obj)lib$(BOARD).a COBJS-y += $(BOARD).o COBJS-y += law.o COBJS-y += tlb.o +COBJS-$(CONFIG_PCI) += pci.o COBJS-y += ddr.o
Please (make and) keep list sorted.
...
board/freescale/p1_p2_rdb/Makefile LIB = $(obj)lib$(BOARD).a
Quoted 4 lines
board/freescale/p1_p2_rdb/Makefile +4
-0+void ft_pci_board_setup(void *blob) +{ +#ifdef CONFIG_PCIE2 + ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
PCIE2 ... pci1 ... pcie2 ???
board/freescale/p1_p2_rdb/Makefile
Quoted 3 lines
board/freescale/p1_p2_rdb/Makefile +3
-0+#endif +#ifdef CONFIG_PCIE1 + ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
PCIE1 ... pci2 ... pcie1 ???
This looks broken to me?
Best regards,
Wolfgang Denk
Signature · 6 lines
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
As far as the laws of mathematics refer to reality, they are not cer-
tain, and as far as they are certain, they do not refer to reality.
-- Albert EinsteinPATCH 1/1 ppc/85xx: Added PCIe support for P1 P2 RDB
Quoted 34 lines · Wolfgang Denk
Dear Poonam Aggrwal,
In message <[email protected]
Quoted 23 lines
you wrote:
* Added PCIe support for P1 P2 RDB
* Calls thefsl_pci_init_portfunction to initialize all the PCIe ports
on the board.Signed-off-by Poonam Aggrwal <[email protected]>Signed-off-by Kumar Gala <[email protected]>---
- applies on git.denx.de/u-boot-mpc85xx.gitbranch->next
board/freescale/p1_p2_rdb/Makefile | 1 +board/freescale/p1_p2_rdb/pci.c| 112 ++++++++++++++++++++++++++
++++++++++include/configs/P1_P2_RDB.h| 6 ++3 files changed, 119 insertions(+), 0 deletions(-)create mode 100644
board/freescale/p1_p2_rdb/pci.cboard/freescale/ renamed from board/freescale/p1_p2_rdb/Makefile +0
-0p1_p2_rdb/Makefile
index 9107263..c366f7c 100644board/freescale/p1_p2_rdb/Makefile +0
-0@@ -27,6 +27,7 @@ LIB = $(obj)lib$(BOARD).aQuoted 5 lines
COBJS-y += $(BOARD).o
COBJS-y += law.o
COBJS-y += tlb.o
+COBJS-$(CONFIG_PCI) += pci.o
COBJS-y += ddr.oPlease (make and) keep list sorted.
Quoted 7 lines
...
board/freescale/p1_p2_rdb/Makefile
Quoted 4 lines
board/freescale/p1_p2_rdb/Makefile +4
-0+void ft_pci_board_setup(void *blob) +{ +#ifdef CONFIG_PCIE2 + ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);PCIE2 ... pci1 ... pcie2 ???
The device tree has always been more generic and used 'pci' for PCI, PCI-X, and PCIe buses.
Quoted 8 lines
board/freescale/p1_p2_rdb/Makefile
Quoted 4 lines
board/freescale/p1_p2_rdb/Makefile +3
-0+#endif +#ifdef CONFIG_PCIE1 + ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);PCIE1 ... pci2 ... pcie1 ???
This looks broken to me?
This is actually correct.. This has to do w/stupid FSL documentation and #. The device tree "orders" PCI buses based on there register offset in CCSRBAR. So 0x9000 is pci1, 0xa000 is pci2. However FSL docs and some internal SoC screwness lists the PCIe controller @ 9000 as PCIE2 and the one at A000 as PCIE1.
Probably should add a comment in the code about this.
- k
PATCH 1/1 ppc/85xx: Added PCIe support for P1 P2 RDB
Dear Kumar Gala,
Quoted 6 lines · In message <[email protected]> you wrote:
Quoted 4 lines
PCIE1 ... pci2 ... pcie1 ???
This looks broken to me?
Quoted 7 lines
This is actually correct.. This has to do w/stupid FSL documentation and #. The device tree "orders" PCI buses based on there register offset in CCSRBAR. So
0x9000is pci1,0xa000is pci2. However FSL docs and some internal SoC screwness lists the PCIe controller @ 9000 as PCIE2 and the one at A000 as PCIE1.Probably should add a comment in the code about this.
Yes, please. This looks just too much like a copy & paste error.
Best regards,
Wolfgang Denk
Signature · 5 lines
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de There are three ways to get something done: do it yourself, hire someone, or forbid your kids to do it.