et131x cleanups - phase 1

index 3a81a85..9a6dbd6 100644
@@ -143,7 +143,7 @@
 
 /**
  * EepromWriteByte - Write a byte to the ET1310's EEPROM
- * @pAdapter: pointer to our private adapter structure
+ * @etdev: pointer to our private adapter structure
  * @unAddress: the address to write
  * @bData: the value to write
  * @unEepronId: the ID of the EEPROM

@@ -151,11 +151,11 @@
  *
  * Returns SUCCESS or FAILURE
  */
-int32_t EepromWriteByte(struct et131x_adapter *pAdapter, uint32_t unAddress,
+int32_t EepromWriteByte(struct et131x_adapter *etdev, uint32_t unAddress,
 			uint8_t bData, uint32_t unEepromId,
 			uint32_t unAddressingMode)
 {
-	struct pci_dev *pdev = pAdapter->pdev;
+	struct pci_dev *pdev = etdev->pdev;
 	int32_t nIndex;
 	int32_t nRetries;
 	int32_t nError = false;

@@ -292,7 +292,7 @@ int32_t EepromWriteByte(struct et131x_adapter *pAdapter, uint32_t unAddress,
 		 *	   so we do a blind write for load bug.
 		 */
 		if (bStatus & LBCIF_STATUS_GENERAL_ERROR
-		    && pAdapter->RevisionID == 0) {
+		    && etdev->RevisionID == 0) {
 			break;
 		}
 

@@ -349,7 +349,7 @@ int32_t EepromWriteByte(struct et131x_adapter *pAdapter, uint32_t unAddress,
 
 /**
  * EepromReadByte - Read a byte from the ET1310's EEPROM
- * @pAdapter: pointer to our private adapter structure
+ * @etdev: pointer to our private adapter structure
  * @unAddress: the address from which to read
  * @pbData: a pointer to a byte in which to store the value of the read
  * @unEepronId: the ID of the EEPROM

@@ -357,11 +357,11 @@ int32_t EepromWriteByte(struct et131x_adapter *pAdapter, uint32_t unAddress,
  *
  * Returns SUCCESS or FAILURE
  */
-int32_t EepromReadByte(struct et131x_adapter *pAdapter, uint32_t unAddress,
+int32_t EepromReadByte(struct et131x_adapter *etdev, uint32_t unAddress,
 		       uint8_t *pbData, uint32_t unEepromId,
 		       uint32_t unAddressingMode)
 {
-	struct pci_dev *pdev = pAdapter->pdev;
+	struct pci_dev *pdev = etdev->pdev;
 	int32_t nIndex;
 	int32_t nError = 0;
 	uint8_t bControl;

index 6fb2c6d..3b4b273 100644
@@ -99,27 +99,27 @@ extern dbg_info_t *et131x_dbginfo;
  * ConfigGlobalRegs - Used to configure the global registers on the JAGCore
  * @pAdpater: pointer to our adapter structure
  */
-void ConfigGlobalRegs(struct et131x_adapter *pAdapter)
+void ConfigGlobalRegs(struct et131x_adapter *etdev)
 {
-	struct _GLOBAL_t __iomem *pGbl = &pAdapter->CSRAddress->global;
+	struct _GLOBAL_t __iomem *pGbl = &etdev->CSRAddress->global;
 
 	DBG_ENTER(et131x_dbginfo);
 
-	if (pAdapter->RegistryPhyLoopbk == false) {
-		if (pAdapter->RegistryJumboPacket < 2048) {
+	if (etdev->RegistryPhyLoopbk == false) {
+		if (etdev->RegistryJumboPacket < 2048) {
 			/* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
 			 * block of RAM that the driver can split between Tx
 			 * and Rx as it desires.  Our default is to split it
 			 * 50/50:
 			 */
 			writel(0, &pGbl->rxq_start_addr.value);
-			writel(pAdapter->RegistryRxMemEnd,
+			writel(etdev->RegistryRxMemEnd,
 			       &pGbl->rxq_end_addr.value);
-			writel(pAdapter->RegistryRxMemEnd + 1,
+			writel(etdev->RegistryRxMemEnd + 1,
 			       &pGbl->txq_start_addr.value);
 			writel(INTERNAL_MEM_SIZE - 1,
 			       &pGbl->txq_end_addr.value);
-		} else if (pAdapter->RegistryJumboPacket < 8192) {
+		} else if (etdev->RegistryJumboPacket < 8192) {
 			/* For jumbo packets > 2k but < 8k, split 50-50. */
 			writel(0, &pGbl->rxq_start_addr.value);
 			writel(INTERNAL_MEM_RX_OFFSET,

@@ -171,9 +171,9 @@ void ConfigGlobalRegs(struct et131x_adapter *pAdapter)
 
 /**
  * ConfigMMCRegs - Used to configure the main memory registers in the JAGCore
- * @pAdapter: pointer to our adapter structure
+ * @etdev: pointer to our adapter structure
  */
-void ConfigMMCRegs(struct et131x_adapter *pAdapter)
+void ConfigMMCRegs(struct et131x_adapter *etdev)
 {
 	MMC_CTRL_t mmc_ctrl = { 0 };
 

@@ -188,7 +188,7 @@ void ConfigMMCRegs(struct et131x_adapter *pAdapter)
 	mmc_ctrl.bits.arb_disable = 0x0;
 	mmc_ctrl.bits.mmc_enable = 0x1;
 
-	writel(mmc_ctrl.value, &pAdapter->CSRAddress->mmc.mmc_ctrl.value);
+	writel(mmc_ctrl.value, &etdev->CSRAddress->mmc.mmc_ctrl.value);
 
 	DBG_LEAVE(et131x_dbginfo);
 }

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index c7f64a8..2730b9c 100644

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index 74a8375..77fac95 100644

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index 82fcb66..d9c7a44 100644
@@ -484,7 +484,7 @@ void et131x_Mii_check(struct et131x_adapter *etdev,
 	uint32_t uiMdiMdix;
 	uint32_t uiMasterSlave;
 	uint32_t uiPolarity;
-	unsigned long lockflags;
+	unsigned long flags;
 
 	DBG_ENTER(et131x_dbginfo);
 

@@ -495,12 +495,12 @@ void et131x_Mii_check(struct et131x_adapter *etdev,
 			/* Update our state variables and indicate the
 			 * connected state
 			 */
-			spin_lock_irqsave(&etdev->Lock, lockflags);
+			spin_lock_irqsave(&etdev->Lock, flags);
 
 			etdev->MediaState = NETIF_STATUS_MEDIA_CONNECT;
 			MP_CLEAR_FLAG(etdev, fMP_ADAPTER_LINK_DETECTION);
 
-			spin_unlock_irqrestore(&etdev->Lock, lockflags);
+			spin_unlock_irqrestore(&etdev->Lock, flags);
 
 			/* Don't indicate state if we're in loopback mode */
 			if (etdev->RegistryPhyLoopbk == false)

@@ -533,11 +533,11 @@ void et131x_Mii_check(struct et131x_adapter *etdev,
 			     (etdev, fMP_ADAPTER_LINK_DETECTION))
 			    || (etdev->MediaState ==
 				NETIF_STATUS_MEDIA_DISCONNECT)) {
-				spin_lock_irqsave(&etdev->Lock, lockflags);
+				spin_lock_irqsave(&etdev->Lock, flags);
 				etdev->MediaState =
 				    NETIF_STATUS_MEDIA_DISCONNECT;
 				spin_unlock_irqrestore(&etdev->Lock,
-						       lockflags);
+						       flags);
 
 				/* Only indicate state if we're in loopback
 				 * mode

index 864d3ad..a507411 100644
@@ -119,7 +119,7 @@ extern dbg_info_t *et131x_dbginfo;
  */
 void EnablePhyComa(struct et131x_adapter *etdev)
 {
-	unsigned long lockflags;
+	unsigned long flags;
 	PM_CSR_t GlobalPmCSR;
 	int32_t LoopCounter = 10;
 

@@ -134,9 +134,9 @@ void EnablePhyComa(struct et131x_adapter *etdev)
 	etdev->PoMgmt.PowerDownDuplex = etdev->AiForceDpx;
 
 	/* Stop sending packets. */
-	spin_lock_irqsave(&etdev->SendHWLock, lockflags);
+	spin_lock_irqsave(&etdev->SendHWLock, flags);
 	MP_SET_FLAG(etdev, fMP_ADAPTER_LOWER_POWER);
-	spin_unlock_irqrestore(&etdev->SendHWLock, lockflags);
+	spin_unlock_irqrestore(&etdev->SendHWLock, flags);
 
 	/* Wait for outstanding Receive packets */
 	while ((MP_GET_RCV_REF(etdev) != 0) && (LoopCounter-- > 0))

index f8cc6a6..9dc08fb 100644
@@ -685,7 +685,7 @@ void ConfigRxDmaRegs(struct et131x_adapter *etdev)
 	PFBR_DESC_t pFbrEntry;
 	uint32_t iEntry;
 	RXDMA_PSR_NUM_DES_t psr_num_des;
-	unsigned long lockflags;
+	unsigned long flags;
 
 	DBG_ENTER(et131x_dbginfo);
 

@@ -718,7 +718,7 @@ void ConfigRxDmaRegs(struct et131x_adapter *etdev)
 	writel((psr_num_des.bits.psr_ndes * LO_MARK_PERCENT_FOR_PSR) / 100,
 	       &pRxDma->psr_min_des.value);
 
-	spin_lock_irqsave(&etdev->RcvLock, lockflags);
+	spin_lock_irqsave(&etdev->RcvLock, flags);
 
 	/* These local variables track the PSR in the adapter structure */
 	pRxLocal->local_psr_full.bits.psr_full = 0;

@@ -801,7 +801,7 @@ void ConfigRxDmaRegs(struct et131x_adapter *etdev)
 	 */
 	writel(etdev->RegistryRxTimeInterval, &pRxDma->max_pkt_time.value);
 
-	spin_unlock_irqrestore(&etdev->RcvLock, lockflags);
+	spin_unlock_irqrestore(&etdev->RcvLock, flags);
 
 	DBG_LEAVE(et131x_dbginfo);
 }

@@ -914,7 +914,7 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev)
 	PMP_RFD pMpRfd;
 	uint32_t nIndex;
 	uint8_t *pBufVa;
-	unsigned long lockflags;
+	unsigned long flags;
 	struct list_head *element;
 	uint8_t ringIndex;
 	uint16_t bufferIndex;

@@ -1013,7 +1013,7 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev)
 	}
 
 	/* Get and fill the RFD. */
-	spin_lock_irqsave(&etdev->RcvLock, lockflags);
+	spin_lock_irqsave(&etdev->RcvLock, flags);
 
 	pMpRfd = NULL;
 	element = pRxLocal->RecvList.next;

@@ -1023,14 +1023,14 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev)
 		DBG_RX(et131x_dbginfo,
 		       "NULL RFD returned from RecvList via list_entry()\n");
 		DBG_RX_LEAVE(et131x_dbginfo);
-		spin_unlock_irqrestore(&etdev->RcvLock, lockflags);
+		spin_unlock_irqrestore(&etdev->RcvLock, flags);
 		return NULL;
 	}
 
 	list_del(&pMpRfd->list_node);
 	pRxLocal->nReadyRecv--;
 
-	spin_unlock_irqrestore(&etdev->RcvLock, lockflags);
+	spin_unlock_irqrestore(&etdev->RcvLock, flags);
 
 	pMpRfd->iBufferIndex = bufferIndex;
 	pMpRfd->iRingIndex = ringIndex;

@@ -1260,9 +1260,9 @@ void et131x_handle_recv_interrupt(struct et131x_adapter *etdev)
 			 * Besides, we don't really need (at this point) the
 			 * pending list anyway.
 			 */
-			/* spin_lock_irqsave( &etdev->RcvPendLock, lockflags );
+			/* spin_lock_irqsave( &etdev->RcvPendLock, flags );
 			 * list_add_tail( &pMpRfd->list_node, &etdev->RxRing.RecvPendingList );
-			 * spin_unlock_irqrestore( &etdev->RcvPendLock, lockflags );
+			 * spin_unlock_irqrestore( &etdev->RcvPendLock, flags );
 			 */
 
 			/* Update the number of outstanding Recvs */

@@ -1302,7 +1302,7 @@ void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD pMpRfd)
 	struct _RXDMA_t __iomem *pRxDma = &etdev->CSRAddress->rxdma;
 	uint16_t bi = pMpRfd->iBufferIndex;
 	uint8_t ri = pMpRfd->iRingIndex;
-	unsigned long lockflags;
+	unsigned long flags;
 
 	DBG_RX_ENTER(et131x_dbginfo);
 

@@ -1314,7 +1314,7 @@ void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD pMpRfd)
 	    (ri == 0 && bi < pRxLocal->Fbr0NumEntries) ||
 #endif
 	    (ri == 1 && bi < pRxLocal->Fbr1NumEntries)) {
-		spin_lock_irqsave(&etdev->FbrLock, lockflags);
+		spin_lock_irqsave(&etdev->FbrLock, flags);
 
 		if (ri == 1) {
 			PFBR_DESC_t pNextDesc =

@@ -1362,7 +1362,7 @@ void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD pMpRfd)
 			       &pRxDma->fbr0_full_offset.value);
 		}
 #endif
-		spin_unlock_irqrestore(&etdev->FbrLock, lockflags);
+		spin_unlock_irqrestore(&etdev->FbrLock, flags);
 	} else {
 		DBG_ERROR(et131x_dbginfo,
 			  "NICReturnRFD illegal Buffer Index returned\n");

@@ -1371,10 +1371,10 @@ void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD pMpRfd)
 	/* The processing on this RFD is done, so put it back on the tail of
 	 * our list
 	 */
-	spin_lock_irqsave(&etdev->RcvLock, lockflags);
+	spin_lock_irqsave(&etdev->RcvLock, flags);
 	list_add_tail(&pMpRfd->list_node, &pRxLocal->RecvList);
 	pRxLocal->nReadyRecv++;
-	spin_unlock_irqrestore(&etdev->RcvLock, lockflags);
+	spin_unlock_irqrestore(&etdev->RcvLock, flags);
 
 	DBG_ASSERT(pRxLocal->nReadyRecv <= pRxLocal->NumRfd);
 	DBG_RX_LEAVE(et131x_dbginfo);

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index 8455e0a..b9018e6 100644
@@ -492,18 +492,18 @@ void et131x_error_timer_handler(unsigned long data)
 void et131x_link_detection_handler(unsigned long data)
 {
 	struct et131x_adapter *etdev = (struct et131x_adapter *) data;
-	unsigned long lockflags;
+	unsigned long flags;
 
 	/* Let everyone know that we have run */
 	etdev->bLinkTimerActive = false;
 
 	if (etdev->MediaState == 0) {
-		spin_lock_irqsave(&etdev->Lock, lockflags);
+		spin_lock_irqsave(&etdev->Lock, flags);
 
 		etdev->MediaState = NETIF_STATUS_MEDIA_DISCONNECT;
 		MP_CLEAR_FLAG(etdev, fMP_ADAPTER_LINK_DETECTION);
 
-		spin_unlock_irqrestore(&etdev->Lock, lockflags);
+		spin_unlock_irqrestore(&etdev->Lock, flags);
 
 		netif_carrier_off(etdev->netdev);
 

index 77fac95..74ba177 100644
@@ -467,12 +467,12 @@ void et131x_multicast(struct net_device *netdev)
 	struct et131x_adapter *adapter = netdev_priv(netdev);
 	uint32_t PacketFilter = 0;
 	uint32_t count;
-	unsigned long lockflags;
+	unsigned long flags;
 	struct dev_mc_list *mclist = netdev->mc_list;
 
 	DBG_ENTER(et131x_dbginfo);
 
-	spin_lock_irqsave(&adapter->Lock, lockflags);
+	spin_lock_irqsave(&adapter->Lock, flags);
 
 	/* Before we modify the platform-independent filter flags, store them
 	 * locally. This allows us to determine if anything's changed and if

@@ -552,7 +552,7 @@ void et131x_multicast(struct net_device *netdev)
 			    "NO UPDATE REQUIRED, FLAGS didn't change\n");
 	}
 
-	spin_unlock_irqrestore(&adapter->Lock, lockflags);
+	spin_unlock_irqrestore(&adapter->Lock, flags);
 
 	DBG_LEAVE(et131x_dbginfo);
 }

@@ -610,7 +610,7 @@ void et131x_tx_timeout(struct net_device *netdev)
 {
 	struct et131x_adapter *etdev = netdev_priv(netdev);
 	PMP_TCB pMpTcb;
-	unsigned long lockflags;
+	unsigned long flags;
 
 	DBG_WARNING(et131x_dbginfo, "TX TIMEOUT\n");
 

@@ -635,7 +635,7 @@ void et131x_tx_timeout(struct net_device *netdev)
 	}
 
 	/* Is send stuck? */
-	spin_lock_irqsave(&etdev->TCBSendQLock, lockflags);
+	spin_lock_irqsave(&etdev->TCBSendQLock, flags);
 
 	pMpTcb = etdev->TxRing.CurrSendHead;
 

@@ -660,7 +660,7 @@ void et131x_tx_timeout(struct net_device *netdev)
 			}
 
 			spin_unlock_irqrestore(&etdev->TCBSendQLock,
-					       lockflags);
+					       flags);
 
 			DBG_WARNING(et131x_dbginfo,
 				"Send stuck - reset.  pMpTcb->WrIndex %x, Flags 0x%08x\n",

@@ -689,7 +689,7 @@ void et131x_tx_timeout(struct net_device *netdev)
 		}
 	}
 
-	spin_unlock_irqrestore(&etdev->TCBSendQLock, lockflags);
+	spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
 }
 
 /**

index dca9977..8e06039 100644
@@ -66,15 +66,6 @@
 #define NUM_WOL_PATTERNS       0x5
 #define CRC16_POLY             0x1021
 
-/* Definition of NDIS_DEVICE_POWER_STATE */
-typedef enum {
-	NdisDeviceStateUnspecified = 0,
-	NdisDeviceStateD0,
-	NdisDeviceStateD1,
-	NdisDeviceStateD2,
-	NdisDeviceStateD3
-} NDIS_DEVICE_POWER_STATE;
-
 typedef struct _MP_POWER_MGMT {
 	/* variable putting the phy into coma mode when boot up with no cable
 	 * plugged in after 5 seconds

@@ -97,7 +88,6 @@ typedef struct _MP_POWER_MGMT {
 	} IPAddress;
 
 	/* Current Power state of the adapter. */
-	NDIS_DEVICE_POWER_STATE PowerState;
 	bool WOLState;
 	bool WOLEnabled;
 	bool Failed10Half;

index 9dc08fb..b05b8c5 100644
@@ -1235,13 +1235,11 @@ void et131x_handle_recv_interrupt(struct et131x_adapter *etdev)
 			break;
 
 		/* Do not receive any packets until a filter has been set.
-		 * Do not receive any packets until we are at D0.
 		 * Do not receive any packets until we have link.
 		 * If length is zero, return the RFD in order to advance the
 		 * Free buffer ring.
 		 */
 		if ((!etdev->PacketFilter) ||
-		    (etdev->PoMgmt.PowerState != NdisDeviceStateD0) ||
 		    (!MP_LINK_DETECTED(etdev)) ||
 		    (pMpRfd->PacketSize == 0)) {
 			continue;

index b9018e6..d84b654 100644
@@ -967,8 +967,6 @@ int __devinit et131x_pci_setup(struct pci_dev *pdev,
 	DBG_TRACE(et131x_dbginfo, "Init send data structures...\n");
 	et131x_init_send(adapter);
 
-	adapter->PoMgmt.PowerState = NdisDeviceStateD0;
-
 	/* Register the interrupt
 	 *
 	 * NOTE - This is being done in the open routine, where most other

index 9f51425..f9687b3 100644
@@ -479,6 +479,5 @@ void et131x_isr_handler(struct work_struct *work)
 		}
 	}
 
-	if (etdev->PoMgmt.PowerState == NdisDeviceStateD0)
-		et131x_enable_interrupts(etdev);
+	et131x_enable_interrupts(etdev);
 }

index 2b55319..82686ea 100644
@@ -108,8 +108,6 @@
 #define MP_TEST_FLAGS(_M, _F)       (((_M)->Flags & (_F)) == (_F))
 #define MP_IS_FLAG_CLEAR(_M, _F)    (((_M)->Flags & (_F)) == 0)
 
-#define MP_INC_RCV_REF(_A)          atomic_inc(&(_A)->RcvRefCount)
-#define MP_DEC_RCV_REF(_A)          atomic_dec(&(_A)->RcvRefCount)
 #define MP_GET_RCV_REF(_A)          atomic_read(&(_A)->RcvRefCount)
 
 /* Macros specific to the private adapter structure */

index a507411..848d6b0 100644
@@ -139,8 +139,6 @@ void EnablePhyComa(struct et131x_adapter *etdev)
 	spin_unlock_irqrestore(&etdev->SendHWLock, flags);
 
 	/* Wait for outstanding Receive packets */
-	while ((MP_GET_RCV_REF(etdev) != 0) && (LoopCounter-- > 0))
-		mdelay(2);
 
 	/* Gate off JAGCore 3 clock domains */
 	GlobalPmCSR.bits.pm_sysclk_gate = 0;

index b05b8c5..6423552 100644
@@ -1258,13 +1258,6 @@ void et131x_handle_recv_interrupt(struct et131x_adapter *etdev)
 			 * Besides, we don't really need (at this point) the
 			 * pending list anyway.
 			 */
-			/* spin_lock_irqsave( &etdev->RcvPendLock, flags );
-			 * list_add_tail( &pMpRfd->list_node, &etdev->RxRing.RecvPendingList );
-			 * spin_unlock_irqrestore( &etdev->RcvPendLock, flags );
-			 */
-
-			/* Update the number of outstanding Recvs */
-			/* MP_INC_RCV_REF( etdev ); */
 		} else {
 			RFDFreeArray[PacketFreeCount] = pMpRfd;
 			PacketFreeCount++;

index 82686ea..04de4ff 100644
@@ -108,8 +108,6 @@
 #define MP_TEST_FLAGS(_M, _F)       (((_M)->Flags & (_F)) == (_F))
 #define MP_IS_FLAG_CLEAR(_M, _F)    (((_M)->Flags & (_F)) == 0)
 
-#define MP_GET_RCV_REF(_A)          atomic_read(&(_A)->RcvRefCount)
-
 /* Macros specific to the private adapter structure */
 #define MP_TCB_RESOURCES_AVAILABLE(_M) ((_M)->TxRing.nBusySend < NUM_TCB)
 #define MP_TCB_RESOURCES_NOT_AVAILABLE(_M) ((_M)->TxRing.nBusySend >= NUM_TCB)

@@ -311,8 +309,6 @@ struct et131x_adapter {
 	MP_POWER_MGMT PoMgmt;
 	INTERRUPT_t CachedMaskValue;
 
-	atomic_t RcvRefCount;	/* Num packets not yet returned */
-
 	/* Xcvr status at last poll */
 	MI_BMSR_t Bmsr;
 

index a017d27..43f5b62 100644
@@ -1375,7 +1375,7 @@ void et131x_free_busy_send_packets(struct et131x_adapter *etdev)
 		DBG_VERBOSE(et131x_dbginfo, "pMpTcb = 0x%p\n", pMpTcb);
 
 		FreeCounter++;
-		MP_FREE_SEND_PACKET_FUN(etdev, pMpTcb);
+		et131x_free_send_packet(etdev, pMpTcb);
 
 		spin_lock_irqsave(&etdev->TCBSendQLock, flags);
 

@@ -1384,7 +1384,7 @@ void et131x_free_busy_send_packets(struct et131x_adapter *etdev)
 
 	if (FreeCounter == NUM_TCB) {
 		DBG_ERROR(et131x_dbginfo,
-		    "MpFreeBusySendPackets exitted loop for a bad reason\n");
+		    "MpFreeBusySendPackets exited loop for a bad reason\n");
 		BUG();
 	}
 

@@ -1451,7 +1451,7 @@ static void et131x_update_tcb_list(struct et131x_adapter *etdev)
 			etdev->TxRing.CurrSendTail = NULL;
 
 		spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
-		MP_FREE_SEND_PACKET_FUN(etdev, pMpTcb);
+		et131x_free_send_packet(etdev, pMpTcb);
 		spin_lock_irqsave(&etdev->TCBSendQLock, flags);
 
 		/* Goto the next packet */

@@ -1466,7 +1466,7 @@ static void et131x_update_tcb_list(struct et131x_adapter *etdev)
 			etdev->TxRing.CurrSendTail = NULL;
 
 		spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
-		MP_FREE_SEND_PACKET_FUN(etdev, pMpTcb);
+		et131x_free_send_packet(etdev, pMpTcb);
 		spin_lock_irqsave(&etdev->TCBSendQLock, flags);
 
 		/* Goto the next packet */

index 04de4ff..df4a625 100644
@@ -333,9 +333,4 @@ struct et131x_adapter {
 	struct net_device_stats net_stats_prev;
 };
 
-#define MPSendPacketsHandler  MPSendPackets
-#define MP_FREE_SEND_PACKET_FUN(Adapter, pMpTcb) \
-	et131x_free_send_packet(Adapter, pMpTcb)
-#define MpSendPacketFun(Adapter, Packet) MpSendPacket(Adapter, Packet)
-
 #endif /* __ET131X_ADAPTER_H__ */

index 9a6dbd6..29d1c0e 100644
@@ -292,7 +292,7 @@ int32_t EepromWriteByte(struct et131x_adapter *etdev, uint32_t unAddress,
 		 *	   so we do a blind write for load bug.
 		 */
 		if (bStatus & LBCIF_STATUS_GENERAL_ERROR
-		    && etdev->RevisionID == 0) {
+		    && etdev->pdev->revision == 0) {
 			break;
 		}
 

index d9c7a44..63a23b9 100644
@@ -841,7 +841,7 @@ void TPAL_SetPhyAutoNeg(struct et131x_adapter *etdev)
 
 	ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_BOTH);
 
-	if (etdev->DeviceID != ET131X_PCI_DEVICE_ID_FAST)
+	if (etdev->pdev->device != ET131X_PCI_DEVICE_ID_FAST)
 		ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL);
 	else
 		ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);

index df4a625..69509d7 100644
@@ -250,19 +250,6 @@ struct et131x_adapter {
 	/* Pointer to the device's PCI register space */
 	ADDRESS_MAP_t __iomem *CSRAddress;
 
-	/* PCI config space info, for debug purposes only. */
-	u8 RevisionID;
-	u16 VendorID;
-	u16 DeviceID;
-	u16 SubVendorID;
-	u16 SubSystemID;
-	u32 CacheFillSize;
-	u16 PciXDevCtl;
-	u8 pci_lat_timer;
-	u8 pci_hdr_type;
-	u8 pci_bist;
-	u32 pci_cfg_state[64 / sizeof(u32)];
-
 	/* Registry parameters */
 	u8 SpeedDuplex;		/* speed/duplex */
 	eFLOW_CONTROL_t RegistryFlowControl;	/* for 802.3x flow control */

index 148672b..499cf75 100644
@@ -76,6 +76,7 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/bitops.h>
+#include <linux/pci.h>
 #include <asm/system.h>
 
 #include <linux/netdevice.h>

@@ -288,7 +289,7 @@ void et131x_config_parse(struct et131x_adapter *etdev)
 	/* If we are the 10/100 device, and gigabit is somehow requested then
 	 * knock it down to 100 full.
 	 */
-	if (etdev->DeviceID == ET131X_PCI_DEVICE_ID_FAST &&
+	if (etdev->pdev->device == ET131X_PCI_DEVICE_ID_FAST &&
 	    etdev->SpeedDuplex == 5)
 		etdev->SpeedDuplex = 4;
 

index d84b654..86bd55d 100644
@@ -240,6 +240,7 @@ int et131x_find_adapter(struct et131x_adapter *adapter, struct pci_dev *pdev)
 	uint8_t eepromStat;
 	uint8_t maxPayload = 0;
 	uint8_t read_size_reg;
+	u8 rev;
 
 	DBG_ENTER(et131x_dbginfo);
 

@@ -283,15 +284,14 @@ int et131x_find_adapter(struct et131x_adapter *adapter, struct pci_dev *pdev)
 	 * present, we need to fail.
 	 */
 	if (eepromStat & 0x4C) {
-		result = pci_read_config_byte(pdev, PCI_REVISION_ID,
-					      &adapter->RevisionID);
+		result = pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
 		if (result != PCIBIOS_SUCCESSFUL) {
 			DBG_ERROR(et131x_dbginfo,
 				  "Could not read PCI config space for "
 				  "Revision ID\n");
 			DBG_LEAVE(et131x_dbginfo);
 			return -EIO;
-		} else if (adapter->RevisionID == 0x01) {
+		} else if (rev == 0x01) {
 			int32_t nLoop;
 			uint8_t ucTemp[4] = { 0xFE, 0x13, 0x10, 0xFF };
 

@@ -405,16 +405,6 @@ int et131x_find_adapter(struct et131x_adapter *adapter, struct pci_dev *pdev)
 		return -EIO;
 	}
 
-	/* PCI Express Configuration registers 0x48-0x5B (Device Control) */
-	result = pci_read_config_word(pdev, ET1310_PCI_DEV_CTRL,
-				      &adapter->PciXDevCtl);
-	if (result != PCIBIOS_SUCCESSFUL) {
-		DBG_ERROR(et131x_dbginfo,
-		  "Could not read PCI config space for PCI Express Dev Ctl\n");
-		DBG_LEAVE(et131x_dbginfo);
-		return -EIO;
-	}
-
 	/* Get MAC address from config space if an eeprom exists, otherwise
 	 * the MAC address there will not be valid
 	 */

@@ -556,7 +546,7 @@ int et131x_adapter_setup(struct et131x_adapter *etdev)
 	 * We need to turn off 1000 base half dulplex, the mac does not
 	 * support it. For the 10/100 part, turn off all gig advertisement
 	 */
-	if (etdev->DeviceID != ET131X_PCI_DEVICE_ID_FAST)
+	if (etdev->pdev->device != ET131X_PCI_DEVICE_ID_FAST)
 		ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL);
 	else
 		ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);

@@ -890,8 +880,6 @@ int __devinit et131x_pci_setup(struct pci_dev *pdev,
 	adapter = netdev_priv(netdev);
 	adapter->pdev = pdev;
 	adapter->netdev = netdev;
-	adapter->VendorID = pdev->vendor;
-	adapter->DeviceID = pdev->device;
 
 	/* Do the same for the netdev struct */
 	netdev->irq = pdev->irq;

index 86bd55d..5485dd7 100644
@@ -742,6 +742,7 @@ void __devexit et131x_pci_remove(struct pci_dev *pdev)
 	unregister_netdev(netdev);
 	et131x_adapter_memory_free(adapter);
 	iounmap(adapter->CSRAddress);
+	pci_dev_put(adapter->pdev);
 	free_netdev(netdev);
 	pci_release_regions(pdev);
 	pci_disable_device(pdev);

@@ -878,7 +879,7 @@ int __devinit et131x_pci_setup(struct pci_dev *pdev,
 
 	/* Allocate private adapter struct and copy in relevant information */
 	adapter = netdev_priv(netdev);
-	adapter->pdev = pdev;
+	adapter->pdev = pci_dev_get(pdev);
 	adapter->netdev = netdev;
 
 	/* Do the same for the netdev struct */

@@ -1022,6 +1023,7 @@ err_mem_free:
 err_iounmap:
 	iounmap(adapter->CSRAddress);
 err_free_dev:
+	pci_dev_put(pdev);
 	free_netdev(netdev);
 err_release_res:
 	pci_release_regions(pdev);

index 3b4b273..4032589 100644
@@ -101,7 +101,7 @@ extern dbg_info_t *et131x_dbginfo;
  */
 void ConfigGlobalRegs(struct et131x_adapter *etdev)
 {
-	struct _GLOBAL_t __iomem *pGbl = &etdev->CSRAddress->global;
+	struct _GLOBAL_t __iomem *pGbl = &etdev->regs->global;
 
 	DBG_ENTER(et131x_dbginfo);
 

@@ -188,7 +188,7 @@ void ConfigMMCRegs(struct et131x_adapter *etdev)
 	mmc_ctrl.bits.arb_disable = 0x0;
 	mmc_ctrl.bits.mmc_enable = 0x1;
 
-	writel(mmc_ctrl.value, &etdev->CSRAddress->mmc.mmc_ctrl.value);
+	writel(mmc_ctrl.value, &etdev->regs->mmc.mmc_ctrl.value);
 
 	DBG_LEAVE(et131x_dbginfo);
 }

@@ -207,12 +207,12 @@ void et131x_enable_interrupts(struct et131x_adapter *adapter)
 		MaskValue |= 0x10000;
 
 	adapter->CachedMaskValue.value = MaskValue;
-	writel(MaskValue, &adapter->CSRAddress->global.int_mask.value);
+	writel(MaskValue, &adapter->regs->global.int_mask.value);
 }
 
 void et131x_disable_interrupts(struct et131x_adapter *adapter)
 {
 	/* Disable all global interrupts */
 	adapter->CachedMaskValue.value = INT_MASK_DISABLE;
-	writel(INT_MASK_DISABLE, &adapter->CSRAddress->global.int_mask.value);
+	writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask.value);
 }

index 4cb4cfc..9461a2d 100644
@@ -103,7 +103,7 @@ extern dbg_info_t *et131x_dbginfo;
  */
 void ConfigMACRegs1(struct et131x_adapter *etdev)
 {
-	struct _MAC_t __iomem *pMac = &etdev->CSRAddress->mac;
+	struct _MAC_t __iomem *pMac = &etdev->regs->mac;
 	MAC_STATION_ADDR1_t station1;
 	MAC_STATION_ADDR2_t station2;
 	MAC_IPG_t ipg;

@@ -182,7 +182,7 @@ void ConfigMACRegs1(struct et131x_adapter *etdev)
 void ConfigMACRegs2(struct et131x_adapter *etdev)
 {
 	int32_t delay = 0;
-	struct _MAC_t __iomem *pMac = &etdev->CSRAddress->mac;
+	struct _MAC_t __iomem *pMac = &etdev->regs->mac;
 	MAC_CFG1_t cfg1;
 	MAC_CFG2_t cfg2;
 	MAC_IF_CTRL_t ifctrl;

@@ -190,7 +190,7 @@ void ConfigMACRegs2(struct et131x_adapter *etdev)
 
 	DBG_ENTER(et131x_dbginfo);
 
-	ctl.value = readl(&etdev->CSRAddress->txmac.ctl.value);
+	ctl.value = readl(&etdev->regs->txmac.ctl.value);
 	cfg1.value = readl(&pMac->cfg1.value);
 	cfg2.value = readl(&pMac->cfg2.value);
 	ifctrl.value = readl(&pMac->if_ctrl.value);

@@ -269,7 +269,7 @@ void ConfigMACRegs2(struct et131x_adapter *etdev)
 	/* Enable TXMAC */
 	ctl.bits.txmac_en = 0x1;
 	ctl.bits.fc_disable = 0x1;
-	writel(ctl.value, &etdev->CSRAddress->txmac.ctl.value);
+	writel(ctl.value, &etdev->regs->txmac.ctl.value);
 
 	/* Ready to start the RXDMA/TXDMA engine */
 	if (!MP_TEST_FLAG(etdev, fMP_ADAPTER_LOWER_POWER)) {

@@ -285,7 +285,7 @@ void ConfigMACRegs2(struct et131x_adapter *etdev)
 
 void ConfigRxMacRegs(struct et131x_adapter *etdev)
 {
-	struct _RXMAC_t __iomem *pRxMac = &etdev->CSRAddress->rxmac;
+	struct _RXMAC_t __iomem *pRxMac = &etdev->regs->rxmac;
 	RXMAC_WOL_SA_LO_t sa_lo;
 	RXMAC_WOL_SA_HI_t sa_hi;
 	RXMAC_PF_CTRL_t pf_ctrl = { 0 };

@@ -427,7 +427,7 @@ void ConfigRxMacRegs(struct et131x_adapter *etdev)
 
 void ConfigTxMacRegs(struct et131x_adapter *etdev)
 {
-	struct _TXMAC_t __iomem *pTxMac = &etdev->CSRAddress->txmac;
+	struct _TXMAC_t __iomem *pTxMac = &etdev->regs->txmac;
 	TXMAC_CF_PARAM_t Local;
 
 	DBG_ENTER(et131x_dbginfo);

@@ -450,7 +450,7 @@ void ConfigTxMacRegs(struct et131x_adapter *etdev)
 void ConfigMacStatRegs(struct et131x_adapter *etdev)
 {
 	struct _MAC_STAT_t __iomem *pDevMacStat =
-		&etdev->CSRAddress->macStat;
+		&etdev->regs->macStat;
 
 	DBG_ENTER(et131x_dbginfo);
 

@@ -581,7 +581,7 @@ void UpdateMacStatHostCounters(struct et131x_adapter *etdev)
 {
 	struct _ce_stats_t *stats = &etdev->Stats;
 	struct _MAC_STAT_t __iomem *pDevMacStat =
-		&etdev->CSRAddress->macStat;
+		&etdev->regs->macStat;
 
 	stats->collisions += readl(&pDevMacStat->TNcl);
 	stats->first_collision += readl(&pDevMacStat->TScl);

@@ -619,11 +619,11 @@ void HandleMacStatInterrupt(struct et131x_adapter *etdev)
 	/* Read the interrupt bits from the register(s).  These are Clear On
 	 * Write.
 	 */
-	Carry1.value = readl(&etdev->CSRAddress->macStat.Carry1.value);
-	Carry2.value = readl(&etdev->CSRAddress->macStat.Carry2.value);
+	Carry1.value = readl(&etdev->regs->macStat.Carry1.value);
+	Carry2.value = readl(&etdev->regs->macStat.Carry2.value);
 
-	writel(Carry1.value, &etdev->CSRAddress->macStat.Carry1.value);
-	writel(Carry2.value, &etdev->CSRAddress->macStat.Carry2.value);
+	writel(Carry1.value, &etdev->regs->macStat.Carry1.value);
+	writel(Carry2.value, &etdev->regs->macStat.Carry2.value);
 
 	/* We need to do update the host copy of all the MAC_STAT counters.
 	 * For each counter, check it's overflow bit.  If the overflow bit is

@@ -665,7 +665,7 @@ void HandleMacStatInterrupt(struct et131x_adapter *etdev)
 
 void SetupDeviceForMulticast(struct et131x_adapter *etdev)
 {
-	struct _RXMAC_t __iomem *rxmac = &etdev->CSRAddress->rxmac;
+	struct _RXMAC_t __iomem *rxmac = &etdev->regs->rxmac;
 	uint32_t nIndex;
 	uint32_t result;
 	uint32_t hash1 = 0;

@@ -718,7 +718,7 @@ void SetupDeviceForMulticast(struct et131x_adapter *etdev)
 	}
 
 	/* Write out the new hash to the device */
-	pm_csr.value = readl(&etdev->CSRAddress->global.pm_csr.value);
+	pm_csr.value = readl(&etdev->regs->global.pm_csr.value);
 	if (pm_csr.bits.pm_phy_sw_coma == 0) {
 		writel(hash1, &rxmac->multi_hash1);
 		writel(hash2, &rxmac->multi_hash2);

@@ -731,7 +731,7 @@ void SetupDeviceForMulticast(struct et131x_adapter *etdev)
 
 void SetupDeviceForUnicast(struct et131x_adapter *etdev)
 {
-	struct _RXMAC_t __iomem *rxmac = &etdev->CSRAddress->rxmac;
+	struct _RXMAC_t __iomem *rxmac = &etdev->regs->rxmac;
 	RXMAC_UNI_PF_ADDR1_t uni_pf1;
 	RXMAC_UNI_PF_ADDR2_t uni_pf2;
 	RXMAC_UNI_PF_ADDR3_t uni_pf3;

@@ -763,7 +763,7 @@ void SetupDeviceForUnicast(struct et131x_adapter *etdev)
 	uni_pf1.bits.addr1_5 = etdev->CurrentAddress[4];
 	uni_pf1.bits.addr1_6 = etdev->CurrentAddress[5];
 
-	pm_csr.value = readl(&etdev->CSRAddress->global.pm_csr.value);
+	pm_csr.value = readl(&etdev->regs->global.pm_csr.value);
 	if (pm_csr.bits.pm_phy_sw_coma == 0) {
 		writel(uni_pf1.value, &rxmac->uni_pf_addr1.value);
 		writel(uni_pf2.value, &rxmac->uni_pf_addr2.value);

index 63a23b9..d0a3c83 100644
@@ -118,7 +118,7 @@ static int et131x_xcvr_init(struct et131x_adapter *adapter);
 int PhyMiRead(struct et131x_adapter *adapter, uint8_t xcvrAddr,
 	      uint8_t xcvrReg, uint16_t *value)
 {
-	struct _MAC_t __iomem *mac = &adapter->CSRAddress->mac;
+	struct _MAC_t __iomem *mac = &adapter->regs->mac;
 	int status = 0;
 	uint32_t delay;
 	MII_MGMT_ADDR_t miiAddr;

@@ -202,7 +202,7 @@ int PhyMiRead(struct et131x_adapter *adapter, uint8_t xcvrAddr,
  */
 int MiWrite(struct et131x_adapter *adapter, uint8_t xcvrReg, uint16_t value)
 {
-	struct _MAC_t __iomem *mac = &adapter->CSRAddress->mac;
+	struct _MAC_t __iomem *mac = &adapter->regs->mac;
 	int status = 0;
 	uint8_t xcvrAddr = adapter->Stats.xcvr_addr;
 	uint32_t delay;

index 848d6b0..846c80b 100644
@@ -125,7 +125,7 @@ void EnablePhyComa(struct et131x_adapter *etdev)
 
 	DBG_ENTER(et131x_dbginfo);
 
-	GlobalPmCSR.value = readl(&etdev->CSRAddress->global.pm_csr.value);
+	GlobalPmCSR.value = readl(&etdev->regs->global.pm_csr.value);
 
 	/* Save the GbE PHY speed and duplex modes. Need to restore this
 	 * when cable is plugged back in

@@ -144,11 +144,11 @@ void EnablePhyComa(struct et131x_adapter *etdev)
 	GlobalPmCSR.bits.pm_sysclk_gate = 0;
 	GlobalPmCSR.bits.pm_txclk_gate = 0;
 	GlobalPmCSR.bits.pm_rxclk_gate = 0;
-	writel(GlobalPmCSR.value, &etdev->CSRAddress->global.pm_csr.value);
+	writel(GlobalPmCSR.value, &etdev->regs->global.pm_csr.value);
 
 	/* Program gigE PHY in to Coma mode */
 	GlobalPmCSR.bits.pm_phy_sw_coma = 1;
-	writel(GlobalPmCSR.value, &etdev->CSRAddress->global.pm_csr.value);
+	writel(GlobalPmCSR.value, &etdev->regs->global.pm_csr.value);
 
 	DBG_LEAVE(et131x_dbginfo);
 }

@@ -163,14 +163,14 @@ void DisablePhyComa(struct et131x_adapter *etdev)
 
 	DBG_ENTER(et131x_dbginfo);
 
-	GlobalPmCSR.value = readl(&etdev->CSRAddress->global.pm_csr.value);
+	GlobalPmCSR.value = readl(&etdev->regs->global.pm_csr.value);
 
 	/* Disable phy_sw_coma register and re-enable JAGCore clocks */
 	GlobalPmCSR.bits.pm_sysclk_gate = 1;
 	GlobalPmCSR.bits.pm_txclk_gate = 1;
 	GlobalPmCSR.bits.pm_rxclk_gate = 1;
 	GlobalPmCSR.bits.pm_phy_sw_coma = 0;
-	writel(GlobalPmCSR.value, &etdev->CSRAddress->global.pm_csr.value);
+	writel(GlobalPmCSR.value, &etdev->regs->global.pm_csr.value);
 
 	/* Restore the GbE PHY speed and duplex modes;
 	 * Reset JAGCore; re-configure and initialize JAGCore and gigE PHY

index 6423552..c60e05e 100644
@@ -680,7 +680,7 @@ void et131x_rfd_resources_free(struct et131x_adapter *adapter, MP_RFD *pMpRfd)
  */
 void ConfigRxDmaRegs(struct et131x_adapter *etdev)
 {
-	struct _RXDMA_t __iomem *pRxDma = &etdev->CSRAddress->rxdma;
+	struct _RXDMA_t __iomem *pRxDma = &etdev->regs->rxdma;
 	struct _rx_ring_t *pRxLocal = &etdev->RxRing;
 	PFBR_DESC_t pFbrEntry;
 	uint32_t iEntry;

@@ -817,8 +817,8 @@ void SetRxDmaTimer(struct et131x_adapter *etdev)
 	 */
 	if ((etdev->uiLinkSpeed == TRUEPHY_SPEED_100MBPS) ||
 	    (etdev->uiLinkSpeed == TRUEPHY_SPEED_10MBPS)) {
-		writel(0, &etdev->CSRAddress->rxdma.max_pkt_time.value);
-		writel(1, &etdev->CSRAddress->rxdma.num_pkt_done.value);
+		writel(0, &etdev->regs->rxdma.max_pkt_time.value);
+		writel(1, &etdev->regs->rxdma.num_pkt_done.value);
 	}
 }
 

@@ -833,11 +833,11 @@ void et131x_rx_dma_disable(struct et131x_adapter *etdev)
 	DBG_ENTER(et131x_dbginfo);
 
 	/* Setup the receive dma configuration register */
-	writel(0x00002001, &etdev->CSRAddress->rxdma.csr.value);
-	csr.value = readl(&etdev->CSRAddress->rxdma.csr.value);
+	writel(0x00002001, &etdev->regs->rxdma.csr.value);
+	csr.value = readl(&etdev->regs->rxdma.csr.value);
 	if (csr.bits.halt_status != 1) {
 		udelay(5);
-		csr.value = readl(&etdev->CSRAddress->rxdma.csr.value);
+		csr.value = readl(&etdev->regs->rxdma.csr.value);
 		if (csr.bits.halt_status != 1)
 			DBG_ERROR(et131x_dbginfo,
 				"RX Dma failed to enter halt state. CSR 0x%08x\n",

@@ -857,7 +857,7 @@ void et131x_rx_dma_enable(struct et131x_adapter *etdev)
 
 	if (etdev->RegistryPhyLoopbk)
 		/* RxDMA is disabled for loopback operation. */
-		writel(0x1, &etdev->CSRAddress->rxdma.csr.value);
+		writel(0x1, &etdev->regs->rxdma.csr.value);
 	else {
 	/* Setup the receive dma configuration register for normal operation */
 		RXDMA_CSR_t csr = { 0 };

@@ -878,12 +878,12 @@ void et131x_rx_dma_enable(struct et131x_adapter *etdev)
 		else if (etdev->RxRing.Fbr0BufferSize == 1024)
 			csr.bits.fbr0_size = 3;
 #endif
-		writel(csr.value, &etdev->CSRAddress->rxdma.csr.value);
+		writel(csr.value, &etdev->regs->rxdma.csr.value);
 
-		csr.value = readl(&etdev->CSRAddress->rxdma.csr.value);
+		csr.value = readl(&etdev->regs->rxdma.csr.value);
 		if (csr.bits.halt_status != 0) {
 			udelay(5);
-			csr.value = readl(&etdev->CSRAddress->rxdma.csr.value);
+			csr.value = readl(&etdev->regs->rxdma.csr.value);
 			if (csr.bits.halt_status != 0) {
 				DBG_ERROR(et131x_dbginfo,
 					"RX Dma failed to exit halt state.  CSR 0x%08x\n",

@@ -978,7 +978,7 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev)
 	}
 
 	writel(pRxLocal->local_psr_full.value,
-	       &etdev->CSRAddress->rxdma.psr_full_offset.value);
+	       &etdev->regs->rxdma.psr_full_offset.value);
 
 #ifndef USE_FBR0
 	if (ringIndex != 1) {

@@ -1273,7 +1273,7 @@ void et131x_handle_recv_interrupt(struct et131x_adapter *etdev)
 	if ((PacketArrayCount == NUM_PACKETS_HANDLED) || TempUnfinishedRec) {
 		etdev->RxRing.UnfinishedReceives = true;
 		writel(etdev->RegistryTxTimeInterval * NANO_IN_A_MICRO,
-		       &etdev->CSRAddress->global.watchdog_timer);
+		       &etdev->regs->global.watchdog_timer);
 	} else {
 		/* Watchdog timer will disable itself if appropriate. */
 		etdev->RxRing.UnfinishedReceives = false;

@@ -1290,7 +1290,7 @@ void et131x_handle_recv_interrupt(struct et131x_adapter *etdev)
 void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD pMpRfd)
 {
 	struct _rx_ring_t *pRxLocal = &etdev->RxRing;
-	struct _RXDMA_t __iomem *pRxDma = &etdev->CSRAddress->rxdma;
+	struct _RXDMA_t __iomem *pRxDma = &etdev->regs->rxdma;
 	uint16_t bi = pMpRfd->iBufferIndex;
 	uint8_t ri = pMpRfd->iRingIndex;
 	unsigned long flags;

index 43f5b62..0dbb824 100644
@@ -249,7 +249,7 @@ void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
  */
 void ConfigTxDmaRegs(struct et131x_adapter *etdev)
 {
-	struct _TXDMA_t __iomem *pTxDma = &etdev->CSRAddress->txdma;
+	struct _TXDMA_t __iomem *pTxDma = &etdev->regs->txdma;
 
 	DBG_ENTER(et131x_dbginfo);
 

@@ -289,7 +289,7 @@ void et131x_tx_dma_disable(struct et131x_adapter *etdev)
 	DBG_ENTER(et131x_dbginfo);
 
 	/* Setup the tramsmit dma configuration register */
-	writel(0x101, &etdev->CSRAddress->txdma.csr.value);
+	writel(0x101, &etdev->regs->txdma.csr.value);
 
 	DBG_LEAVE(et131x_dbginfo);
 }

@@ -306,7 +306,7 @@ void et131x_tx_dma_enable(struct et131x_adapter *etdev)
 
 	if (etdev->RegistryPhyLoopbk) {
 		/* TxDMA is disabled for loopback operation. */
-		writel(0x101, &etdev->CSRAddress->txdma.csr.value);
+		writel(0x101, &etdev->regs->txdma.csr.value);
 	} else {
 		TXDMA_CSR_t csr = { 0 };
 

@@ -316,7 +316,7 @@ void et131x_tx_dma_enable(struct et131x_adapter *etdev)
 		csr.bits.sngl_epkt_mode = 1;
 		csr.bits.halt = 0;
 		csr.bits.cache_thrshld = etdev->RegistryDMACache;
-		writel(csr.value, &etdev->CSRAddress->txdma.csr.value);
+		writel(csr.value, &etdev->regs->txdma.csr.value);
 	}
 
 	DBG_LEAVE(et131x_dbginfo);

@@ -788,14 +788,14 @@ static int nic_send_packet(struct et131x_adapter *etdev, PMP_TCB pMpTcb)
 
 	/* Write the new write pointer back to the device. */
 	writel(etdev->TxRing.txDmaReadyToSend.value,
-	       &etdev->CSRAddress->txdma.service_request.value);
+	       &etdev->regs->txdma.service_request.value);
 
 	/* For Gig only, we use Tx Interrupt coalescing.  Enable the software
 	 * timer to wake us up if this packet isn't followed by N more.
 	 */
 	if (etdev->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
 		writel(etdev->RegistryTxTimeInterval * NANO_IN_A_MICRO,
-		       &etdev->CSRAddress->global.watchdog_timer);
+		       &etdev->regs->global.watchdog_timer);
 	}
 
 	spin_unlock_irqrestore(&etdev->SendHWLock, flags);

@@ -837,7 +837,7 @@ static int nic_send_packet(struct et131x_adapter *etdev, PMP_TCB pMpTcb)
 	DBG_TX_ENTER(et131x_dbginfo);
 
 	ServiceComplete.value =
-		readl(&etdev->CSRAddress->txdma.NewServiceComplete.value);
+		readl(&etdev->regs->txdma.NewServiceComplete.value);
 
 	/*
 	 * Attempt to fix TWO hardware bugs:

@@ -1202,7 +1202,7 @@ static int nic_send_packet(struct et131x_adapter *etdev, PMP_TCB pMpTcb)
 
 	/* Write the new write pointer back to the device. */
 	writel(etdev->TxRing.txDmaReadyToSend.value,
-	       &etdev->CSRAddress->txdma.service_request.value);
+	       &etdev->regs->txdma.service_request.value);
 
 #ifdef CONFIG_ET131X_DEBUG
 	DumpDeviceBlock(DBG_TX_ON, etdev, 1);

@@ -1213,7 +1213,7 @@ static int nic_send_packet(struct et131x_adapter *etdev, PMP_TCB pMpTcb)
 	 */
 	if (etdev->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
 		writel(etdev->RegistryTxTimeInterval * NANO_IN_A_MICRO,
-		       &etdev->CSRAddress->global.watchdog_timer);
+		       &etdev->regs->global.watchdog_timer);
 	}
 
 	spin_unlock_irqrestore(&etdev->SendHWLock, flags);

@@ -1434,7 +1434,7 @@ static void et131x_update_tcb_list(struct et131x_adapter *etdev)
 	PMP_TCB pMpTcb;
 
 	ServiceComplete.value =
-	    readl(&etdev->CSRAddress->txdma.NewServiceComplete.value);
+	    readl(&etdev->regs->txdma.NewServiceComplete.value);
 
 	/* Has the ring wrapped?  Process any descriptors that do not have
 	 * the same "wrap" indicator as the current completion indicator

index 69509d7..70a90b8 100644
@@ -248,7 +248,7 @@ struct et131x_adapter {
 	TXMAC_TXTEST_t TxMacTest;
 
 	/* Pointer to the device's PCI register space */
-	ADDRESS_MAP_t __iomem *CSRAddress;
+	ADDRESS_MAP_t __iomem *regs;
 
 	/* Registry parameters */
 	u8 SpeedDuplex;		/* speed/duplex */

index 2730b9c..4346c82 100644
@@ -110,7 +110,7 @@ extern dbg_info_t *et131x_dbginfo;
  */
 void DumpTxQueueContents(int dbgLvl, struct et131x_adapter *etdev)
 {
-	MMC_t __iomem *mmc = &etdev->CSRAddress->mmc;
+	MMC_t __iomem *mmc = &etdev->regs->mmc;
 	uint32_t TxQueueAddr;
 
 	if (DBG_FLAGS(et131x_dbginfo) & dbgLvl) {

@@ -134,7 +134,7 @@ void DumpTxQueueContents(int dbgLvl, struct et131x_adapter *etdev)
 		}
 
 		DBG_PRINT("Shadow Pointers 0x%08x\n",
-			  readl(&etdev->CSRAddress->txmac.shadow_ptr.value));
+			  readl(&etdev->regs->txmac.shadow_ptr.value));
 	}
 }
 

@@ -151,7 +151,7 @@ void DumpDeviceBlock(int dbgLvl, struct et131x_adapter *etdev,
 {
 	uint32_t Address1, Address2;
 	uint32_t __iomem *BigDevicePointer =
-		(uint32_t __iomem *) etdev->CSRAddress;
+		(uint32_t __iomem *) etdev->regs;
 	const char *BlockNames[NUM_BLOCKS] = {
 		"Global", "Tx DMA", "Rx DMA", "Tx MAC",
 		"Rx MAC", "MAC", "MAC Stat", "MMC"

@@ -189,7 +189,7 @@ void DumpDeviceReg(int dbgLvl, struct et131x_adapter *etdev)
 	uint32_t Address1, Address2;
 	uint32_t Block;
 	uint32_t __iomem *BigDevicePointer =
-		(uint32_t __iomem *) etdev->CSRAddress;
+		(uint32_t __iomem *) etdev->regs;
 	uint32_t __iomem *Pointer;
 	const char *BlockNames[NUM_BLOCKS] = {
 		"Global", "Tx DMA", "Rx DMA", "Tx MAC",

index 5485dd7..4d45941 100644
@@ -440,7 +440,7 @@ void et131x_error_timer_handler(unsigned long data)
 	struct et131x_adapter *etdev = (struct et131x_adapter *) data;
 	PM_CSR_t pm_csr;
 
-	pm_csr.value = readl(&etdev->CSRAddress->global.pm_csr.value);
+	pm_csr.value = readl(&etdev->regs->global.pm_csr.value);
 
 	if (pm_csr.bits.pm_phy_sw_coma == 0) {
 		if (etdev->RegistryMACStat)

@@ -615,12 +615,12 @@ void et131x_soft_reset(struct et131x_adapter *adapter)
 	DBG_ENTER(et131x_dbginfo);
 
 	/* Disable MAC Core */
-	writel(0xc00f0000, &adapter->CSRAddress->mac.cfg1.value);
+	writel(0xc00f0000, &adapter->regs->mac.cfg1.value);
 
 	/* Set everything to a reset value */
-	writel(0x7F, &adapter->CSRAddress->global.sw_reset.value);
-	writel(0x000f0000, &adapter->CSRAddress->mac.cfg1.value);
-	writel(0x00000000, &adapter->CSRAddress->mac.cfg1.value);
+	writel(0x7F, &adapter->regs->global.sw_reset.value);
+	writel(0x000f0000, &adapter->regs->mac.cfg1.value);
+	writel(0x00000000, &adapter->regs->mac.cfg1.value);
 
 	DBG_LEAVE(et131x_dbginfo);
 }

@@ -741,7 +741,7 @@ void __devexit et131x_pci_remove(struct pci_dev *pdev)
 	/* Perform device cleanup */
 	unregister_netdev(netdev);
 	et131x_adapter_memory_free(adapter);
-	iounmap(adapter->CSRAddress);
+	iounmap(adapter->regs);
 	pci_dev_put(adapter->pdev);
 	free_netdev(netdev);
 	pci_release_regions(pdev);

@@ -915,9 +915,9 @@ int __devinit et131x_pci_setup(struct pci_dev *pdev,
 	DBG_TRACE(et131x_dbginfo,
 		  "Mapping bus-relative registers to virtual memory...\n");
 
-	adapter->CSRAddress = ioremap_nocache(pci_resource_start(pdev, 0),
+	adapter->regs = ioremap_nocache(pci_resource_start(pdev, 0),
 					      pci_resource_len(pdev, 0));
-	if (adapter->CSRAddress == NULL) {
+	if (adapter->regs == NULL) {
 		DBG_ERROR(et131x_dbginfo, "Cannot map device registers\n");
 		result = -ENOMEM;
 		goto err_free_dev;

@@ -933,7 +933,7 @@ int __devinit et131x_pci_setup(struct pci_dev *pdev,
 		GlobalPmCSR.bits.pm_txclk_gate = 1;
 		GlobalPmCSR.bits.pm_rxclk_gate = 1;
 		writel(GlobalPmCSR.value,
-		       &adapter->CSRAddress->global.pm_csr.value);
+		       &adapter->regs->global.pm_csr.value);
 	}
 
 	/* Issue a global reset to the et1310 */

@@ -1021,7 +1021,7 @@ out:
 err_mem_free:
 	et131x_adapter_memory_free(adapter);
 err_iounmap:
-	iounmap(adapter->CSRAddress);
+	iounmap(adapter->regs);
 err_free_dev:
 	pci_dev_put(pdev);
 	free_netdev(netdev);

index f9687b3..478569f 100644
@@ -129,7 +129,7 @@ irqreturn_t et131x_isr(int irq, void *dev_id)
 	/* Get a copy of the value in the interrupt status register
 	 * so we can process the interrupting section
 	 */
-	status.value = readl(&adapter->CSRAddress->global.int_status.value);
+	status.value = readl(&adapter->regs->global.int_status.value);
 
 	if (adapter->FlowControl == TxOnly ||
 	    adapter->FlowControl == Both) {

@@ -168,7 +168,7 @@ irqreturn_t et131x_isr(int irq, void *dev_id)
 		if (adapter->RxRing.UnfinishedReceives)
 			status.bits.rxdma_xfr_done = 1;
 		else if (pMpTcb == NULL)
-			writel(0, &adapter->CSRAddress->global.watchdog_timer);
+			writel(0, &adapter->regs->global.watchdog_timer);
 
 		status.bits.watchdog_interrupt = 0;
 #ifdef CONFIG_ET131X_DEBUG

@@ -214,7 +214,7 @@ void et131x_isr_handler(struct work_struct *work)
 	struct et131x_adapter *etdev =
 		container_of(work, struct et131x_adapter, task);
 	INTERRUPT_t GlobStatus = etdev->Stats.InterruptStatus;
-	ADDRESS_MAP_t __iomem *iomem = etdev->CSRAddress;
+	ADDRESS_MAP_t __iomem *iomem = etdev->regs;
 
 	/*
 	 * These first two are by far the most common.  Once handled, we clear

index 74ba177..fec3f86 100644
@@ -393,8 +393,8 @@ int et131x_set_packet_filter(struct et131x_adapter *adapter)
 
 	DBG_ENTER(et131x_dbginfo);
 
-	ctrl.value = readl(&adapter->CSRAddress->rxmac.ctrl.value);
-	pf_ctrl.value = readl(&adapter->CSRAddress->rxmac.pf_ctrl.value);
+	ctrl.value = readl(&adapter->regs->rxmac.ctrl.value);
+	pf_ctrl.value = readl(&adapter->regs->rxmac.pf_ctrl.value);
 
 	/* Default to disabled packet filtering.  Enable it in the individual
 	 * case statements that require the device to filter something

@@ -450,8 +450,8 @@ int et131x_set_packet_filter(struct et131x_adapter *adapter)
 		 * in the control reg.
 		 */
 		writel(pf_ctrl.value,
-		       &adapter->CSRAddress->rxmac.pf_ctrl.value);
-		writel(ctrl.value, &adapter->CSRAddress->rxmac.ctrl.value);
+		       &adapter->regs->rxmac.pf_ctrl.value);
+		writel(ctrl.value, &adapter->regs->rxmac.ctrl.value);
 	}
 
 	DBG_LEAVE(et131x_dbginfo);

index 0dbb824..8e8486a 100644
@@ -315,7 +315,7 @@ void et131x_tx_dma_enable(struct et131x_adapter *etdev)
 		 */
 		csr.bits.sngl_epkt_mode = 1;
 		csr.bits.halt = 0;
-		csr.bits.cache_thrshld = etdev->RegistryDMACache;
+		csr.bits.cache_thrshld = PARM_DMA_CACHE_DEF;
 		writel(csr.value, &etdev->regs->txdma.csr.value);
 	}
 

index 70a90b8..8e811af 100644
@@ -271,7 +271,6 @@ struct et131x_adapter {
 	/* Validation helpers */
 	u8 RegistryPMWOL;
 	u8 RegistryNMIDisable;
-	u32 RegistryDMACache;
 	u32 RegistrySCGain;
 	u8 RegistryPhyLoopbk;	/* Enable Phy loopback */
 

index 499cf75..628d6ad 100644
@@ -265,7 +265,6 @@ void et131x_config_parse(struct et131x_adapter *etdev)
 	else
 		etdev->RegistryNMIDisable = PARM_NMI_DISABLE_DEF;
 
-	etdev->RegistryDMACache = PARM_DMA_CACHE_DEF;
 	etdev->RegistryPhyLoopbk = PARM_PHY_LOOPBK_DEF;
 
 	/* Set the MAC address to a default */

index 8e811af..a7402a3 100644
@@ -253,8 +253,6 @@ struct et131x_adapter {
 	/* Registry parameters */
 	u8 SpeedDuplex;		/* speed/duplex */
 	eFLOW_CONTROL_t RegistryFlowControl;	/* for 802.3x flow control */
-	u8 RegistryWOLMatch;	/* Enable WOL pattern-matching */
-	u8 RegistryWOLLink;	/* Link state change is independant */
 	u8 RegistryPhyComa;	/* Phy Coma mode enable/disable */
 
 	u32 RegistryRxMemEnd;	/* Size of internal rx memory */

@@ -269,9 +267,7 @@ struct et131x_adapter {
 	u32 RegistryRxTimeInterval;
 
 	/* Validation helpers */
-	u8 RegistryPMWOL;
 	u8 RegistryNMIDisable;
-	u32 RegistrySCGain;
 	u8 RegistryPhyLoopbk;	/* Enable Phy loopback */
 
 	/* Derived from the registry: */

index 628d6ad..f8273d1 100644
@@ -247,8 +247,6 @@ void et131x_config_parse(struct et131x_adapter *etdev)
 
 	etdev->RegistryVlanTag = PARM_VLAN_TAG_DEF;
 	etdev->RegistryFlowControl = PARM_FLOW_CTL_DEF;
-	etdev->RegistryWOLLink = PARM_WOL_LINK_DEF;
-	etdev->RegistryWOLMatch = PARM_WOL_MATCH_DEF;
 	etdev->RegistryJumboPacket = PARM_JUMBO_PKT_DEF;
 	etdev->RegistryPhyComa = PARM_PHY_COMA_DEF;
 	etdev->RegistryRxNumBuffers = PARM_RX_NUM_BUFS_DEF;

@@ -257,8 +255,6 @@ void et131x_config_parse(struct et131x_adapter *etdev)
 	etdev->RegistryTxTimeInterval = PARM_TX_TIME_INT_DEF;
 	etdev->RegistryRxMemEnd = PARM_RX_MEM_END_DEF;
 	etdev->RegistryMACStat = PARM_MAC_STAT_DEF;
-	etdev->RegistrySCGain = PARM_SC_GAIN_DEF;
-	etdev->RegistryPMWOL = PARM_PM_WOL_DEF;
 
 	if (et131x_nmi_disable != PARM_NMI_DISABLE_DEF)
 		etdev->RegistryNMIDisable = et131x_nmi_disable;

index 4032589..5c847ad 100644
@@ -113,9 +113,9 @@ void ConfigGlobalRegs(struct et131x_adapter *etdev)
 			 * 50/50:
 			 */
 			writel(0, &pGbl->rxq_start_addr.value);
-			writel(etdev->RegistryRxMemEnd,
+			writel(PARM_RX_MEM_END_DEF,
 			       &pGbl->rxq_end_addr.value);
-			writel(etdev->RegistryRxMemEnd + 1,
+			writel(PARM_RX_MEM_END_DEF + 1,
 			       &pGbl->txq_start_addr.value);
 			writel(INTERNAL_MEM_SIZE - 1,
 			       &pGbl->txq_end_addr.value);

index c60e05e..53efa08 100644
@@ -792,14 +792,14 @@ void ConfigRxDmaRegs(struct et131x_adapter *etdev)
 	 * For version B silicon, this value gets updated once autoneg is
 	 *complete.
 	 */
-	writel(etdev->RegistryRxNumBuffers, &pRxDma->num_pkt_done.value);
+	writel(PARM_RX_NUM_BUFS_DEF, &pRxDma->num_pkt_done.value);
 
 	/* The "time_done" is not working correctly to coalesce interrupts
 	 * after a given time period, but rather is giving us an interrupt
 	 * regardless of whether we have received packets.
 	 * This value gets updated once autoneg is complete.
 	 */
-	writel(etdev->RegistryRxTimeInterval, &pRxDma->max_pkt_time.value);
+	writel(PARM_RX_TIME_INT_DEF, &pRxDma->max_pkt_time.value);
 
 	spin_unlock_irqrestore(&etdev->RcvLock, flags);
 

@@ -1272,7 +1272,7 @@ void et131x_handle_recv_interrupt(struct et131x_adapter *etdev)
 
 	if ((PacketArrayCount == NUM_PACKETS_HANDLED) || TempUnfinishedRec) {
 		etdev->RxRing.UnfinishedReceives = true;
-		writel(etdev->RegistryTxTimeInterval * NANO_IN_A_MICRO,
+		writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
 		       &etdev->regs->global.watchdog_timer);
 	} else {
 		/* Watchdog timer will disable itself if appropriate. */

index 8e8486a..8472c1b 100644
@@ -94,6 +94,7 @@
 
 #include "et1310_tx.h"
 
+
 /* Data for debugging facilities */
 #ifdef CONFIG_ET131X_DEBUG
 extern dbg_info_t *et131x_dbginfo;

@@ -711,7 +712,7 @@ static int nic_send_packet(struct et131x_adapter *etdev, PMP_TCB pMpTcb)
 
 	if (etdev->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
 		if (++etdev->TxRing.TxPacketsSinceLastinterrupt ==
-		    etdev->RegistryTxNumBuffers) {
+		    PARM_TX_NUM_BUFS_DEF) {
 			CurDesc[FragmentNumber - 1].word3.value = 0x5;
 			etdev->TxRing.TxPacketsSinceLastinterrupt = 0;
 		} else {

@@ -794,7 +795,7 @@ static int nic_send_packet(struct et131x_adapter *etdev, PMP_TCB pMpTcb)
 	 * timer to wake us up if this packet isn't followed by N more.
 	 */
 	if (etdev->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
-		writel(etdev->RegistryTxTimeInterval * NANO_IN_A_MICRO,
+		writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
 		       &etdev->regs->global.watchdog_timer);
 	}
 

@@ -1064,7 +1065,7 @@ static int nic_send_packet(struct et131x_adapter *etdev, PMP_TCB pMpTcb)
 				    TRUEPHY_SPEED_1000MBPS) {
 					if (++etdev->TxRing.
 					    TxPacketsSinceLastinterrupt >=
-					    etdev->RegistryTxNumBuffers) {
+					    PARM_TX_NUM_BUFS_DEF) {
 						CurDesc.word3.value = 0x5;
 						etdev->TxRing.
 						    TxPacketsSinceLastinterrupt

@@ -1132,7 +1133,7 @@ static int nic_send_packet(struct et131x_adapter *etdev, PMP_TCB pMpTcb)
 
 		if (etdev->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
 			if (++etdev->TxRing.TxPacketsSinceLastinterrupt >=
-			    etdev->RegistryTxNumBuffers) {
+			    PARM_TX_NUM_BUFS_DEF) {
 				CurDesc.word3.value = 0x5;
 				etdev->TxRing.TxPacketsSinceLastinterrupt =
 				    0;

@@ -1212,7 +1213,7 @@ static int nic_send_packet(struct et131x_adapter *etdev, PMP_TCB pMpTcb)
 	 * timer to wake us up if this packet isn't followed by N more.
 	 */
 	if (etdev->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
-		writel(etdev->RegistryTxTimeInterval * NANO_IN_A_MICRO,
+		writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
 		       &etdev->regs->global.watchdog_timer);
 	}
 

index a7402a3..bbbada0 100644
@@ -260,12 +260,6 @@ struct et131x_adapter {
 	u32 RegistryVlanTag;	/* 802.1q Vlan TAG */
 	u32 RegistryJumboPacket;	/* Max supported ethernet packet size */
 
-	u32 RegistryTxNumBuffers;
-	u32 RegistryTxTimeInterval;
-
-	u32 RegistryRxNumBuffers;
-	u32 RegistryRxTimeInterval;
-
 	/* Validation helpers */
 	u8 RegistryNMIDisable;
 	u8 RegistryPhyLoopbk;	/* Enable Phy loopback */

index f8273d1..a31f82a 100644
@@ -129,26 +129,6 @@ extern dbg_info_t *et131x_dbginfo;
 #define PARM_PHY_COMA_MIN       0
 #define PARM_PHY_COMA_MAX       1
 
-#define PARM_RX_NUM_BUFS_DEF    4
-#define PARM_RX_NUM_BUFS_MIN    1
-#define PARM_RX_NUM_BUFS_MAX    64
-
-#define PARM_RX_TIME_INT_DEF    10
-#define PARM_RX_TIME_INT_MIN    2
-#define PARM_RX_TIME_INT_MAX    320
-
-#define PARM_TX_NUM_BUFS_DEF    4
-#define PARM_TX_NUM_BUFS_MIN    1
-#define PARM_TX_NUM_BUFS_MAX    40
-
-#define PARM_TX_TIME_INT_DEF    40
-#define PARM_TX_TIME_INT_MIN    1
-#define PARM_TX_TIME_INT_MAX    140
-
-#define PARM_RX_MEM_END_DEF     0x2bc
-#define PARM_RX_MEM_END_MIN     0
-#define PARM_RX_MEM_END_MAX     0x3ff
-
 #define PARM_MAC_STAT_DEF       1
 #define PARM_MAC_STAT_MIN       0
 #define PARM_MAC_STAT_MAX       1

@@ -166,8 +146,6 @@ extern dbg_info_t *et131x_dbginfo;
 #define PARM_NMI_DISABLE_MAX    2
 
 #define PARM_DMA_CACHE_DEF      0
-#define PARM_DMA_CACHE_MIN      0
-#define PARM_DMA_CACHE_MAX      15
 
 #define PARM_PHY_LOOPBK_DEF     0
 #define PARM_PHY_LOOPBK_MIN     0

@@ -249,11 +227,6 @@ void et131x_config_parse(struct et131x_adapter *etdev)
 	etdev->RegistryFlowControl = PARM_FLOW_CTL_DEF;
 	etdev->RegistryJumboPacket = PARM_JUMBO_PKT_DEF;
 	etdev->RegistryPhyComa = PARM_PHY_COMA_DEF;
-	etdev->RegistryRxNumBuffers = PARM_RX_NUM_BUFS_DEF;
-	etdev->RegistryRxTimeInterval = PARM_RX_TIME_INT_DEF;
-	etdev->RegistryTxNumBuffers = PARM_TX_NUM_BUFS_DEF;
-	etdev->RegistryTxTimeInterval = PARM_TX_TIME_INT_DEF;
-	etdev->RegistryRxMemEnd = PARM_RX_MEM_END_DEF;
 	etdev->RegistryMACStat = PARM_MAC_STAT_DEF;
 
 	if (et131x_nmi_disable != PARM_NMI_DISABLE_DEF)

index 9d609e5..5665c6a 100644
@@ -125,4 +125,12 @@
 /* Define order of magnitude converter */
 #define NANO_IN_A_MICRO	1000
 
+#define PARM_RX_NUM_BUFS_DEF    4
+#define PARM_RX_TIME_INT_DEF    10
+#define PARM_RX_MEM_END_DEF     0x2bc
+#define PARM_TX_TIME_INT_DEF    40
+#define PARM_TX_NUM_BUFS_DEF    4
+#define PARM_DMA_CACHE_DEF      0
+
+
 #endif /* __ET131X_DEFS_H__ */

index bbbada0..63d7c8a 100644
@@ -256,8 +256,6 @@ struct et131x_adapter {
 	u8 RegistryPhyComa;	/* Phy Coma mode enable/disable */
 
 	u32 RegistryRxMemEnd;	/* Size of internal rx memory */
-	u8 RegistryMACStat;	/* If set, read MACSTAT, else don't */
-	u32 RegistryVlanTag;	/* 802.1q Vlan TAG */
 	u32 RegistryJumboPacket;	/* Max supported ethernet packet size */
 
 	/* Validation helpers */

174 lines not on this page · raw message

index 4d45941..c489090 100644
@@ -442,10 +442,9 @@ void et131x_error_timer_handler(unsigned long data)
 
 	pm_csr.value = readl(&etdev->regs->global.pm_csr.value);
 
-	if (pm_csr.bits.pm_phy_sw_coma == 0) {
-		if (etdev->RegistryMACStat)
-			UpdateMacStatHostCounters(etdev);
-	} else
+	if (pm_csr.bits.pm_phy_sw_coma == 0)
+		UpdateMacStatHostCounters(etdev);
+	else
 		DBG_VERBOSE(et131x_dbginfo,
 			    "No interrupts, in PHY coma, pm_csr = 0x%x\n",
 			    pm_csr.value);

index 358e6f6..cde727d 100644
@@ -101,58 +101,30 @@ extern dbg_info_t *et131x_dbginfo;
 #endif /* CONFIG_ET131X_DEBUG */
 
 /* Defines for Parameter Default/Min/Max vaules */
-#define PARM_SPEED_DUPLEX_DEF   0
 #define PARM_SPEED_DUPLEX_MIN   0
 #define PARM_SPEED_DUPLEX_MAX   5
 
-#define PARM_FLOW_CTL_DEF       0
-#define PARM_FLOW_CTL_MIN       0
-#define PARM_FLOW_CTL_MAX       3
-
-#define PARM_JUMBO_PKT_DEF      1514
-#define PARM_JUMBO_PKT_MIN      1514
-#define PARM_JUMBO_PKT_MAX      9216
-
-#define PARM_PHY_COMA_DEF       0
-#define PARM_PHY_COMA_MIN       0
-#define PARM_PHY_COMA_MAX       1
-
-#define PARM_SC_GAIN_DEF        7
-#define PARM_SC_GAIN_MIN        0
-#define PARM_SC_GAIN_MAX        7
-
-#define PARM_PM_WOL_DEF         0
-#define PARM_PM_WOL_MIN         0
-#define PARM_PM_WOL_MAX         1
-
-#define PARM_NMI_DISABLE_DEF    0
-#define PARM_NMI_DISABLE_MIN    0
-#define PARM_NMI_DISABLE_MAX    2
-
-
-
 /* Module parameter for disabling NMI
- * et131x_speed_set :
+ * et131x_nmi_disable :
+ * Disable NMI (0-2) [0]
+ *  0 :
+ *  1 :
+ *  2 :
+ */
+static u32 et131x_nmi_disable;	/* 0-2 */
+module_param(et131x_nmi_disable, uint, 0);
+MODULE_PARM_DESC(et131x_nmi_disable, "Disable NMI (0-2) [0]");
+
+/* Module parameter for manual speed setting
  * Set Link speed and dublex manually (0-5)  [0]
  *  1 : 10Mb   Half-Duplex
  *  2 : 10Mb   Full-Duplex
  *  3 : 100Mb  Half-Duplex
  *  4 : 100Mb  Full-Duplex
  *  5 : 1000Mb Full-Duplex
- *  0 : Auto Speed Auto Dublex // default
- */
-static u32 et131x_nmi_disable = PARM_NMI_DISABLE_DEF;
-module_param(et131x_nmi_disable, uint, 0);
-MODULE_PARM_DESC(et131x_nmi_disable, "Disable NMI (0-2) [0]");
-
-/* Module parameter for manual speed setting
- * et131x_nmi_disable :
- * Disable NMI (0-2) [0]
- *  0 :
- *  1 :
- *  2 :
+ *  0 : Auto Speed Auto Duplex // default
  */
-static u32 et131x_speed_set = PARM_SPEED_DUPLEX_DEF;
+static u32 et131x_speed_set;
 module_param(et131x_speed_set, uint, 0);
 MODULE_PARM_DESC(et131x_speed_set,
 		"Set Link speed and dublex manually (0-5)  [0] \n  1 : 10Mb   Half-Duplex \n  2 : 10Mb   Full-Duplex \n  3 : 100Mb  Half-Duplex \n  4 : 100Mb  Full-Duplex \n  5 : 1000Mb Full-Duplex \n 0 : Auto Speed Auto Dublex");

@@ -175,33 +147,22 @@ void et131x_config_parse(struct et131x_adapter *etdev)
 
 	DBG_ENTER(et131x_dbginfo);
 
-	etdev->SpeedDuplex = et131x_speed_set;
-
 	if (et131x_speed_set < PARM_SPEED_DUPLEX_MIN ||
 	    et131x_speed_set > PARM_SPEED_DUPLEX_MAX) {
 	    	dev_warn(&etdev->pdev->dev, "invalid speed setting ignored.\n");
-	    	et131x_speed_set = PARM_SPEED_DUPLEX_DEF;
+	    	et131x_speed_set = 0;
 	}
-	else if (et131x_speed_set != PARM_SPEED_DUPLEX_DEF)
+	else if (et131x_speed_set)
 		DBG_VERBOSE(et131x_dbginfo, "Speed set manually to : %d \n",
 			    et131x_speed_set);
 
-	/*  etdev->SpeedDuplex            = PARM_SPEED_DUPLEX_DEF; */
-
-	etdev->RegistryFlowControl = PARM_FLOW_CTL_DEF;
-	etdev->RegistryJumboPacket = PARM_JUMBO_PKT_DEF;
-	etdev->RegistryPhyComa = PARM_PHY_COMA_DEF;
-
-	if (et131x_nmi_disable != PARM_NMI_DISABLE_DEF)
-		etdev->RegistryNMIDisable = et131x_nmi_disable;
-	else
-		etdev->RegistryNMIDisable = PARM_NMI_DISABLE_DEF;
+	etdev->SpeedDuplex = et131x_speed_set;
+	etdev->RegistryJumboPacket = 1514;	/* 1514-9216 */
 
-	etdev->RegistryPhyLoopbk = 0;	/* 0 off 1 on */
+	etdev->RegistryNMIDisable = et131x_nmi_disable;
 
 	/* Set the MAC address to a default */
 	memcpy(etdev->CurrentAddress, default_mac, ETH_ALEN);
-	etdev->bOverrideAddress = false;
 
 	/* Decode SpeedDuplex
 	 *

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104 lines not on this page · raw message

index 29d1c0e..9453862 100644
@@ -137,34 +137,34 @@
  * Define macros that allow individual register values to be extracted from a
  * DWORD1 register grouping
  */
-#define EXTRACT_DATA_REGISTER(x)    (uint8_t)(x & 0xFF)
-#define EXTRACT_STATUS_REGISTER(x)  (uint8_t)((x >> 16) & 0xFF)
-#define EXTRACT_CONTROL_REG(x)      (uint8_t)((x >> 8) & 0xFF)
+#define EXTRACT_DATA_REGISTER(x)    (u8)(x & 0xFF)
+#define EXTRACT_STATUS_REGISTER(x)  (u8)((x >> 16) & 0xFF)
+#define EXTRACT_CONTROL_REG(x)      (u8)((x >> 8) & 0xFF)
 
 /**
  * EepromWriteByte - Write a byte to the ET1310's EEPROM
  * @etdev: pointer to our private adapter structure
- * @unAddress: the address to write
- * @bData: the value to write
- * @unEepronId: the ID of the EEPROM
- * @unAddressingMode: how the EEPROM is to be accessed
+ * @addr: the address to write
+ * @data: the value to write
+ * @eeprom_id: the ID of the EEPROM
+ * @addrmode: how the EEPROM is to be accessed
  *
  * Returns SUCCESS or FAILURE
  */
-int32_t EepromWriteByte(struct et131x_adapter *etdev, uint32_t unAddress,
-			uint8_t bData, uint32_t unEepromId,
-			uint32_t unAddressingMode)
+int EepromWriteByte(struct et131x_adapter *etdev, u32 addr,
+			u8 data, u32 eeprom_id,
+			u32 addrmode)
 {
 	struct pci_dev *pdev = etdev->pdev;
-	int32_t nIndex;
-	int32_t nRetries;
-	int32_t nError = false;
-	int32_t nI2CWriteActive = 0;
-	int32_t nWriteSuccessful = 0;
-	uint8_t bControl;
-	uint8_t bStatus = 0;
-	uint32_t unDword1 = 0;
-	uint32_t unData = 0;
+	int index;
+	int retries;
+	int err = 0;
+	int i2c_wack = 0;
+	int writeok = 0;
+	u8 control;
+	u8 status = 0;
+	u32 dword1 = 0;
+	u32 val = 0;
 
 	/*
 	 * The following excerpt is from "Serial EEPROM HW Design

@@ -215,89 +215,89 @@ int32_t EepromWriteByte(struct et131x_adapter *etdev, uint32_t unAddress,
 	 */
 
 	/* Step 1: */
-	for (nIndex = 0; nIndex < MAX_NUM_REGISTER_POLLS; nIndex++) {
+	for (index = 0; index < MAX_NUM_REGISTER_POLLS; index++) {
 		/* Read registers grouped in DWORD1 */
 		if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP_OFFSET,
-					  &unDword1)) {
-			nError = 1;
+					  &dword1)) {
+			err = 1;
 			break;
 		}
 
-		bStatus = EXTRACT_STATUS_REGISTER(unDword1);
+		status = EXTRACT_STATUS_REGISTER(dword1);
 
-		if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL &&
-			bStatus & LBCIF_STATUS_I2C_IDLE)
+		if (status & LBCIF_STATUS_PHY_QUEUE_AVAIL &&
+			status & LBCIF_STATUS_I2C_IDLE)
 			/* bits 1:0 are equal to 1 */
 			break;
 	}
 
-	if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS))
+	if (err || (index >= MAX_NUM_REGISTER_POLLS))
 		return FAILURE;
 
 	/* Step 2: */
-	bControl = 0;
-	bControl |= LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE;
+	control = 0;
+	control |= LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE;
 
-	if (unAddressingMode == DUAL_BYTE)
-		bControl |= LBCIF_CONTROL_TWO_BYTE_ADDR;
+	if (addrmode == DUAL_BYTE)
+		control |= LBCIF_CONTROL_TWO_BYTE_ADDR;
 
 	if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER_OFFSET,
-				  bControl)) {
+				  control)) {
 		return FAILURE;
 	}
 
-	nI2CWriteActive = 1;
+	i2c_wack = 1;
 
 	/* Prepare EEPROM address for Step 3 */
-	unAddress |= (unAddressingMode == DUAL_BYTE) ?
-	    (unEepromId << 16) : (unEepromId << 8);
+	addr |= (addrmode == DUAL_BYTE) ?
+	    (eeprom_id << 16) : (eeprom_id << 8);
 
-	for (nRetries = 0; nRetries < MAX_NUM_WRITE_RETRIES; nRetries++) {
+	for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) {
 		/* Step 3:*/
 		if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER_OFFSET,
-					   unAddress)) {
+					   addr)) {
 			break;
 		}
 
 		/* Step 4: */
 		if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER_OFFSET,
-					  bData)) {
+					  data)) {
 			break;
 		}
 
 		/* Step 5: */
-		for (nIndex = 0; nIndex < MAX_NUM_REGISTER_POLLS; nIndex++) {
+		for (index = 0; index < MAX_NUM_REGISTER_POLLS; index++) {
 			/* Read registers grouped in DWORD1 */
 			if (pci_read_config_dword(pdev,
 						  LBCIF_DWORD1_GROUP_OFFSET,
-						  &unDword1)) {
-				nError = 1;
+						  &dword1)) {
+				err = 1;
 				break;
 			}
 
-			bStatus = EXTRACT_STATUS_REGISTER(unDword1);
+			status = EXTRACT_STATUS_REGISTER(dword1);
 
-			if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL &&
-				bStatus & LBCIF_STATUS_I2C_IDLE) {
+			if (status & LBCIF_STATUS_PHY_QUEUE_AVAIL &&
+				status & LBCIF_STATUS_I2C_IDLE) {
 				/* I2C write complete */
 				break;
 			}
 		}
 
-		if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS))
+		if (err || (index >= MAX_NUM_REGISTER_POLLS))
 			break;
 
 		/*
 		 * Step 6: Don't break here if we are revision 1, this is
 		 *	   so we do a blind write for load bug.
 		 */
-		if (bStatus & LBCIF_STATUS_GENERAL_ERROR
+		if (status & LBCIF_STATUS_GENERAL_ERROR
 		    && etdev->pdev->revision == 0) {
 			break;
 		}
 
 		/* Step 7 */
-		if (bStatus & LBCIF_STATUS_ACK_ERROR) {
+		if (status & LBCIF_STATUS_ACK_ERROR) {
 			/*
 			 * This could be due to an actual hardware failure
 			 * or the EEPROM may still be in its internal write

@@ -308,19 +308,19 @@ int32_t EepromWriteByte(struct et131x_adapter *etdev, uint32_t unAddress,
 			continue;
 		}
 
-		nWriteSuccessful = 1;
+		writeok = 1;
 		break;
 	}
 
 	/* Step 8: */
 	udelay(10);
-	nIndex = 0;
-	while (nI2CWriteActive) {
-		bControl &= ~LBCIF_CONTROL_I2C_WRITE;
+	index = 0;
+	while (i2c_wack) {
+		control &= ~LBCIF_CONTROL_I2C_WRITE;
 
 		if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER_OFFSET,
-					  bControl)) {
-			nWriteSuccessful = 0;
+					  control)) {
+			writeok = 0;
 		}
 
 		/* Do read until internal ACK_ERROR goes away meaning write

@@ -329,44 +329,44 @@ int32_t EepromWriteByte(struct et131x_adapter *etdev, uint32_t unAddress,
 		do {
 			pci_write_config_dword(pdev,
 					       LBCIF_ADDRESS_REGISTER_OFFSET,
-					       unAddress);
+					       addr);
 			do {
 				pci_read_config_dword(pdev,
-					LBCIF_DATA_REGISTER_OFFSET, &unData);
-			} while ((unData & 0x00010000) == 0);
-		} while (unData & 0x00040000);
+					LBCIF_DATA_REGISTER_OFFSET, &val);
+			} while ((val & 0x00010000) == 0);
+		} while (val & 0x00040000);
 
-		bControl = EXTRACT_CONTROL_REG(unData);
+		control = EXTRACT_CONTROL_REG(val);
 
-		if (bControl != 0xC0 || nIndex == 10000)
+		if (control != 0xC0 || index == 10000)
 			break;
 
-		nIndex++;
+		index++;
 	}
 
-	return nWriteSuccessful ? SUCCESS : FAILURE;
+	return writeok ? SUCCESS : FAILURE;
 }
 
 /**
  * EepromReadByte - Read a byte from the ET1310's EEPROM
  * @etdev: pointer to our private adapter structure
- * @unAddress: the address from which to read
- * @pbData: a pointer to a byte in which to store the value of the read
- * @unEepronId: the ID of the EEPROM
- * @unAddressingMode: how the EEPROM is to be accessed
+ * @addr: the address from which to read
+ * @pdata: a pointer to a byte in which to store the value of the read
+ * @eeprom_id: the ID of the EEPROM
+ * @addrmode: how the EEPROM is to be accessed
  *
  * Returns SUCCESS or FAILURE
  */
-int32_t EepromReadByte(struct et131x_adapter *etdev, uint32_t unAddress,
-		       uint8_t *pbData, uint32_t unEepromId,
-		       uint32_t unAddressingMode)
+int EepromReadByte(struct et131x_adapter *etdev, u32 addr,
+		       u8 *pdata, u32 eeprom_id,
+		       u32 addrmode)
 {
 	struct pci_dev *pdev = etdev->pdev;
-	int32_t nIndex;
-	int32_t nError = 0;
-	uint8_t bControl;
-	uint8_t bStatus = 0;
-	uint32_t unDword1 = 0;
+	int index;
+	int err = 0;
+	u8 control;
+	u8 status = 0;
+	u32 dword1 = 0;
 
 	/*
 	 * The following excerpt is from "Serial EEPROM HW Design

@@ -403,70 +403,70 @@ int32_t EepromReadByte(struct et131x_adapter *etdev, uint32_t unAddress,
 	 */
 
 	/* Step 1: */
-	for (nIndex = 0; nIndex < MAX_NUM_REGISTER_POLLS; nIndex++) {
+	for (index = 0; index < MAX_NUM_REGISTER_POLLS; index++) {
 		/* Read registers grouped in DWORD1 */
 		if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP_OFFSET,
-					  &unDword1)) {
-			nError = 1;
+					  &dword1)) {
+			err = 1;
 			break;
 		}
 
-		bStatus = EXTRACT_STATUS_REGISTER(unDword1);
+		status = EXTRACT_STATUS_REGISTER(dword1);
 
-		if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL &&
-		    bStatus & LBCIF_STATUS_I2C_IDLE) {
+		if (status & LBCIF_STATUS_PHY_QUEUE_AVAIL &&
+		    status & LBCIF_STATUS_I2C_IDLE) {
 			/* bits 1:0 are equal to 1 */
 			break;
 		}
 	}
 
-	if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS))
+	if (err || (index >= MAX_NUM_REGISTER_POLLS))
 		return FAILURE;
 
 	/* Step 2: */
-	bControl = 0;
-	bControl |= LBCIF_CONTROL_LBCIF_ENABLE;
+	control = 0;
+	control |= LBCIF_CONTROL_LBCIF_ENABLE;
 
-	if (unAddressingMode == DUAL_BYTE)
-		bControl |= LBCIF_CONTROL_TWO_BYTE_ADDR;
+	if (addrmode == DUAL_BYTE)
+		control |= LBCIF_CONTROL_TWO_BYTE_ADDR;
 
 	if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER_OFFSET,
-				  bControl)) {
+				  control)) {
 		return FAILURE;
 	}
 
 	/* Step 3: */
-	unAddress |= (unAddressingMode == DUAL_BYTE) ?
-	    (unEepromId << 16) : (unEepromId << 8);
+	addr |= (addrmode == DUAL_BYTE) ?
+	    (eeprom_id << 16) : (eeprom_id << 8);
 
 	if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER_OFFSET,
-				   unAddress)) {
+				   addr)) {
 		return FAILURE;
 	}
 
 	/* Step 4: */
-	for (nIndex = 0; nIndex < MAX_NUM_REGISTER_POLLS; nIndex++) {
+	for (index = 0; index < MAX_NUM_REGISTER_POLLS; index++) {
 		/* Read registers grouped in DWORD1 */
 		if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP_OFFSET,
-					  &unDword1)) {
-			nError = 1;
+					  &dword1)) {
+			err = 1;
 			break;
 		}
 
-		bStatus = EXTRACT_STATUS_REGISTER(unDword1);
+		status = EXTRACT_STATUS_REGISTER(dword1);
 
-		if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL
-		    && bStatus & LBCIF_STATUS_I2C_IDLE) {
+		if (status & LBCIF_STATUS_PHY_QUEUE_AVAIL
+		    && status & LBCIF_STATUS_I2C_IDLE) {
 			/* I2C read complete */
 			break;
 		}
 	}
 
-	if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS))
+	if (err || (index >= MAX_NUM_REGISTER_POLLS))
 		return FAILURE;
 
 	/* Step 6: */
-	*pbData = EXTRACT_DATA_REGISTER(unDword1);
+	*pdata = EXTRACT_DATA_REGISTER(dword1);
 
-	return (bStatus & LBCIF_STATUS_ACK_ERROR) ? FAILURE : SUCCESS;
+	return (status & LBCIF_STATUS_ACK_ERROR) ? FAILURE : SUCCESS;
 }

index 9461a2d..b2123d0 100644
@@ -195,7 +195,7 @@ void ConfigMACRegs2(struct et131x_adapter *etdev)
 	cfg2.value = readl(&pMac->cfg2.value);
 	ifctrl.value = readl(&pMac->if_ctrl.value);
 
-	if (etdev->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
+	if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS) {
 		cfg2.bits.if_mode = 0x2;
 		ifctrl.bits.phy_mode = 0x0;
 	} else {

@@ -241,8 +241,8 @@ void ConfigMACRegs2(struct et131x_adapter *etdev)
 	}
 
 	/* 1 - full duplex, 0 - half-duplex */
-	cfg2.bits.full_duplex = etdev->uiDuplexMode;
-	ifctrl.bits.ghd_mode = !etdev->uiDuplexMode;
+	cfg2.bits.full_duplex = etdev->duplex_mode;
+	ifctrl.bits.ghd_mode = !etdev->duplex_mode;
 
 	writel(ifctrl.value, &pMac->if_ctrl.value);
 	writel(cfg2.value, &pMac->cfg2.value);

@@ -262,7 +262,7 @@ void ConfigMACRegs2(struct et131x_adapter *etdev)
 
 	DBG_TRACE(et131x_dbginfo,
 		"Speed %d, Dup %d, CFG1 0x%08x, CFG2 0x%08x, if_ctrl 0x%08x\n",
-		etdev->uiLinkSpeed, etdev->uiDuplexMode,
+		etdev->linkspeed, etdev->duplex_mode,
 		readl(&pMac->cfg1.value), readl(&pMac->cfg2.value),
 		readl(&pMac->if_ctrl.value));
 

@@ -408,7 +408,7 @@ void ConfigRxMacRegs(struct et131x_adapter *etdev)
 	 * bit 16: Receive frame truncated.
 	 * bit 17: Drop packet enable
 	 */
-	if (etdev->uiLinkSpeed == TRUEPHY_SPEED_100MBPS)
+	if (etdev->linkspeed == TRUEPHY_SPEED_100MBPS)
 		writel(0x30038, &pRxMac->mif_ctrl.value);
 	else
 		writel(0x30030, &pRxMac->mif_ctrl.value);

@@ -540,7 +540,7 @@ void ConfigMacStatRegs(struct et131x_adapter *etdev)
 
 void ConfigFlowControl(struct et131x_adapter *etdev)
 {
-	if (etdev->uiDuplexMode == 0) {
+	if (etdev->duplex_mode == 0) {
 		etdev->FlowControl = None;
 	} else {
 		char RemotePause, RemoteAsyncPause;

479 lines not on this page · raw message

index 34e08e8..aec0a7b 100644
@@ -895,12 +895,12 @@ void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *adapter,
 void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *adapter,
 				u16 duplex);
 void ET1310_PhyLinkStatus(struct et131x_adapter *adapter,
-			  u8 *ucLinkStatus,
-			  u32 *uiAutoNeg,
-			  u32 *uiLinkSpeed,
-			  u32 *uiDuplexMode,
-			  u32 *uiMdiMdix,
-			  u32 *uiMasterSlave, u32 *uiPolarity);
+			  u8 *Link_status,
+			  u32 *autoneg,
+			  u32 *linkspeed,
+			  u32 *duplex_mode,
+			  u32 *mdi_mdix,
+			  u32 *masterslave, u32 *polarity);
 void ET1310_PhyAndOrReg(struct et131x_adapter *adapter,
 			u16 regnum, u16 andMask, u16 orMask);
 void ET1310_PhyAccessMiBit(struct et131x_adapter *adapter,

267 lines not on this page · raw message

273 lines not on this page · raw message

index 63d7c8a..3ac2343 100644
@@ -133,8 +133,8 @@ typedef struct _MP_RFD {
 	struct list_head list_node;
 	struct sk_buff *Packet;
 	u32 PacketSize;	/* total size of receive frame */
-	u16 iBufferIndex;
-	u8 iRingIndex;
+	u16 bufferindex;
+	u8 ringindex;
 } MP_RFD, *PMP_RFD;
 
 /* Enum for Flow Control */

@@ -214,8 +214,7 @@ struct et131x_adapter {
 	/* Configuration  */
 	u8 PermanentAddress[ETH_ALEN];
 	u8 CurrentAddress[ETH_ALEN];
-	bool bOverrideAddress;
-	bool bEepromPresent;
+	bool has_eeprom;
 	u8 eepromData[2];
 
 	/* Spinlocks */

@@ -234,11 +233,8 @@ struct et131x_adapter {
 
 	/* Packet Filter and look ahead size */
 	u32 PacketFilter;
-	u32 ulLookAhead;
-	u32 uiLinkSpeed;
-	u32 uiDuplexMode;
-	u32 uiAutoNegStatus;
-	u8 ucLinkStatus;
+	u32 linkspeed;
+	u32 duplex_mode;
 
 	/* multicast list */
 	u32 MCAddressCount;

@@ -275,11 +271,7 @@ struct et131x_adapter {
 	u8 DriverNoPhyAccess;
 
 	/* Minimize init-time */
-	bool bQueryPending;
-	bool bSetPending;
-	bool bResetPending;
 	struct timer_list ErrorTimer;
-	bool bLinkTimerActive;
 	MP_POWER_MGMT PoMgmt;
 	INTERRUPT_t CachedMaskValue;
 

118 lines not on this page · raw message

index 78228af..0807a01 100644
@@ -65,8 +65,6 @@
 #define INTERNAL_MEM_SIZE       0x400	/* 1024 of internal memory */
 #define INTERNAL_MEM_RX_OFFSET  0x1FF	/* 50%   Tx, 50%   Rx */
 
-#define REGS_MAX_ARRAY          4096
-
 /*
  * For interrupts, normal running is:
  *       rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,

@@ -85,23 +83,6 @@
 #define INT_MASK_ENABLE             0xfffebf17
 #define INT_MASK_ENABLE_NO_FLOW     0xfffebfd7
 
-/* DATA STRUCTURES FOR DIRECT REGISTER ACCESS */
-
-typedef struct {
-	u8 bReadWrite;
-	u32 nRegCount;
-	u32 nData[REGS_MAX_ARRAY];
-	u32 nOffsets[REGS_MAX_ARRAY];
-} JAGCORE_ACCESS_REGS, *PJAGCORE_ACCESS_REGS;
-
-typedef struct {
-	u8 bReadWrite;
-	u32 nDataWidth;
-	u32 nRegCount;
-	u32 nOffsets[REGS_MAX_ARRAY];
-	u32 nData[REGS_MAX_ARRAY];
-} PCI_CFG_SPACE_REGS, *PPCI_CFG_SPACE_REGS;
-
 /* Forward declaration of the private adapter structure */
 struct et131x_adapter;
 

index a16ce16..19ffb65 100644
@@ -547,7 +547,7 @@ void et131x_Mii_check(struct et131x_adapter *etdev,
 			}
 
 			etdev->linkspeed = 0;
-			etdev->duplexMode = 0;
+			etdev->duplex_mode = 0;
 
 			/* Free the packets being actively sent & stopped */
 			et131x_free_busy_send_packets(etdev);

index 3ac2343..04bb603 100644
@@ -284,10 +284,6 @@ struct et131x_adapter {
 	/* Rx Memory Variables */
 	RX_RING_t RxRing;
 
-	/* ET1310 register Access */
-	JAGCORE_ACCESS_REGS JagCoreRegs;
-	PCI_CFG_SPACE_REGS PciCfgRegs;
-
 	/* Loopback specifics */
 	u8 ReplicaPhyLoopbk;	/* Replica Enable */
 	u8 ReplicaPhyLoopbkPF;	/* Replica Enable Pass/Fail */

index aec0a7b..080656c 100644
@@ -63,9 +63,6 @@
 
 #define TRUEPHY_SUCCESS 0
 #define TRUEPHY_FAILURE 1
-typedef void *TRUEPHY_HANDLE;
-typedef void *TRUEPHY_PLATFORM_HANDLE;
-typedef void *TRUEPHY_OSAL_HANDLE;
 
 /* MI Register Addresses */
 #define MI_CONTROL_REG                      0

@@ -742,28 +739,6 @@ typedef union _MI_LCR2_t {
 
 /* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */
 
-/* TruePHY headers */
-typedef struct _TRUEPHY_ACCESS_MI_REGS_ {
-	TRUEPHY_HANDLE hTruePhy;
-	int32_t nPhyId;
-	u8 bReadWrite;
-	u8 *pbyRegs;
-	u8 *pwData;
-	int32_t nRegCount;
-} TRUEPHY_ACCESS_MI_REGS, *PTRUEPHY_ACCESS_MI_REGS;
-
-/* TruePHY headers */
-typedef struct _TAG_TPAL_ACCESS_MI_REGS_ {
-	u32 nPhyId;
-	u8 bReadWrite;
-	u32 nRegCount;
-	u16 Data[4096];
-	u8 Regs[4096];
-} TPAL_ACCESS_MI_REGS, *PTPAL_ACCESS_MI_REGS;
-
-
-typedef TRUEPHY_HANDLE TPAL_HANDLE;
-
 /* Forward declaration of the private adapter structure */
 struct et131x_adapter;
 

index 8e06039..295f3ab 100644
@@ -61,54 +61,24 @@
 
 #include "et1310_address_map.h"
 
-#define MAX_WOL_PACKET_SIZE    0x80
-#define MAX_WOL_MASK_SIZE      (MAX_WOL_PACKET_SIZE / 8)
-#define NUM_WOL_PATTERNS       0x5
-#define CRC16_POLY             0x1021
-
 typedef struct _MP_POWER_MGMT {
 	/* variable putting the phy into coma mode when boot up with no cable
 	 * plugged in after 5 seconds
 	 */
 	u8 TransPhyComaModeOnBoot;
 
-	/* Array holding the five CRC values that the device is currently
-	 * using for WOL.  This will be queried when a pattern is to be
-	 * removed.
-	 */
-	u32 localWolAndCrc0;
-	u16 WOLPatternList[NUM_WOL_PATTERNS];
-	u8 WOLMaskList[NUM_WOL_PATTERNS][MAX_WOL_MASK_SIZE];
-	u32 WOLMaskSize[NUM_WOL_PATTERNS];
-
-	/* IP address */
-	union {
-		u32 u32;
-		u8 u8[4];
-	} IPAddress;
-
-	/* Current Power state of the adapter. */
-	bool WOLState;
-	bool WOLEnabled;
-	bool Failed10Half;
-	bool bFailedStateTransition;
-
 	/* Next two used to save power information at power down. This
 	 * information will be used during power up to set up parts of Power
 	 * Management in JAGCore
 	 */
-	u32 tx_en;
-	u32 rx_en;
 	u16 PowerDownSpeed;
 	u8 PowerDownDuplex;
 } MP_POWER_MGMT, *PMP_POWER_MGMT;
 
 /* Forward declaration of the private adapter structure
- * ( IS THERE A WAY TO DO THIS WITH A TYPEDEF??? )
  */
 struct et131x_adapter;
 
-u16 CalculateCCITCRC16(u8 *Pattern, u8 *Mask, u32 MaskSize);
 void EnablePhyComa(struct et131x_adapter *adapter);
 void DisablePhyComa(struct et131x_adapter *adapter);
 

index 5665c6a..f98dca5 100644
@@ -61,7 +61,6 @@
 
 /* Packet and header sizes */
 #define NIC_MIN_PACKET_SIZE	60
-#define NIC_HEADER_SIZE		ETH_HLEN	/* 14 */
 
 /* Multicast list size */
 #define NIC_MAX_MCAST_LIST	128

@@ -102,20 +101,13 @@
 #define fMP_ADAPTER_NOT_READY_MASK	0x3ff00000
 
 /* Some offsets in PCI config space that are actually used. */
-#define ET1310_PCI_PM_CAPABILITY	0x40
-#define ET1310_PCI_PM_CSR		0x44
 #define ET1310_PCI_MAX_PYLD		0x4C
-#define ET1310_PCI_DEV_CTRL		0x50
-#define ET1310_PCI_DEV_STAT		0x52
 #define ET1310_NMI_DISABLE		0x61
 #define ET1310_PCI_MAC_ADDRESS		0xA4
 #define ET1310_PCI_EEPROM_STATUS	0xB2
-#define ET1310_PCI_PHY_INDEX_REG	0xB4
 #define ET1310_PCI_ACK_NACK		0xC0
 #define ET1310_PCI_REPLAY		0xC2
 #define ET1310_PCI_L0L1LATENCY		0xCF
-#define ET1310_PCI_SEL_PHY_CTRL		0xE4
-#define ET1310_PCI_ADVANCED_ERR		0x100
 
 /* PCI Vendor/Product IDs */
 #define ET131X_PCI_VENDOR_ID		0x11C1	/* Agere Systems */

index 9453862..7b2e4ea 100644
@@ -146,14 +146,10 @@
  * @etdev: pointer to our private adapter structure
  * @addr: the address to write
  * @data: the value to write
- * @eeprom_id: the ID of the EEPROM
- * @addrmode: how the EEPROM is to be accessed
  *
  * Returns SUCCESS or FAILURE
  */
-int EepromWriteByte(struct et131x_adapter *etdev, u32 addr,
-			u8 data, u32 eeprom_id,
-			u32 addrmode)
+int EepromWriteByte(struct et131x_adapter *etdev, u32 addr, u8 data)
 {
 	struct pci_dev *pdev = etdev->pdev;
 	int index;

@@ -238,9 +234,6 @@ int EepromWriteByte(struct et131x_adapter *etdev, u32 addr,
 	control = 0;
 	control |= LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE;
 
-	if (addrmode == DUAL_BYTE)
-		control |= LBCIF_CONTROL_TWO_BYTE_ADDR;
-
 	if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER_OFFSET,
 				  control)) {
 		return FAILURE;

@@ -249,8 +242,6 @@ int EepromWriteByte(struct et131x_adapter *etdev, u32 addr,
 	i2c_wack = 1;
 
 	/* Prepare EEPROM address for Step 3 */
-	addr |= (addrmode == DUAL_BYTE) ?
-	    (eeprom_id << 16) : (eeprom_id << 8);
 
 	for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) {
 		/* Step 3:*/

@@ -357,9 +348,7 @@ int EepromWriteByte(struct et131x_adapter *etdev, u32 addr,
  *
  * Returns SUCCESS or FAILURE
  */
-int EepromReadByte(struct et131x_adapter *etdev, u32 addr,
-		       u8 *pdata, u32 eeprom_id,
-		       u32 addrmode)
+int EepromReadByte(struct et131x_adapter *etdev, u32 addr, u8 *pdata)
 {
 	struct pci_dev *pdev = etdev->pdev;
 	int index;

@@ -427,17 +416,12 @@ int EepromReadByte(struct et131x_adapter *etdev, u32 addr,
 	control = 0;
 	control |= LBCIF_CONTROL_LBCIF_ENABLE;
 
-	if (addrmode == DUAL_BYTE)
-		control |= LBCIF_CONTROL_TWO_BYTE_ADDR;
-
 	if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER_OFFSET,
 				  control)) {
 		return FAILURE;
 	}
 
 	/* Step 3: */
-	addr |= (addrmode == DUAL_BYTE) ?
-	    (eeprom_id << 16) : (eeprom_id << 8);
 
 	if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER_OFFSET,
 				   addr)) {

index 8033743..d8ac9a0 100644
@@ -66,24 +66,12 @@
 #define FAILURE		1
 #endif
 
-#ifndef READ
-#define READ		0
-#define WRITE		1
-#endif
-
-#ifndef SINGLE_BYTE
-#define SINGLE_BYTE	0
-#define DUAL_BYTE	1
-#endif
-
 /* Forward declaration of the private adapter structure */
 struct et131x_adapter;
 
 int32_t EepromWriteByte(struct et131x_adapter *adapter, u32 unAddress,
-			u8 bData, u32 unEepromId,
-			u32 unAddressingMode);
+			u8 bData);
 int32_t EepromReadByte(struct et131x_adapter *adapter, u32 unAddress,
-		       u8 *pbData, u32 unEepromId,
-		       u32 unAddressingMode);
+			u8 *pbData);
 
 #endif /* _ET1310_EEPROM_H_ */

deleted file mode 100644
index e69de29..0000000

index a719e90..bea9918 100644
@@ -337,8 +337,7 @@ int et131x_find_adapter(struct et131x_adapter *adapter, struct pci_dev *pdev)
 			 * corruption seen with 1310 B Silicon
 			 */
 			for (nLoop = 0; nLoop < 3; nLoop++) {
-				EepromWriteByte(adapter, nLoop, temp[nLoop],
-						0, SINGLE_BYTE);
+				EepromWriteByte(adapter, nLoop, temp[nLoop]);
 			}
 		}
 

@@ -364,8 +363,8 @@ int et131x_find_adapter(struct et131x_adapter *adapter, struct pci_dev *pdev)
 	/* Read the EEPROM for information regarding LED behavior. Refer to
 	 * ET1310_phy.c, et131x_xcvr_init(), for its use.
 	 */
-	EepromReadByte(adapter, 0x70, &adapter->eepromData[0], 0, SINGLE_BYTE);
-	EepromReadByte(adapter, 0x71, &adapter->eepromData[1], 0, SINGLE_BYTE);
+	EepromReadByte(adapter, 0x70, &adapter->eepromData[0]);
+	EepromReadByte(adapter, 0x71, &adapter->eepromData[1]);
 
 	if (adapter->eepromData[0] != 0xcd)
 		/* Disable all optional features */

index 388ac40..d2ac26c 100644
@@ -2267,30 +2267,14 @@ typedef struct _MAC_STAT_t {		/* Location: */
  * structure for Main Memory Controller Control reg in mmc address map.
  * located at address 0x7000
  */
-typedef union _MMC_CTRL_t {
-	u32 value;
-	struct {
-#ifdef _BIT_FIELDS_HTOL
-		u32 reserved:25;		/* bits 7-31 */
-		u32 force_ce:1;		/* bit 6 */
-		u32 rxdma_disable:1;	/* bit 5 */
-		u32 txdma_disable:1;	/* bit 4 */
-		u32 txmac_disable:1;	/* bit 3 */
-		u32 rxmac_disable:1;	/* bit 2 */
-		u32 arb_disable:1;		/* bit 1 */
-		u32 mmc_enable:1;		/* bit 0 */
-#else
-		u32 mmc_enable:1;		/* bit 0 */
-		u32 arb_disable:1;		/* bit 1 */
-		u32 rxmac_disable:1;	/* bit 2 */
-		u32 txmac_disable:1;	/* bit 3 */
-		u32 txdma_disable:1;	/* bit 4 */
-		u32 rxdma_disable:1;	/* bit 5 */
-		u32 force_ce:1;		/* bit 6 */
-		u32 reserved:25;		/* bits 7-31 */
-#endif
-	} bits;
-} MMC_CTRL_t, *PMMC_CTRL_t;
+ 
+#define ET_MMC_ENABLE		1
+#define ET_MMC_ARB_DISABLE	2
+#define ET_MMC_RXMAC_DISABLE	4
+#define ET_MMC_TXMAC_DISABLE	8
+#define ET_MMC_TXDMA_DISABLE	16
+#define ET_MMC_RXDMA_DISABLE	32
+#define ET_MMC_FORCE_CE		64
 
 /*
  * structure for Main Memory Controller Host Memory Access Address reg in mmc

@@ -2329,7 +2313,7 @@ typedef union _MMC_SRAM_ACCESS_t {
  * Memory Control Module of JAGCore Address Mapping
  */
 typedef struct _MMC_t {			/* Location: */
-	MMC_CTRL_t mmc_ctrl;		/*  0x7000 */
+	u32 mmc_ctrl;		/*  0x7000 */
 	MMC_SRAM_ACCESS_t sram_access;	/*  0x7004 */
 	u32 sram_word1;		/*  0x7008 */
 	u32 sram_word2;		/*  0x700C */

index 5c847ad..2767e4d 100644
@@ -175,21 +175,9 @@ void ConfigGlobalRegs(struct et131x_adapter *etdev)
  */
 void ConfigMMCRegs(struct et131x_adapter *etdev)
 {
-	MMC_CTRL_t mmc_ctrl = { 0 };
-
 	DBG_ENTER(et131x_dbginfo);
-
 	/* All we need to do is initialize the Memory Control Register */
-	mmc_ctrl.bits.force_ce = 0x0;
-	mmc_ctrl.bits.rxdma_disable = 0x0;
-	mmc_ctrl.bits.txdma_disable = 0x0;
-	mmc_ctrl.bits.txmac_disable = 0x0;
-	mmc_ctrl.bits.rxmac_disable = 0x0;
-	mmc_ctrl.bits.arb_disable = 0x0;
-	mmc_ctrl.bits.mmc_enable = 0x1;
-
-	writel(mmc_ctrl.value, &etdev->regs->mmc.mmc_ctrl.value);
-
+	writel(ET_MMC_ENABLE, &etdev->regs->mmc.mmc_ctrl);
 	DBG_LEAVE(et131x_dbginfo);
 }
 

index d2ac26c..01c990c 100644
@@ -2264,7 +2264,7 @@ typedef struct _MAC_STAT_t {		/* Location: */
 /* START OF MMC REGISTER ADDRESS MAP */
 
 /*
- * structure for Main Memory Controller Control reg in mmc address map.
+ * Main Memory Controller Control reg in mmc address map.
  * located at address 0x7000
  */
  

@@ -2277,31 +2277,13 @@ typedef struct _MAC_STAT_t {		/* Location: */
 #define ET_MMC_FORCE_CE		64
 
 /*
- * structure for Main Memory Controller Host Memory Access Address reg in mmc
- * address map.  Located at address 0x7004
+ * Main Memory Controller Host Memory Access Address reg in mmc
+ * address map.  Located at address 0x7004. Top 16 bits hold the address bits
  */
-typedef union _MMC_SRAM_ACCESS_t {
-	u32 value;
-	struct {
-#ifdef _BIT_FIELDS_HTOL
-		u32 byte_enable:16;	/* bits 16-31 */
-		u32 reserved2:2;		/* bits 14-15 */
-		u32 req_addr:10;		/* bits 4-13 */
-		u32 reserved1:1;		/* bit 3 */
-		u32 is_ctrl_word:1;	/* bit 2 */
-		u32 wr_access:1;		/* bit 1 */
-		u32 req_access:1;		/* bit 0 */
-#else
-		u32 req_access:1;		/* bit 0 */
-		u32 wr_access:1;		/* bit 1 */
-		u32 is_ctrl_word:1;	/* bit 2 */
-		u32 reserved1:1;		/* bit 3 */
-		u32 req_addr:10;		/* bits 4-13 */
-		u32 reserved2:2;		/* bits 14-15 */
-		u32 byte_enable:16;	/* bits 16-31 */
-#endif
-	} bits;
-} MMC_SRAM_ACCESS_t, *PMMC_SRAM_ACCESS_t;
+
+#define ET_SRAM_REQ_ACCESS	1
+#define ET_SRAM_WR_ACCESS	2
+#define ET_SRAM_IS_CTRL		4
 
 /*
  * structure for Main Memory Controller Host Memory Access Data reg in mmc

@@ -2314,7 +2296,7 @@ typedef union _MMC_SRAM_ACCESS_t {
  */
 typedef struct _MMC_t {			/* Location: */
 	u32 mmc_ctrl;		/*  0x7000 */
-	MMC_SRAM_ACCESS_t sram_access;	/*  0x7004 */
+	u32 sram_access;	/*  0x7004 */
 	u32 sram_word1;		/*  0x7008 */
 	u32 sram_word2;		/*  0x700C */
 	u32 sram_word3;		/*  0x7010 */

index 4346c82..61203c1 100644
@@ -115,18 +115,16 @@ void DumpTxQueueContents(int dbgLvl, struct et131x_adapter *etdev)
 
 	if (DBG_FLAGS(et131x_dbginfo) & dbgLvl) {
 		for (TxQueueAddr = 0x200; TxQueueAddr < 0x3ff; TxQueueAddr++) {
-			MMC_SRAM_ACCESS_t sram_access;
-
-			sram_access.value = readl(&mmc->sram_access.value);
-			sram_access.bits.req_addr = TxQueueAddr;
-			sram_access.bits.req_access = 1;
-			writel(sram_access.value, &mmc->sram_access.value);
+			u32 sram_access = readl(&mmc->sram_access);
+			sram_access &= 0xFFFF;
+			sram_access |= (TxQueueAddr << 16) | ET_SRAM_REQ_ACCESS;
+			writel(sram_access, &mmc->sram_access);
 
 			DBG_PRINT("Addr 0x%x, Access 0x%08x\t"
 				  "Value 1 0x%08x, Value 2 0x%08x, "
 				  "Value 3 0x%08x, Value 4 0x%08x, \n",
 				  TxQueueAddr,
-				  readl(&mmc->sram_access.value),
+				  readl(&mmc->sram_access),
 				  readl(&mmc->sram_word1),
 				  readl(&mmc->sram_word2),
 				  readl(&mmc->sram_word3),

index 61203c1..779130b 100644
@@ -1,4 +1,3 @@
-/*
  * Agere Systems Inc.
  * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
  *

@@ -108,22 +107,22 @@ extern dbg_info_t *et131x_dbginfo;
  * DumpTxQueueContents - Dump out the tx queue and the shadow pointers
  * @etdev: pointer to our adapter structure
  */
-void DumpTxQueueContents(int dbgLvl, struct et131x_adapter *etdev)
+void DumpTxQueueContents(int debug, struct et131x_adapter *etdev)
 {
 	MMC_t __iomem *mmc = &etdev->regs->mmc;
-	uint32_t TxQueueAddr;
+	u32 txq_addr;
 
-	if (DBG_FLAGS(et131x_dbginfo) & dbgLvl) {
-		for (TxQueueAddr = 0x200; TxQueueAddr < 0x3ff; TxQueueAddr++) {
+	if (DBG_FLAGS(et131x_dbginfo) & debug) {
+		for (txq_addr = 0x200; txq_addr < 0x3ff; txq_addr++) {
 			u32 sram_access = readl(&mmc->sram_access);
 			sram_access &= 0xFFFF;
-			sram_access |= (TxQueueAddr << 16) | ET_SRAM_REQ_ACCESS;
+			sram_access |= (txq_addr << 16) | ET_SRAM_REQ_ACCESS;
 			writel(sram_access, &mmc->sram_access);
 
 			DBG_PRINT("Addr 0x%x, Access 0x%08x\t"
 				  "Value 1 0x%08x, Value 2 0x%08x, "
 				  "Value 3 0x%08x, Value 4 0x%08x, \n",
-				  TxQueueAddr,
+				  txq_addr,
 				  readl(&mmc->sram_access),
 				  readl(&mmc->sram_word1),
 				  readl(&mmc->sram_word2),

@@ -136,6 +135,12 @@ void DumpTxQueueContents(int dbgLvl, struct et131x_adapter *etdev)
 	}
 }
 
+static const char *BlockNames[NUM_BLOCKS] = {
+	"Global", "Tx DMA", "Rx DMA", "Tx MAC",
+	"Rx MAC", "MAC", "MAC Stat", "MMC"
+};
+
+
 /**
  * DumpDeviceBlock
  * @etdev: pointer to our adapter

@@ -144,30 +149,23 @@ void DumpTxQueueContents(int dbgLvl, struct et131x_adapter *etdev)
  * mapped to a new page, each page is 4096 bytes).
  */
 #define NUM_BLOCKS 8
-void DumpDeviceBlock(int dbgLvl, struct et131x_adapter *etdev,
-		     uint32_t Block)
+void DumpDeviceBlock(int debug, struct et131x_adapter *etdev,
+		     u32 block)
 {
-	uint32_t Address1, Address2;
-	uint32_t __iomem *BigDevicePointer =
-		(uint32_t __iomem *) etdev->regs;
-	const char *BlockNames[NUM_BLOCKS] = {
-		"Global", "Tx DMA", "Rx DMA", "Tx MAC",
-		"Rx MAC", "MAC", "MAC Stat", "MMC"
-	};
+	u32 addr1, addr2;
+	u32 __iomem *regs = (u32 __iomem *) etdev->regs;
 
 	/* Output the debug counters to the debug terminal */
-	if (DBG_FLAGS(et131x_dbginfo) & dbgLvl) {
-		DBG_PRINT("%s block\n", BlockNames[Block]);
-		BigDevicePointer += Block * 1024;
-		for (Address1 = 0; Address1 < 8; Address1++) {
-			for (Address2 = 0; Address2 < 8; Address2++) {
-				if (Block == 0 &&
-				    (Address1 * 8 + Address2) == 6) {
+	if (DBG_FLAGS(et131x_dbginfo) & debug) {
+		DBG_PRINT("%s block\n", BlockNames[block]);
+		regs += block * 1024;
+		for (addr1 = 0; addr1 < 8; addr1++) {
+			for (addr2 = 0; addr2 < 8; addr2++) {
+				if (block == 0 &&
+				    (addr1 * 8 + addr2) == 6)
 					DBG_PRINT("  ISR    , ");
-				} else {
-					DBG_PRINT("0x%08x, ",
-						  readl(BigDevicePointer++));
-				}
+				else
+					DBG_PRINT("0x%08x, ", readl(regs++));
 			}
 			DBG_PRINT("\n");
 		}

@@ -182,29 +180,22 @@ void DumpDeviceBlock(int dbgLvl, struct et131x_adapter *etdev,
  * Dumps the first 64 regs of each block of the et-1310 (each block is
  * mapped to a new page, each page is 4096 bytes).
  */
-void DumpDeviceReg(int dbgLvl, struct et131x_adapter *etdev)
+void DumpDeviceReg(int debug, struct et131x_adapter *etdev)
 {
-	uint32_t Address1, Address2;
-	uint32_t Block;
-	uint32_t __iomem *BigDevicePointer =
-		(uint32_t __iomem *) etdev->regs;
-	uint32_t __iomem *Pointer;
-	const char *BlockNames[NUM_BLOCKS] = {
-		"Global", "Tx DMA", "Rx DMA", "Tx MAC",
-		"Rx MAC", "MAC", "MAC Stat", "MMC"
-	};
+	u32 addr1, addr2;
+	u32 block;
+	u32 __iomem *regs = (u32 __iomem *)etdev->regs;
+	u32 __iomem *p;
 
 	/* Output the debug counters to the debug terminal */
-	if (DBG_FLAGS(et131x_dbginfo) & dbgLvl) {
-		for (Block = 0; Block < NUM_BLOCKS; Block++) {
-			DBG_PRINT("%s block\n", BlockNames[Block]);
-			Pointer = BigDevicePointer + (Block * 1024);
-
-			for (Address1 = 0; Address1 < 8; Address1++) {
-				for (Address2 = 0; Address2 < 8; Address2++) {
-					DBG_PRINT("0x%08x, ",
-						  readl(Pointer++));
-				}
+	if (DBG_FLAGS(et131x_dbginfo) & debug) {
+		for (block = 0; block < NUM_BLOCKS; block++) {
+			DBG_PRINT("%s block\n", BlockNames[block]);
+			p = regs + block * 1024;
+
+			for (addr1 = 0; addr1 < 8; addr1++) {
+				for (addr2 = 0; addr2 < 8; addr2++)
+					DBG_PRINT("0x%08x, ", readl(p++));
 				DBG_PRINT("\n");
 			}
 			DBG_PRINT("\n");

index 01c990c..7f6baa3 100644
@@ -61,41 +61,13 @@
 
 /* START OF GLOBAL REGISTER ADDRESS MAP */
 
-typedef union _Q_ADDR_t {
-	u32 value;
-	struct {
-#ifdef _BIT_FIELDS_HTOL
-		u32 unused:22;	/* bits 10-31 */
-		u32 addr:10;	/* bits 0-9 */
-#else
-		u32 addr:10;	/* bits 0-9 */
-		u32 unused:22;	/* bits 10-31 */
-#endif
-	} bits;
-} Q_ADDR_t, *PQ_ADDR_t;
-
 /*
- * structure for tx queue start address reg in global address map
- * located at address 0x0000
- * Defined earlier (Q_ADDR_t)
- */
-
-/*
- * structure for tx queue end address reg in global address map
- * located at address 0x0004
- * Defined earlier (Q_ADDR_t)
- */
-
-/*
- * structure for rx queue start address reg in global address map
- * located at address 0x0008
- * Defined earlier (Q_ADDR_t)
- */
-
-/*
- * structure for rx queue end address reg in global address map
- * located at address 0x000C
- * Defined earlier (Q_ADDR_t)
+ * 10bit registers
+ *
+ * Tx queue start address reg in global address map at address 0x0000
+ * tx queue end address reg in global address map at address 0x0004
+ * rx queue start address reg in global address map at address 0x0008
+ * rx queue end address reg in global address map at address 0x000C
  */
 
 /*

@@ -295,10 +267,10 @@ typedef union _LOOPBACK_t {
  * Located at address 0x0000
  */
 typedef struct _GLOBAL_t {			/* Location: */
-	Q_ADDR_t txq_start_addr;		/*  0x0000 */
-	Q_ADDR_t txq_end_addr;			/*  0x0004 */
-	Q_ADDR_t rxq_start_addr;		/*  0x0008 */
-	Q_ADDR_t rxq_end_addr;			/*  0x000C */
+	u32 txq_start_addr;			/*  0x0000 */
+	u32 txq_end_addr;			/*  0x0004 */
+	u32 rxq_start_addr;			/*  0x0008 */
+	u32 rxq_end_addr;			/*  0x000C */
 	PM_CSR_t pm_csr;			/*  0x0010 */
 	u32 unused;				/*  0x0014 */
 	INTERRUPT_t int_status;			/*  0x0018 */

63 lines not on this page · raw message

index 779130b..945b4b5 100644
@@ -1,3 +1,4 @@
+/*
  * Agere Systems Inc.
  * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
  *

@@ -135,6 +136,8 @@ void DumpTxQueueContents(int debug, struct et131x_adapter *etdev)
 	}
 }
 
+#define NUM_BLOCKS 8
+
 static const char *BlockNames[NUM_BLOCKS] = {
 	"Global", "Tx DMA", "Rx DMA", "Tx MAC",
 	"Rx MAC", "MAC", "MAC Stat", "MMC"

@@ -148,7 +151,6 @@ static const char *BlockNames[NUM_BLOCKS] = {
  * Dumps the first 64 regs of each block of the et-1310 (each block is
  * mapped to a new page, each page is 4096 bytes).
  */
-#define NUM_BLOCKS 8
 void DumpDeviceBlock(int debug, struct et131x_adapter *etdev,
 		     u32 block)
 {

index 7f6baa3..f4867f5 100644
@@ -73,37 +73,20 @@
 /*
  * structure for power management control status reg in global address map
  * located at address 0x0010
+ *	jagcore_rx_rdy	bit 9
+ *	jagcore_tx_rdy	bit 8
+ *	phy_lped_en	bit 7
+ *	phy_sw_coma	bit 6
+ *	rxclk_gate	bit 5
+ *	txclk_gate	bit 4
+ *	sysclk_gate	bit 3
+ *	jagcore_rx_en	bit 2
+ *	jagcore_tx_en	bit 1
+ *	gigephy_en	bit 0
  */
-typedef union _PM_CSR_t {
-	u32 value;
-	struct {
-#ifdef _BIT_FIELDS_HTOL
-		u32 unused:22;		/* bits 10-31 */
-		u32 pm_jagcore_rx_rdy:1;	/* bit 9 */
-		u32 pm_jagcore_tx_rdy:1;	/* bit 8 */
-		u32 pm_phy_lped_en:1;	/* bit 7 */
-		u32 pm_phy_sw_coma:1;	/* bit 6 */
-		u32 pm_rxclk_gate:1;	/* bit 5 */
-		u32 pm_txclk_gate:1;	/* bit 4 */
-		u32 pm_sysclk_gate:1;	/* bit 3 */
-		u32 pm_jagcore_rx_en:1;	/* bit 2 */
-		u32 pm_jagcore_tx_en:1;	/* bit 1 */
-		u32 pm_gigephy_en:1;	/* bit 0 */
-#else
-		u32 pm_gigephy_en:1;	/* bit 0 */
-		u32 pm_jagcore_tx_en:1;	/* bit 1 */
-		u32 pm_jagcore_rx_en:1;	/* bit 2 */
-		u32 pm_sysclk_gate:1;	/* bit 3 */
-		u32 pm_txclk_gate:1;	/* bit 4 */
-		u32 pm_rxclk_gate:1;	/* bit 5 */
-		u32 pm_phy_sw_coma:1;	/* bit 6 */
-		u32 pm_phy_lped_en:1;	/* bit 7 */
-		u32 pm_jagcore_tx_rdy:1;	/* bit 8 */
-		u32 pm_jagcore_rx_rdy:1;	/* bit 9 */
-		u32 unused:22;		/* bits 10-31 */
-#endif
-	} bits;
-} PM_CSR_t, *PPM_CSR_t;
+
+#define ET_PM_PHY_SW_COMA		0x40
+#define ET_PMCSR_INIT			0x38
 
 /*
  * structure for interrupt status reg in global address map

@@ -271,7 +254,7 @@ typedef struct _GLOBAL_t {			/* Location: */
 	u32 txq_end_addr;			/*  0x0004 */
 	u32 rxq_start_addr;			/*  0x0008 */
 	u32 rxq_end_addr;			/*  0x000C */
-	PM_CSR_t pm_csr;			/*  0x0010 */
+	u32 pm_csr;				/*  0x0010 */
 	u32 unused;				/*  0x0014 */
 	INTERRUPT_t int_status;			/*  0x0018 */
 	INTERRUPT_t int_mask;			/*  0x001C */

index b2123d0..a27d815 100644
@@ -672,7 +672,7 @@ void SetupDeviceForMulticast(struct et131x_adapter *etdev)
 	uint32_t hash2 = 0;
 	uint32_t hash3 = 0;
 	uint32_t hash4 = 0;
-	PM_CSR_t pm_csr;
+	u32 pm_csr;
 
 	DBG_ENTER(et131x_dbginfo);
 

@@ -718,8 +718,8 @@ void SetupDeviceForMulticast(struct et131x_adapter *etdev)
 	}
 
 	/* Write out the new hash to the device */
-	pm_csr.value = readl(&etdev->regs->global.pm_csr.value);
-	if (pm_csr.bits.pm_phy_sw_coma == 0) {
+	pm_csr = readl(&etdev->regs->global.pm_csr);
+	if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) {
 		writel(hash1, &rxmac->multi_hash1);
 		writel(hash2, &rxmac->multi_hash2);
 		writel(hash3, &rxmac->multi_hash3);

@@ -735,7 +735,7 @@ void SetupDeviceForUnicast(struct et131x_adapter *etdev)
 	RXMAC_UNI_PF_ADDR1_t uni_pf1;
 	RXMAC_UNI_PF_ADDR2_t uni_pf2;
 	RXMAC_UNI_PF_ADDR3_t uni_pf3;
-	PM_CSR_t pm_csr;
+	u32 pm_csr;
 
 	DBG_ENTER(et131x_dbginfo);
 

@@ -763,8 +763,8 @@ void SetupDeviceForUnicast(struct et131x_adapter *etdev)
 	uni_pf1.bits.addr1_5 = etdev->CurrentAddress[4];
 	uni_pf1.bits.addr1_6 = etdev->CurrentAddress[5];
 
-	pm_csr.value = readl(&etdev->regs->global.pm_csr.value);
-	if (pm_csr.bits.pm_phy_sw_coma == 0) {
+	pm_csr = readl(&etdev->regs->global.pm_csr);
+	if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) {
 		writel(uni_pf1.value, &rxmac->uni_pf_addr1.value);
 		writel(uni_pf2.value, &rxmac->uni_pf_addr2.value);
 		writel(uni_pf3.value, &rxmac->uni_pf_addr3.value);

index 846c80b..ea186a8 100644
@@ -120,12 +120,11 @@ extern dbg_info_t *et131x_dbginfo;
 void EnablePhyComa(struct et131x_adapter *etdev)
 {
 	unsigned long flags;
-	PM_CSR_t GlobalPmCSR;
-	int32_t LoopCounter = 10;
+	u32 GlobalPmCSR;
 
 	DBG_ENTER(et131x_dbginfo);
 
-	GlobalPmCSR.value = readl(&etdev->regs->global.pm_csr.value);
+	GlobalPmCSR = readl(&etdev->regs->global.pm_csr);
 
 	/* Save the GbE PHY speed and duplex modes. Need to restore this
 	 * when cable is plugged back in

@@ -141,14 +140,12 @@ void EnablePhyComa(struct et131x_adapter *etdev)
 	/* Wait for outstanding Receive packets */
 
 	/* Gate off JAGCore 3 clock domains */
-	GlobalPmCSR.bits.pm_sysclk_gate = 0;
-	GlobalPmCSR.bits.pm_txclk_gate = 0;
-	GlobalPmCSR.bits.pm_rxclk_gate = 0;
-	writel(GlobalPmCSR.value, &etdev->regs->global.pm_csr.value);
+	GlobalPmCSR &= ~ET_PMCSR_INIT;
+	writel(GlobalPmCSR, &etdev->regs->global.pm_csr);
 
 	/* Program gigE PHY in to Coma mode */
-	GlobalPmCSR.bits.pm_phy_sw_coma = 1;
-	writel(GlobalPmCSR.value, &etdev->regs->global.pm_csr.value);
+	GlobalPmCSR |= ET_PM_PHY_SW_COMA;
+	writel(GlobalPmCSR, &etdev->regs->global.pm_csr);
 
 	DBG_LEAVE(et131x_dbginfo);
 }

@@ -159,18 +156,16 @@ void EnablePhyComa(struct et131x_adapter *etdev)
  */
 void DisablePhyComa(struct et131x_adapter *etdev)
 {
-	PM_CSR_t GlobalPmCSR;
+	u32 GlobalPmCSR;
 
 	DBG_ENTER(et131x_dbginfo);
 
-	GlobalPmCSR.value = readl(&etdev->regs->global.pm_csr.value);
+	GlobalPmCSR = readl(&etdev->regs->global.pm_csr);
 
 	/* Disable phy_sw_coma register and re-enable JAGCore clocks */
-	GlobalPmCSR.bits.pm_sysclk_gate = 1;
-	GlobalPmCSR.bits.pm_txclk_gate = 1;
-	GlobalPmCSR.bits.pm_rxclk_gate = 1;
-	GlobalPmCSR.bits.pm_phy_sw_coma = 0;
-	writel(GlobalPmCSR.value, &etdev->regs->global.pm_csr.value);
+	GlobalPmCSR |= ET_PMCSR_INIT;
+	GlobalPmCSR &= ~ET_PM_PHY_SW_COMA;
+	writel(GlobalPmCSR, &etdev->regs->global.pm_csr);
 
 	/* Restore the GbE PHY speed and duplex modes;
 	 * Reset JAGCore; re-configure and initialize JAGCore and gigE PHY

index bea9918..d7a1b34 100644
@@ -474,16 +474,16 @@ int et131x_find_adapter(struct et131x_adapter *adapter, struct pci_dev *pdev)
 void et131x_error_timer_handler(unsigned long data)
 {
 	struct et131x_adapter *etdev = (struct et131x_adapter *) data;
-	PM_CSR_t pm_csr;
+	u32 pm_csr;
 
-	pm_csr.value = readl(&etdev->regs->global.pm_csr.value);
+	pm_csr = readl(&etdev->regs->global.pm_csr);
 
-	if (pm_csr.bits.pm_phy_sw_coma == 0)
+	if ((pm_csr & ET_PM_PHY_SW_COMA) == 0)
 		UpdateMacStatHostCounters(etdev);
 	else
 		DBG_VERBOSE(et131x_dbginfo,
 			    "No interrupts, in PHY coma, pm_csr = 0x%x\n",
-			    pm_csr.value);
+			    pm_csr);
 
 	if (!etdev->Bmsr.bits.link_status &&
 	    etdev->RegistryPhyComa &&

@@ -494,7 +494,7 @@ void et131x_error_timer_handler(unsigned long data)
 	if (etdev->PoMgmt.TransPhyComaModeOnBoot == 10) {
 		if (!etdev->Bmsr.bits.link_status
 		    && etdev->RegistryPhyComa) {
-			if (pm_csr.bits.pm_phy_sw_coma == 0) {
+			if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) {
 				/* NOTE - This was originally a 'sync with
 				 *  interrupt'. How to do that under Linux?
 				 */

@@ -1002,15 +1002,7 @@ int __devinit et131x_pci_setup(struct pci_dev *pdev,
 	/* Perform device-specific initialization here (See code below) */
 
 	/* If Phy COMA mode was enabled when we went down, disable it here. */
-	{
-		PM_CSR_t GlobalPmCSR = { 0 };
-
-		GlobalPmCSR.bits.pm_sysclk_gate = 1;
-		GlobalPmCSR.bits.pm_txclk_gate = 1;
-		GlobalPmCSR.bits.pm_rxclk_gate = 1;
-		writel(GlobalPmCSR.value,
-		       &adapter->regs->global.pm_csr.value);
-	}
+	writel(ET_PMCSR_INIT,  &adapter->regs->global.pm_csr);
 
 	/* Issue a global reset to the et1310 */
 	DBG_TRACE(et131x_dbginfo, "Issuing soft reset...\n");

index 478569f..00b815a 100644
@@ -274,14 +274,13 @@ void et131x_isr_handler(struct work_struct *work)
 			 */
 			if (etdev->FlowControl == TxOnly ||
 			    etdev->FlowControl == Both) {
-				PM_CSR_t pm_csr;
+				u32 pm_csr;
 
 				/* Tell the device to send a pause packet via
 				 * the back pressure register
 				 */
-				pm_csr.value =
-					readl(&iomem->global.pm_csr.value);
-				if (pm_csr.bits.pm_phy_sw_coma == 0) {
+				pm_csr = readl(&iomem->global.pm_csr);
+				if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) {
 					TXMAC_BP_CTRL_t bp_ctrl = { 0 };
 
 					bp_ctrl.bits.bp_req = 1;

@@ -351,7 +350,7 @@ void et131x_isr_handler(struct work_struct *work)
 
 		/* Handle the PHY interrupt */
 		if (GlobStatus.bits.phy_interrupt) {
-			PM_CSR_t pm_csr;
+			u32 pm_csr;
 			MI_BMSR_t BmsrInts, BmsrData;
 			MI_ISR_t myIsr;
 

@@ -360,8 +359,8 @@ void et131x_isr_handler(struct work_struct *work)
 			/* If we are in coma mode when we get this interrupt,
 			 * we need to disable it.
 			 */
-			pm_csr.value = readl(&iomem->global.pm_csr.value);
-			if (pm_csr.bits.pm_phy_sw_coma == 1) {
+			pm_csr = readl(&iomem->global.pm_csr);
+			if (pm_csr & ET_PM_PHY_SW_COMA) {
 				/*
 				 * Check to see if we are in coma mode and if
 				 * so, disable it because we will not be able

index f4867f5..7d1bdc8 100644
@@ -329,94 +329,40 @@ typedef union _TXDMA_PR_NUM_DES_t {
 } TXDMA_PR_NUM_DES_t, *PTXDMA_PR_NUM_DES_t;
 
 
-typedef union _DMA10W_t {
-	u32 value;
-	struct {
-#ifdef _BIT_FIELDS_HTOL
-		u32 unused:21;	/* bits 11-31 */
-		u32 wrap:1;	/* bit 10 */
-		u32 val:10;	/* bits 0-9 */
-#else
-		u32 val:10;	/* bits 0-9 */
-		u32 wrap:1;	/* bit 10 */
-		u32 unused:21;	/* bits 11-31 */
-#endif
-	} bits;
-} DMA10W_t, *PDMA10W_t;
-
-/*
- * structure for txdma tx queue write address reg in txdma address map
- * located at address 0x1010
- * Defined earlier (DMA10W_t)
- */
-
-/*
- * structure for txdma tx queue write address external reg in txdma address map
- * located at address 0x1014
- * Defined earlier (DMA10W_t)
- */
-
-/*
- * structure for txdma tx queue read address reg in txdma address map
- * located at address 0x1018
- * Defined earlier (DMA10W_t)
- */
-
-/*
- * structure for txdma status writeback address hi reg in txdma address map
- * located at address 0x101C
- * Defined earlier (u32)
- */
-
-/*
- * structure for txdma status writeback address lo reg in txdma address map
- * located at address 0x1020
- * Defined earlier (u32)
- */
-
-/*
- * structure for txdma service request reg in txdma address map
- * located at address 0x1024
- * Defined earlier (DMA10W_t)
- */
+#define ET_DMA10_MASK		0x3FF	/* 10 bit mask for DMA10W types */
+#define ET_DMA10_WRAP		0x400
+#define ET_DMA4_MASK		0x00F	/* 4 bit mask for DMA4W types */
+#define ET_DMA4_WRAP		0x010
 
-/*
- * structure for txdma service complete reg in txdma address map
- * located at address 0x1028
- * Defined earlier (DMA10W_t)
- */
+#define INDEX10(x)	((x) & ET_DMA10_MASK)
+#define INDEX4(x)	((x) & ET_DMA4_MASK)
 
-typedef union _DMA4W_t {
-	u32 value;
-	struct {
-#ifdef _BIT_FIELDS_HTOL
-		u32 unused:27;	/* bits 5-31 */
-		u32 wrap:1;	/* bit 4 */
-		u32 val:4;		/* bit 0-3 */
-#else
-		u32 val:4;		/* bits 0-3 */
-		u32 wrap:1;	/* bit 4 */
-		u32 unused:27;	/* bits 5-31 */
-#endif
-	} bits;
-} DMA4W_t, *PDMA4W_t;
+extern inline void add_10bit(u32 *v, int n)
+{
+	*v = INDEX10(*v + n);
+}
 
 /*
- * structure for txdma tx descriptor cache read index reg in txdma address map
- * located at address 0x102C
- * Defined earlier (DMA4W_t)
- */
-
-/*
- * structure for txdma tx descriptor cache write index reg in txdma address map
- * located at address 0x1030
- * Defined earlier (DMA4W_t)
+ * 10bit DMA with wrap
+ * txdma tx queue write address reg in txdma address map at 0x1010
+ * txdma tx queue write address external reg in txdma address map at 0x1014
+ * txdma tx queue read address reg in txdma address map at 0x1018
+ *
+ * u32
+ * txdma status writeback address hi reg in txdma address map at0x101C
+ * txdma status writeback address lo reg in txdma address map at 0x1020
+ *
+ * 10bit DMA with wrap
+ * txdma service request reg in txdma address map at 0x1024
+ * structure for txdma service complete reg in txdma address map at 0x1028
+ *
+ * 4bit DMA with wrap
+ * txdma tx descriptor cache read index reg in txdma address map at 0x102C
+ * txdma tx descriptor cache write index reg in txdma address map at 0x1030
+ *
+ * txdma error reg in txdma address map at address 0x1034
  */
 
-/*
- * structure for txdma error reg in txdma address map
- * located at address 0x1034
- */
 typedef union _TXDMA_ERROR_t {
 	u32 value;
 	struct {