2.6.33-rc3-git3: Reported regressions from 2.6.32

1/1

2010-01-10       55       33          21
  2009-12-29       36       34          27
		  http://marc.info/?l=linux-kernel&m=126160893126548&w=4
		  http://marc.info/?l=linux-kernel&m=126114565103300&w=4
		  http://marc.info/?l=linux-kbuild&m=126202819526623&w=2
		  http://patchwork.kernel.org/patch/71957/
		  http://patchwork.kernel.org/patch/67257/
@@ -419,7 +419,7 @@
 
 static const struct driver_info        cdc_info = {
        .description =  "CDC Ethernet Device",
-       .flags =        FLAG_ETHER | FLAG_LINK_INTR,
+       .flags =        FLAG_ETHER,
        // .check_connect = cdc_check_connect,
        .bind =         cdc_bind,
        .unbind =       usbnet_cdc_unbind,

Ben Hutchings
The generation of random numbers is too important to be left to chance.
                                                            - Robert Coveyou
@@ -419,7 +419,7 @@
 
 static const struct driver_info        cdc_info = {
        .description =  "CDC Ethernet Device",
-       .flags =        FLAG_ETHER | FLAG_LINK_INTR,
+       .flags =        FLAG_ETHER,
        // .check_connect = cdc_check_connect,
        .bind =         cdc_bind,
        .unbind =       usbnet_cdc_unbind,

--- END ---

@@ -419,7 +419,7 @@
 
 static const struct driver_info	cdc_info = {
 	.description =	"CDC Ethernet Device",
-	.flags =	FLAG_ETHER | FLAG_LINK_INTR,
+	.flags =	FLAG_ETHER,
 	// .check_connect = cdc_check_connect,
 	.bind =		cdc_bind,
 	.unbind =	usbnet_cdc_unbind,

Ben Hutchings
The generation of random numbers is too important to be left to chance.
                                                            - Robert Coveyou
		  http://marc.info/?l=linux-kernel&m=126114565103300&w=4
		  http://marc.info/?l=linux-kbuild&m=126202819526623&w=2
		  http://patchwork.kernel.org/patch/71957/
		  http://marc.info/?l=linux-kernel&m=126114565103300&w=4
		  http://marc.info/?l=linux-kbuild&m=126202819526623&w=2
		  http://patchwork.kernel.org/patch/71957/
		  http://marc.info/?l=linux-kernel&m=126114565103300&w=4
		  http://marc.info/?l=linux-kbuild&m=126202819526623&w=2
		  http://patchwork.kernel.org/patch/71957/
		  http://marc.info/?l=linux-kernel&m=126114565103300&w=4
		  http://marc.info/?l=linux-kbuild&m=126202819526623&w=2
		  http://patchwork.kernel.org/patch/71957/
		  http://marc.info/?l=linux-kernel&m=126114565103300&w=4
		  http://marc.info/?l=linux-kbuild&m=126202819526623&w=2
		  http://patchwork.kernel.org/patch/71957/
		  http://marc.info/?l=linux-kernel&m=126114565103300&w=4
		  http://marc.info/?l=linux-kbuild&m=126202819526623&w=2
		  http://patchwork.kernel.org/patch/71957/
		  http://marc.info/?l=linux-kernel&m=126114565103300&w=4
		  http://marc.info/?l=linux-kbuild&m=126202819526623&w=2
		  http://patchwork.kernel.org/patch/71957/
		  http://patchwork.kernel.org/patch/67257/
		  http://patchwork.kernel.org/patch/67257/
		  http://patchwork.kernel.org/patch/67257/
		  http://marc.info/?l=linux-kernel&m=126160893126548&w=4
		  http://marc.info/?l=linux-kernel&m=126160893126548&w=4
 drivers/net/sky2.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)
index 1c01b96..7650f73 100644
@@ -1844,7 +1844,8 @@ static void sky2_tx_complete(struct sky2_port

		  http://marc.info/?l=linux-kernel&m=126160893126548&w=4
 drivers/net/sky2.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)
index 1c01b96..7650f73 100644
@@ -1844,7 +1844,8 @@ static void sky2_tx_complete(struct sky2_port
 *sky2, u16 done)
 	sky2->tx_cons = idx;
 	smp_mb();
 
-	if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
+	/* Wake unless it's detached, and called e.g. from sky2_down() */
+	if (tx_avail(sky2) > MAX_SKB_TX_LE + 4 && netif_device_present(dev))
 		netif_wake_queue(dev);
 }

 drivers/net/sky2.c |    3 ++-
---
 drivers/net/sky2.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)
index 93d9635..6d9111d 100644
@@ -1843,9 +1843,6 @@ static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
 
 	sky2->tx_cons = idx;
 	smp_mb();
-
-	if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
-		netif_wake_queue(dev);
 }
 
 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)

@@ -2416,8 +2413,11 @@ static inline void sky2_tx_done(struct net_device *dev, u16 last)
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 
-	if (netif_running(dev))
+	if (netif_running(dev)) {
 		sky2_tx_complete(sky2, last);
+		if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
+			netif_wake_queue(dev);
+	}
 }
 
 static inline void sky2_skb_rx(const struct sky2_port *sky2,

@@ -1843,9 +1843,6 @@ static void sky2_tx_complete(struct sky2
 
 	sky2->tx_cons = idx;
 	smp_mb();
-
-	if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
-		netif_wake_queue(dev);
 }
 
 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)

@@ -2416,8 +2413,12 @@ static inline void sky2_tx_done(struct n
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 
-	if (netif_running(dev))
+	if (netif_running(dev) && netif_device_present(dev)) {
 		sky2_tx_complete(sky2, last);
+
+		if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
+			netif_wake_queue(dev);
+	}
 }
 
 static inline void sky2_skb_rx(const struct sky2_port *sky2,

@@ -3197,6 +3198,7 @@ static int sky2_reattach(struct net_devi
 		} else {
 			netif_device_attach(dev);
 			sky2_set_multicast(dev);
+			netif_start_queue(dev);
 		}
 	}
 

@@ -1843,9 +1843,6 @@ static void sky2_tx_complete(struct sky2
 
 	sky2->tx_cons = idx;
 	smp_mb();
-
-	if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
-		netif_wake_queue(dev);
 }
 
 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)

@@ -2416,8 +2413,12 @@ static inline void sky2_tx_done(struct n
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 
-	if (netif_running(dev))
+	if (netif_running(dev) && netif_device_present(dev)) {
 		sky2_tx_complete(sky2, last);
+
+		if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
+			netif_wake_queue(dev);
+	}
 }
 
 static inline void sky2_skb_rx(const struct sky2_port *sky2,

@@ -3197,6 +3198,7 @@ static int sky2_reattach(struct net_devi
 		} else {
 			netif_device_attach(dev);
 			sky2_set_multicast(dev);
+			netif_start_queue(dev);
 		}
 	}
 

-- 
@@ -1596,6 +1596,9 @@ static inline int tx_inuse(const struct 
 /* Number of list elements available for next tx */
 static inline int tx_avail(const struct sky2_port *sky2)
 {
+	/* Makes sure update of tx_prod from start_xmit and
+	   tx_cons from tx_done are seen. */
+	smp_mb();
 	return sky2->tx_pending - tx_inuse(sky2);
 }
 

@@ -1618,8 +1621,7 @@ static unsigned tx_le_req(const struct s
 	return count;
 }
 
-static void sky2_tx_unmap(struct pci_dev *pdev,
-			  const struct tx_ring_info *re)
+static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
 {
 	if (re->flags & TX_MAP_SINGLE)
 		pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),

@@ -1629,6 +1631,7 @@ static void sky2_tx_unmap(struct pci_dev
 		pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
 			       pci_unmap_len(re, maplen),
 			       PCI_DMA_TODEVICE);
+	re->flags = 0;
 }
 
 /*

@@ -1804,7 +1807,8 @@ mapping_error:
 }
 
 /*
- * Free ring elements from starting at tx_cons until "done"
+ * Transmit complete processing
+ * Free ring elements from starting at tx_cons until done index
  *
  * NB:
  *  1. The hardware will tell us about partial completion of multi-part

@@ -1813,9 +1817,9 @@ mapping_error:
  *     looks at the tail of the queue of FIFO (tx_cons), not
  *     the head (tx_prod)
  */
-static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
+static void sky2_tx_done(struct net_device *dev, u16 done)
 {
-	struct net_device *dev = sky2->netdev;
+	struct sky2_port *sky2 = netdev_priv(dev);
 	unsigned idx;
 
 	BUG_ON(done >= sky2->tx_ring_size);

@@ -1828,6 +1832,8 @@ static void sky2_tx_complete(struct sky2
 		sky2_tx_unmap(sky2->hw->pdev, re);
 
 		if (skb) {
+			re->skb = NULL;
+
 			if (unlikely(netif_msg_tx_done(sky2)))
 				printk(KERN_DEBUG "%s: tx done %u\n",
 				       dev->name, idx);

@@ -1836,13 +1842,10 @@ static void sky2_tx_complete(struct sky2
 			dev->stats.tx_bytes += skb->len;
 
 			dev_kfree_skb_any(skb);
-
-			sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
 		}
 	}
 
 	sky2->tx_cons = idx;
-	smp_mb();
 
 	if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
 		netif_wake_queue(dev);

@@ -1870,6 +1873,21 @@ static void sky2_tx_reset(struct sky2_hw
 	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
 }
 
+static void sky2_tx_clean(struct sky2_port *sky2)
+{
+	u16 idx;
+
+	for (idx = 0; idx < sky2->tx_ring_size; idx++) {
+		struct tx_ring_info *re = sky2->tx_ring + idx;
+
+		sky2_tx_unmap(sky2->hw->pdev, re);
+		if (re->skb) {
+			dev_kfree_skb_any(re->skb);
+			re->skb = NULL;
+		}
+	}
+}
+
 /* Network shutdown */
 static int sky2_down(struct net_device *dev)
 {

@@ -1933,8 +1951,7 @@ static int sky2_down(struct net_device *
 	sky2_tx_reset(hw, port);
 
 	/* Free any pending frames stuck in HW queue */
-	sky2_tx_complete(sky2, sky2->tx_prod);
-
+	sky2_tx_clean(sky2);
 	sky2_rx_clean(sky2);
 
 	sky2_free_buffers(sky2);

@@ -2411,15 +2428,6 @@ error:
 	goto resubmit;
 }
 
-/* Transmit complete */
-static inline void sky2_tx_done(struct net_device *dev, u16 last)
-{
-	struct sky2_port *sky2 = netdev_priv(dev);
-
-	if (netif_running(dev))
-		sky2_tx_complete(sky2, last);
-}
-
 static inline void sky2_skb_rx(const struct sky2_port *sky2,
 			       u32 status, struct sk_buff *skb)
 {

@@ -4201,7 +4209,7 @@ static int sky2_debug_show(struct seq_fi
 
 	/* Dump contents of tx ring */
 	sop = 1;
-	for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
+	for (idx = sky2->tx_cons; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
 	     idx = RING_NEXT(idx, sky2->tx_ring_size)) {
 		const struct sky2_tx_le *le = sky2->tx_le + idx;
 		u32 a = le32_to_cpu(le->addr);

@@ -2187,7 +2187,6 @@ struct sky2_port {
 	u16		     tx_ring_size;
 	u16		     tx_cons;		/* next le to check */
 	u16		     tx_prod;		/* next le to use */
-	u16		     tx_next;		/* debug only */
 
 	u16		     tx_pending;
 	u16		     tx_last_mss;

@@ -1596,6 +1596,9 @@ static inline int tx_inuse(const struct 
 /* Number of list elements available for next tx */
 static inline int tx_avail(const struct sky2_port *sky2)
 {
+	/* Makes sure update of tx_prod from start_xmit and
+	   tx_cons from tx_done are seen. */
+	smp_mb();
 	return sky2->tx_pending - tx_inuse(sky2);
 }
 

@@ -1618,8 +1621,7 @@ static unsigned tx_le_req(const struct s
 	return count;
 }
 
-static void sky2_tx_unmap(struct pci_dev *pdev,
-			  const struct tx_ring_info *re)
+static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
 {
 	if (re->flags & TX_MAP_SINGLE)
 		pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),

@@ -1629,6 +1631,7 @@ static void sky2_tx_unmap(struct pci_dev
 		pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
 			       pci_unmap_len(re, maplen),
 			       PCI_DMA_TODEVICE);
+	re->flags = 0;
 }
 
 /*

@@ -1804,7 +1807,8 @@ mapping_error:
 }
 
 /*
- * Free ring elements from starting at tx_cons until "done"
+ * Transmit complete processing
+ * Free ring elements from starting at tx_cons until done index
  *
  * NB:
  *  1. The hardware will tell us about partial completion of multi-part

@@ -1813,9 +1817,9 @@ mapping_error:
  *     looks at the tail of the queue of FIFO (tx_cons), not
  *     the head (tx_prod)
  */
-static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
+static void sky2_tx_done(struct net_device *dev, u16 done)
 {
-	struct net_device *dev = sky2->netdev;
+	struct sky2_port *sky2 = netdev_priv(dev);
 	unsigned idx;
 
 	BUG_ON(done >= sky2->tx_ring_size);

@@ -1828,6 +1832,8 @@ static void sky2_tx_complete(struct sky2
 		sky2_tx_unmap(sky2->hw->pdev, re);
 
 		if (skb) {
+			re->skb = NULL;
+
 			if (unlikely(netif_msg_tx_done(sky2)))
 				printk(KERN_DEBUG "%s: tx done %u\n",
 				       dev->name, idx);

@@ -1836,13 +1842,10 @@ static void sky2_tx_complete(struct sky2
 			dev->stats.tx_bytes += skb->len;
 
 			dev_kfree_skb_any(skb);
-
-			sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
 		}
 	}
 
 	sky2->tx_cons = idx;
-	smp_mb();
 
 	if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
 		netif_wake_queue(dev);

@@ -1870,6 +1873,21 @@ static void sky2_tx_reset(struct sky2_hw
 	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
 }
 
+static void sky2_tx_clean(struct sky2_port *sky2)
+{
+	u16 idx;
+
+	for (idx = 0; idx < sky2->tx_ring_size; idx++) {
+		struct tx_ring_info *re = sky2->tx_ring + idx;
+
+		sky2_tx_unmap(sky2->hw->pdev, re);
+		if (re->skb) {
+			dev_kfree_skb_any(re->skb);
+			re->skb = NULL;
+		}
+	}
+}
+
 /* Network shutdown */
 static int sky2_down(struct net_device *dev)
 {

@@ -1933,8 +1951,7 @@ static int sky2_down(struct net_device *
 	sky2_tx_reset(hw, port);
 
 	/* Free any pending frames stuck in HW queue */
-	sky2_tx_complete(sky2, sky2->tx_prod);
-
+	sky2_tx_clean(sky2);
 	sky2_rx_clean(sky2);
 
 	sky2_free_buffers(sky2);

@@ -2411,15 +2428,6 @@ error:
 	goto resubmit;
 }
 
-/* Transmit complete */
-static inline void sky2_tx_done(struct net_device *dev, u16 last)
-{
-	struct sky2_port *sky2 = netdev_priv(dev);
-
-	if (netif_running(dev))
-		sky2_tx_complete(sky2, last);
-}
-
 static inline void sky2_skb_rx(const struct sky2_port *sky2,
 			       u32 status, struct sk_buff *skb)
 {

@@ -4201,7 +4209,7 @@ static int sky2_debug_show(struct seq_fi
 
 	/* Dump contents of tx ring */
 	sop = 1;
-	for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
+	for (idx = sky2->tx_cons; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
 	     idx = RING_NEXT(idx, sky2->tx_ring_size)) {
 		const struct sky2_tx_le *le = sky2->tx_le + idx;
 		u32 a = le32_to_cpu(le->addr);

@@ -2187,7 +2187,6 @@ struct sky2_port {
 	u16		     tx_ring_size;
 	u16		     tx_cons;		/* next le to check */
 	u16		     tx_prod;		/* next le to use */
-	u16		     tx_next;		/* debug only */
 
 	u16		     tx_pending;
 	u16		     tx_last_mss;

@@ -1596,6 +1596,9 @@ static inline int tx_inuse(const struct 
 /* Number of list elements available for next tx */
 static inline int tx_avail(const struct sky2_port *sky2)
 {
+	/* Makes sure update of tx_prod from start_xmit and
+	   tx_cons from tx_done are seen. */
+	smp_mb();
 	return sky2->tx_pending - tx_inuse(sky2);
 }
 

@@ -1618,8 +1621,7 @@ static unsigned tx_le_req(const struct s
 	return count;
 }
 
-static void sky2_tx_unmap(struct pci_dev *pdev,
-			  const struct tx_ring_info *re)
+static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
 {
 	if (re->flags & TX_MAP_SINGLE)
 		pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),

@@ -1629,6 +1631,7 @@ static void sky2_tx_unmap(struct pci_dev
 		pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
 			       pci_unmap_len(re, maplen),
 			       PCI_DMA_TODEVICE);
+	re->flags = 0;
 }
 
 /*

@@ -1804,7 +1807,8 @@ mapping_error:
 }
 
 /*
- * Free ring elements from starting at tx_cons until "done"
+ * Transmit complete processing
+ * Free ring elements from starting at tx_cons until done index
  *
  * NB:
  *  1. The hardware will tell us about partial completion of multi-part

@@ -1813,11 +1817,14 @@ mapping_error:
  *     looks at the tail of the queue of FIFO (tx_cons), not
  *     the head (tx_prod)
  */
-static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
+static void sky2_tx_done(struct net_device *dev, u16 done)
 {
-	struct net_device *dev = sky2->netdev;
+	struct sky2_port *sky2 = netdev_priv(dev);
 	unsigned idx;
 
+	if (unlikely(!netif_running(dev)))
+		return;
+
 	BUG_ON(done >= sky2->tx_ring_size);
 
 	for (idx = sky2->tx_cons; idx != done;

@@ -1828,6 +1835,8 @@ static void sky2_tx_complete(struct sky2
 		sky2_tx_unmap(sky2->hw->pdev, re);
 
 		if (skb) {
+			re->skb = NULL;
+
 			if (unlikely(netif_msg_tx_done(sky2)))
 				printk(KERN_DEBUG "%s: tx done %u\n",
 				       dev->name, idx);

@@ -1836,13 +1845,10 @@ static void sky2_tx_complete(struct sky2
 			dev->stats.tx_bytes += skb->len;
 
 			dev_kfree_skb_any(skb);
-
-			sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
 		}
 	}
 
 	sky2->tx_cons = idx;
-	smp_mb();
 
 	if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
 		netif_wake_queue(dev);

@@ -1870,6 +1876,21 @@ static void sky2_tx_reset(struct sky2_hw
 	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
 }
 
+static void sky2_tx_clean(struct sky2_port *sky2)
+{
+	u16 idx;
+
+	for (idx = 0; idx < sky2->tx_ring_size; idx++) {
+		struct tx_ring_info *re = sky2->tx_ring + idx;
+
+		sky2_tx_unmap(sky2->hw->pdev, re);
+		if (re->skb) {
+			dev_kfree_skb_any(re->skb);
+			re->skb = NULL;
+		}
+	}
+}
+
 /* Network shutdown */
 static int sky2_down(struct net_device *dev)
 {

@@ -1933,8 +1954,7 @@ static int sky2_down(struct net_device *
 	sky2_tx_reset(hw, port);
 
 	/* Free any pending frames stuck in HW queue */
-	sky2_tx_complete(sky2, sky2->tx_prod);
-
+	sky2_tx_clean(sky2);
 	sky2_rx_clean(sky2);
 
 	sky2_free_buffers(sky2);

@@ -2411,15 +2431,6 @@ error:
 	goto resubmit;
 }
 
-/* Transmit complete */
-static inline void sky2_tx_done(struct net_device *dev, u16 last)
-{
-	struct sky2_port *sky2 = netdev_priv(dev);
-
-	if (netif_running(dev))
-		sky2_tx_complete(sky2, last);
-}
-
 static inline void sky2_skb_rx(const struct sky2_port *sky2,
 			       u32 status, struct sk_buff *skb)
 {

@@ -4201,7 +4212,7 @@ static int sky2_debug_show(struct seq_fi
 
 	/* Dump contents of tx ring */
 	sop = 1;
-	for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
+	for (idx = sky2->tx_cons; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
 	     idx = RING_NEXT(idx, sky2->tx_ring_size)) {
 		const struct sky2_tx_le *le = sky2->tx_le + idx;
 		u32 a = le32_to_cpu(le->addr);

@@ -2187,7 +2187,6 @@ struct sky2_port {
 	u16		     tx_ring_size;
 	u16		     tx_cons;		/* next le to check */
 	u16		     tx_prod;		/* next le to use */
-	u16		     tx_next;		/* debug only */
 
 	u16		     tx_pending;
 	u16		     tx_last_mss;

@@ -1596,6 +1596,9 @@ static inline int tx_inuse(const struct 
 /* Number of list elements available for next tx */
 static inline int tx_avail(const struct sky2_port *sky2)
 {
+	/* Makes sure update of tx_prod from start_xmit and
+	   tx_cons from tx_done are seen. */
+	smp_mb();
 	return sky2->tx_pending - tx_inuse(sky2);
 }
 

@@ -1618,8 +1621,7 @@ static unsigned tx_le_req(const struct s
 	return count;
 }
 
-static void sky2_tx_unmap(struct pci_dev *pdev,
-			  const struct tx_ring_info *re)
+static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
 {
 	if (re->flags & TX_MAP_SINGLE)
 		pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),

@@ -1629,6 +1631,7 @@ static void sky2_tx_unmap(struct pci_dev
 		pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
 			       pci_unmap_len(re, maplen),
 			       PCI_DMA_TODEVICE);
+	re->flags = 0;
 }
 
 /*

@@ -1804,7 +1807,8 @@ mapping_error:
 }
 
 /*
- * Free ring elements from starting at tx_cons until "done"
+ * Transmit complete processing
+ * Free ring elements from starting at tx_cons until done index
  *
  * NB:
  *  1. The hardware will tell us about partial completion of multi-part

@@ -1813,11 +1817,14 @@ mapping_error:
  *     looks at the tail of the queue of FIFO (tx_cons), not
  *     the head (tx_prod)
  */
-static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
+static void sky2_tx_done(struct net_device *dev, u16 done)
 {
-	struct net_device *dev = sky2->netdev;
+	struct sky2_port *sky2 = netdev_priv(dev);
 	unsigned idx;
 
+	if (unlikely(!netif_running(dev)))
+		return;
+
 	BUG_ON(done >= sky2->tx_ring_size);
 
 	for (idx = sky2->tx_cons; idx != done;

@@ -1828,6 +1835,8 @@ static void sky2_tx_complete(struct sky2
 		sky2_tx_unmap(sky2->hw->pdev, re);
 
 		if (skb) {
+			re->skb = NULL;
+
 			if (unlikely(netif_msg_tx_done(sky2)))
 				printk(KERN_DEBUG "%s: tx done %u\n",
 				       dev->name, idx);

@@ -1836,13 +1845,10 @@ static void sky2_tx_complete(struct sky2
 			dev->stats.tx_bytes += skb->len;
 
 			dev_kfree_skb_any(skb);
-
-			sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
 		}
 	}
 
 	sky2->tx_cons = idx;
-	smp_mb();
 
 	if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
 		netif_wake_queue(dev);

@@ -1870,6 +1876,21 @@ static void sky2_tx_reset(struct sky2_hw
 	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
 }
 
+static void sky2_tx_clean(struct sky2_port *sky2)
+{
+	u16 idx;
+
+	for (idx = 0; idx < sky2->tx_ring_size; idx++) {
+		struct tx_ring_info *re = sky2->tx_ring + idx;
+
+		sky2_tx_unmap(sky2->hw->pdev, re);
+		if (re->skb) {
+			dev_kfree_skb_any(re->skb);
+			re->skb = NULL;
+		}
+	}
+}
+
 /* Network shutdown */
 static int sky2_down(struct net_device *dev)
 {

@@ -1933,8 +1954,7 @@ static int sky2_down(struct net_device *
 	sky2_tx_reset(hw, port);
 
 	/* Free any pending frames stuck in HW queue */
-	sky2_tx_complete(sky2, sky2->tx_prod);
-
+	sky2_tx_clean(sky2);
 	sky2_rx_clean(sky2);
 
 	sky2_free_buffers(sky2);

@@ -2411,15 +2431,6 @@ error:
 	goto resubmit;
 }
 
-/* Transmit complete */
-static inline void sky2_tx_done(struct net_device *dev, u16 last)
-{
-	struct sky2_port *sky2 = netdev_priv(dev);
-
-	if (netif_running(dev))
-		sky2_tx_complete(sky2, last);
-}
-
 static inline void sky2_skb_rx(const struct sky2_port *sky2,
 			       u32 status, struct sk_buff *skb)
 {

@@ -4201,7 +4212,7 @@ static int sky2_debug_show(struct seq_fi
 
 	/* Dump contents of tx ring */
 	sop = 1;
-	for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
+	for (idx = sky2->tx_cons; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
 	     idx = RING_NEXT(idx, sky2->tx_ring_size)) {
 		const struct sky2_tx_le *le = sky2->tx_le + idx;
 		u32 a = le32_to_cpu(le->addr);

@@ -2187,7 +2187,6 @@ struct sky2_port {
 	u16		     tx_ring_size;
 	u16		     tx_cons;		/* next le to check */
 	u16		     tx_prod;		/* next le to use */
-	u16		     tx_next;		/* debug only */
 
 	u16		     tx_pending;
 	u16		     tx_last_mss;

@@ -1596,6 +1596,9 @@ static inline int tx_inuse(const struct
  /* Number of list elements available for next tx */
  static inline int tx_avail(const struct sky2_port *sky2)
  {
+	/* Makes sure update of tx_prod from start_xmit and
+	   tx_cons from tx_done are seen. */
+	smp_mb();
  	return sky2->tx_pending - tx_inuse(sky2);
  }
 

@@ -1618,8 +1621,7 @@ static unsigned tx_le_req(const struct s
  	return count;
  }
 
-static void sky2_tx_unmap(struct pci_dev *pdev,
-			  const struct tx_ring_info *re)
+static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
  {
  	if (re->flags&  TX_MAP_SINGLE)
  		pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),

@@ -1629,6 +1631,7 @@ static void sky2_tx_unmap(struct pci_dev
  		pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
  			       pci_unmap_len(re, maplen),
  			       PCI_DMA_TODEVICE);
+	re->flags = 0;
  }
 
  /*

@@ -1804,7 +1807,8 @@ mapping_error:
  }
 
  /*
- * Free ring elements from starting at tx_cons until "done"
+ * Transmit complete processing
+ * Free ring elements from starting at tx_cons until done index
   *
   * NB:
   *  1. The hardware will tell us about partial completion of multi-part

@@ -1813,11 +1817,14 @@ mapping_error:
   *     looks at the tail of the queue of FIFO (tx_cons), not
   *     the head (tx_prod)
   */
-static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
+static void sky2_tx_done(struct net_device *dev, u16 done)
  {
-	struct net_device *dev = sky2->netdev;
+	struct sky2_port *sky2 = netdev_priv(dev);
  	unsigned idx;
 
+	if (unlikely(!netif_running(dev)))
+		return;
+
  	BUG_ON(done>= sky2->tx_ring_size);
 
  	for (idx = sky2->tx_cons; idx != done;

@@ -1828,6 +1835,8 @@ static void sky2_tx_complete(struct sky2
  		sky2_tx_unmap(sky2->hw->pdev, re);
 
  		if (skb) {
+			re->skb = NULL;
+
  			if (unlikely(netif_msg_tx_done(sky2)))
  				printk(KERN_DEBUG "%s: tx done %u\n",
  				       dev->name, idx);

@@ -1836,13 +1845,10 @@ static void sky2_tx_complete(struct sky2
  			dev->stats.tx_bytes += skb->len;
 
  			dev_kfree_skb_any(skb);
-
-			sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
  		}
  	}
 
  	sky2->tx_cons = idx;
-	smp_mb();
 
  	if (tx_avail(sky2)>  MAX_SKB_TX_LE + 4)
  		netif_wake_queue(dev);

@@ -1870,6 +1876,21 @@ static void sky2_tx_reset(struct sky2_hw
  	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
  }
 
+static void sky2_tx_clean(struct sky2_port *sky2)
+{
+	u16 idx;
+
+	for (idx = 0; idx<  sky2->tx_ring_size; idx++) {
+		struct tx_ring_info *re = sky2->tx_ring + idx;
+
+		sky2_tx_unmap(sky2->hw->pdev, re);
+		if (re->skb) {
+			dev_kfree_skb_any(re->skb);
+			re->skb = NULL;
+		}
+	}
+}
+
  /* Network shutdown */
  static int sky2_down(struct net_device *dev)
  {

@@ -1933,8 +1954,7 @@ static int sky2_down(struct net_device *
  	sky2_tx_reset(hw, port);
 
  	/* Free any pending frames stuck in HW queue */
-	sky2_tx_complete(sky2, sky2->tx_prod);
-
+	sky2_tx_clean(sky2);
  	sky2_rx_clean(sky2);
 
  	sky2_free_buffers(sky2);

@@ -2411,15 +2431,6 @@ error:
  	goto resubmit;
  }
 
-/* Transmit complete */
-static inline void sky2_tx_done(struct net_device *dev, u16 last)
-{
-	struct sky2_port *sky2 = netdev_priv(dev);
-
-	if (netif_running(dev))
-		sky2_tx_complete(sky2, last);
-}
-
  static inline void sky2_skb_rx(const struct sky2_port *sky2,
  			       u32 status, struct sk_buff *skb)
  {

@@ -4201,7 +4212,7 @@ static int sky2_debug_show(struct seq_fi
 
  	/* Dump contents of tx ring */
  	sop = 1;
-	for (idx = sky2->tx_next; idx != sky2->tx_prod&&  idx<  sky2->tx_ring_size;
+	for (idx = sky2->tx_cons; idx != sky2->tx_prod&&  idx<  sky2->tx_ring_size;
  	     idx = RING_NEXT(idx, sky2->tx_ring_size)) {
  		const struct sky2_tx_le *le = sky2->tx_le + idx;
  		u32 a = le32_to_cpu(le->addr);

@@ -2187,7 +2187,6 @@ struct sky2_port {
  	u16		     tx_ring_size;
  	u16		     tx_cons;		/* next le to check */
  	u16		     tx_prod;		/* next le to use */
-	u16		     tx_next;		/* debug only */
 
  	u16		     tx_pending;
  	u16		     tx_last_mss;

@@ -1596,6 +1596,9 @@ static inline int tx_inuse(const struct
  /* Number of list elements available for next tx */
  static inline int tx_avail(const struct sky2_port *sky2)
  {
+	/* Makes sure update of tx_prod from start_xmit and
+	   tx_cons from tx_done are seen. */
+	smp_mb();
  	return sky2->tx_pending - tx_inuse(sky2);
  }
 

@@ -1618,8 +1621,7 @@ static unsigned tx_le_req(const struct s
  	return count;
  }
 
-static void sky2_tx_unmap(struct pci_dev *pdev,
-			  const struct tx_ring_info *re)
+static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
  {
  	if (re->flags&  TX_MAP_SINGLE)
  		pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),

@@ -1629,6 +1631,7 @@ static void sky2_tx_unmap(struct pci_dev
  		pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
  			       pci_unmap_len(re, maplen),
  			       PCI_DMA_TODEVICE);
+	re->flags = 0;
  }
 
  /*

@@ -1804,7 +1807,8 @@ mapping_error:
  }
 
  /*
- * Free ring elements from starting at tx_cons until "done"
+ * Transmit complete processing
+ * Free ring elements from starting at tx_cons until done index
   *
   * NB:
   *  1. The hardware will tell us about partial completion of multi-part

@@ -1813,9 +1817,9 @@ mapping_error:
   *     looks at the tail of the queue of FIFO (tx_cons), not
   *     the head (tx_prod)
   */
-static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
+static void sky2_tx_done(struct net_device *dev, u16 done)
  {
-	struct net_device *dev = sky2->netdev;
+	struct sky2_port *sky2 = netdev_priv(dev);
  	unsigned idx;
 
  	BUG_ON(done>= sky2->tx_ring_size);

@@ -1828,6 +1832,8 @@ static void sky2_tx_complete(struct sky2
  		sky2_tx_unmap(sky2->hw->pdev, re);
 
  		if (skb) {
+			re->skb = NULL;
+
  			if (unlikely(netif_msg_tx_done(sky2)))
  				printk(KERN_DEBUG "%s: tx done %u\n",
  				       dev->name, idx);

@@ -1836,13 +1842,10 @@ static void sky2_tx_complete(struct sky2
  			dev->stats.tx_bytes += skb->len;
 
  			dev_kfree_skb_any(skb);
-
-			sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
  		}
  	}
 
  	sky2->tx_cons = idx;
-	smp_mb();
 
  	if (tx_avail(sky2)>  MAX_SKB_TX_LE + 4)
  		netif_wake_queue(dev);

@@ -1870,6 +1873,21 @@ static void sky2_tx_reset(struct sky2_hw
  	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
  }
 
+static void sky2_tx_clean(struct sky2_port *sky2)
+{
+	u16 idx;
+
+	for (idx = 0; idx<  sky2->tx_ring_size; idx++) {
+		struct tx_ring_info *re = sky2->tx_ring + idx;
+
+		sky2_tx_unmap(sky2->hw->pdev, re);
+		if (re->skb) {
+			dev_kfree_skb_any(re->skb);
+			re->skb = NULL;
+		}
+	}
+}
+
  /* Network shutdown */
  static int sky2_down(struct net_device *dev)
  {

@@ -1933,8 +1951,7 @@ static int sky2_down(struct net_device *
  	sky2_tx_reset(hw, port);
 
  	/* Free any pending frames stuck in HW queue */
-	sky2_tx_complete(sky2, sky2->tx_prod);
-
+	sky2_tx_clean(sky2);
  	sky2_rx_clean(sky2);
 
  	sky2_free_buffers(sky2);

@@ -2411,15 +2428,6 @@ error:
  	goto resubmit;
  }
 
-/* Transmit complete */
-static inline void sky2_tx_done(struct net_device *dev, u16 last)
-{
-	struct sky2_port *sky2 = netdev_priv(dev);
-
-	if (netif_running(dev))
-		sky2_tx_complete(sky2, last);
-}
-
  static inline void sky2_skb_rx(const struct sky2_port *sky2,
  			       u32 status, struct sk_buff *skb)
  {

@@ -4201,7 +4209,7 @@ static int sky2_debug_show(struct seq_fi
 
  	/* Dump contents of tx ring */
  	sop = 1;
-	for (idx = sky2->tx_next; idx != sky2->tx_prod&&  idx<  sky2->tx_ring_size;
+	for (idx = sky2->tx_cons; idx != sky2->tx_prod&&  idx<  sky2->tx_ring_size;
  	     idx = RING_NEXT(idx, sky2->tx_ring_size)) {
  		const struct sky2_tx_le *le = sky2->tx_le + idx;
  		u32 a = le32_to_cpu(le->addr);

@@ -2187,7 +2187,6 @@ struct sky2_port {
  	u16		     tx_ring_size;
  	u16		     tx_cons;		/* next le to check */
  	u16		     tx_prod;		/* next le to use */
-	u16		     tx_next;		/* debug only */
 
  	u16		     tx_pending;
  	u16		     tx_last_mss;

@@ -1596,6 +1596,9 @@ static inline int tx_inuse(const struct
  /* Number of list elements available for next tx */
  static inline int tx_avail(const struct sky2_port *sky2)
  {
+    /* Makes sure update of tx_prod from start_xmit and
+       tx_cons from tx_done are seen. */
+    smp_mb();
      return sky2->tx_pending - tx_inuse(sky2);
  }
 

@@ -1618,8 +1621,7 @@ static unsigned tx_le_req(const struct s
      return count;
  }
 
-static void sky2_tx_unmap(struct pci_dev *pdev,
-              const struct tx_ring_info *re)
+static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info 
 *re)
  {
      if (re->flags&  TX_MAP_SINGLE)

@@ -1629,6 +1631,7 @@ static void sky2_tx_unmap(struct pci_dev
          pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
                     pci_unmap_len(re, maplen),
                     PCI_DMA_TODEVICE);
+    re->flags = 0;
  }
 
  /*

@@ -1804,7 +1807,8 @@ mapping_error:
  }
 
  /*
- * Free ring elements from starting at tx_cons until "done"
+ * Transmit complete processing
+ * Free ring elements from starting at tx_cons until done index
   *
   * NB:
   *  1. The hardware will tell us about partial completion of 

@@ -1813,9 +1817,9 @@ mapping_error:
   *     looks at the tail of the queue of FIFO (tx_cons), not
   *     the head (tx_prod)
   */
-static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
+static void sky2_tx_done(struct net_device *dev, u16 done)
  {
-    struct net_device *dev = sky2->netdev;
+    struct sky2_port *sky2 = netdev_priv(dev);
      unsigned idx;
 
      BUG_ON(done>= sky2->tx_ring_size);

@@ -1828,6 +1832,8 @@ static void sky2_tx_complete(struct sky2
          sky2_tx_unmap(sky2->hw->pdev, re);
 
          if (skb) {
+            re->skb = NULL;
+
              if (unlikely(netif_msg_tx_done(sky2)))
                  printk(KERN_DEBUG "%s: tx done %u\n",
                         dev->name, idx);

@@ -1836,13 +1842,10 @@ static void sky2_tx_complete(struct sky2
              dev->stats.tx_bytes += skb->len;
 
              dev_kfree_skb_any(skb);
-
-            sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
          }
      }
 
      sky2->tx_cons = idx;
-    smp_mb();
 
      if (tx_avail(sky2)>  MAX_SKB_TX_LE + 4)
          netif_wake_queue(dev);

@@ -1870,6 +1873,21 @@ static void sky2_tx_reset(struct sky2_hw
      sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
  }
 
+static void sky2_tx_clean(struct sky2_port *sky2)
+{
+    u16 idx;
+
+    for (idx = 0; idx<  sky2->tx_ring_size; idx++) {
+        struct tx_ring_info *re = sky2->tx_ring + idx;
+
+        sky2_tx_unmap(sky2->hw->pdev, re);
+        if (re->skb) {
+            dev_kfree_skb_any(re->skb);
+            re->skb = NULL;
+        }
+    }
+}
+
  /* Network shutdown */
  static int sky2_down(struct net_device *dev)
  {

@@ -1933,8 +1951,7 @@ static int sky2_down(struct net_device *
      sky2_tx_reset(hw, port);
 
      /* Free any pending frames stuck in HW queue */
-    sky2_tx_complete(sky2, sky2->tx_prod);
-
+    sky2_tx_clean(sky2);
      sky2_rx_clean(sky2);
 
      sky2_free_buffers(sky2);

@@ -2411,15 +2428,6 @@ error:
      goto resubmit;
  }
 
-/* Transmit complete */
-static inline void sky2_tx_done(struct net_device *dev, u16 last)
-{
-    struct sky2_port *sky2 = netdev_priv(dev);
-
-    if (netif_running(dev))
-        sky2_tx_complete(sky2, last);
-}
-
  static inline void sky2_skb_rx(const struct sky2_port *sky2,
                     u32 status, struct sk_buff *skb)
  {

@@ -4201,7 +4209,7 @@ static int sky2_debug_show(struct seq_fi
 
      /* Dump contents of tx ring */
      sop = 1;
-    for (idx = sky2->tx_next; idx != sky2->tx_prod&&  idx<  
 sky2->tx_ring_size;
+    for (idx = sky2->tx_cons; idx != sky2->tx_prod&&  idx<  
 sky2->tx_ring_size;
           idx = RING_NEXT(idx, sky2->tx_ring_size)) {

          const struct sky2_tx_le *le = sky2->tx_le + idx;
          u32 a = le32_to_cpu(le->addr);
@@ -2187,7 +2187,6 @@ struct sky2_port {
      u16             tx_ring_size;
      u16             tx_cons;        /* next le to check */
      u16             tx_prod;        /* next le to use */
-    u16             tx_next;        /* debug only */
 
      u16             tx_pending;
      u16             tx_last_mss;

@@ -1596,6 +1596,9 @@ static inline int tx_inuse(const struct
  /* Number of list elements available for next tx */
  static inline int tx_avail(const struct sky2_port *sky2)
  {
+    /* Makes sure update of tx_prod from start_xmit and
+       tx_cons from tx_done are seen. */
+    smp_mb();
      return sky2->tx_pending - tx_inuse(sky2);
  }
 

@@ -1618,8 +1621,7 @@ static unsigned tx_le_req(const struct s
      return count;
  }
 
-static void sky2_tx_unmap(struct pci_dev *pdev,
-              const struct tx_ring_info *re)
+static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info 
 *re)
  {
      if (re->flags&  TX_MAP_SINGLE)

@@ -1629,6 +1631,7 @@ static void sky2_tx_unmap(struct pci_dev
          pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
                     pci_unmap_len(re, maplen),
                     PCI_DMA_TODEVICE);
+    re->flags = 0;
  }
 
  /*

@@ -1804,7 +1807,8 @@ mapping_error:
  }
 
  /*
- * Free ring elements from starting at tx_cons until "done"
+ * Transmit complete processing
+ * Free ring elements from starting at tx_cons until done index
   *
   * NB:
   *  1. The hardware will tell us about partial completion of 

@@ -1813,9 +1817,9 @@ mapping_error:
   *     looks at the tail of the queue of FIFO (tx_cons), not
   *     the head (tx_prod)
   */
-static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
+static void sky2_tx_done(struct net_device *dev, u16 done)
  {
-    struct net_device *dev = sky2->netdev;
+    struct sky2_port *sky2 = netdev_priv(dev);
      unsigned idx;
 
      BUG_ON(done>= sky2->tx_ring_size);

@@ -1828,6 +1832,8 @@ static void sky2_tx_complete(struct sky2
          sky2_tx_unmap(sky2->hw->pdev, re);
 
          if (skb) {
+            re->skb = NULL;
+
              if (unlikely(netif_msg_tx_done(sky2)))
                  printk(KERN_DEBUG "%s: tx done %u\n",
                         dev->name, idx);

@@ -1836,13 +1842,10 @@ static void sky2_tx_complete(struct sky2
              dev->stats.tx_bytes += skb->len;
 
              dev_kfree_skb_any(skb);
-
-            sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
          }
      }
 
      sky2->tx_cons = idx;
-    smp_mb();
 
      if (tx_avail(sky2)>  MAX_SKB_TX_LE + 4)
          netif_wake_queue(dev);

@@ -1870,6 +1873,21 @@ static void sky2_tx_reset(struct sky2_hw
      sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
  }
 
+static void sky2_tx_clean(struct sky2_port *sky2)
+{
+    u16 idx;
+
+    for (idx = 0; idx<  sky2->tx_ring_size; idx++) {
+        struct tx_ring_info *re = sky2->tx_ring + idx;
+
+        sky2_tx_unmap(sky2->hw->pdev, re);
+        if (re->skb) {
+            dev_kfree_skb_any(re->skb);
+            re->skb = NULL;
+        }
+    }
+}
+
  /* Network shutdown */
  static int sky2_down(struct net_device *dev)
  {

@@ -1933,8 +1951,7 @@ static int sky2_down(struct net_device *
      sky2_tx_reset(hw, port);
 
      /* Free any pending frames stuck in HW queue */
-    sky2_tx_complete(sky2, sky2->tx_prod);
-
+    sky2_tx_clean(sky2);
      sky2_rx_clean(sky2);
 
      sky2_free_buffers(sky2);

@@ -2411,15 +2428,6 @@ error:
      goto resubmit;
  }
 
-/* Transmit complete */
-static inline void sky2_tx_done(struct net_device *dev, u16 last)
-{
-    struct sky2_port *sky2 = netdev_priv(dev);
-
-    if (netif_running(dev))
-        sky2_tx_complete(sky2, last);
-}
-
  static inline void sky2_skb_rx(const struct sky2_port *sky2,
                     u32 status, struct sk_buff *skb)
  {

@@ -4201,7 +4209,7 @@ static int sky2_debug_show(struct seq_fi
 
      /* Dump contents of tx ring */
      sop = 1;
-    for (idx = sky2->tx_next; idx != sky2->tx_prod&&  idx<  
 sky2->tx_ring_size;
+    for (idx = sky2->tx_cons; idx != sky2->tx_prod&&  idx<  
 sky2->tx_ring_size;
           idx = RING_NEXT(idx, sky2->tx_ring_size)) {

          const struct sky2_tx_le *le = sky2->tx_le + idx;
          u32 a = le32_to_cpu(le->addr);
@@ -2187,7 +2187,6 @@ struct sky2_port {
      u16             tx_ring_size;
      u16             tx_cons;        /* next le to check */
      u16             tx_prod;        /* next le to use */
-    u16             tx_next;        /* debug only */
 
      u16             tx_pending;
      u16             tx_last_mss;

@@ -1596,6 +1596,9 @@ static inline int tx_inuse(const struct 
 /* Number of list elements available for next tx */
 static inline int tx_avail(const struct sky2_port *sky2)
 {
+	/* Makes sure update of tx_prod from start_xmit and
+	   tx_cons from tx_done are seen. */
+	smp_mb();
 	return sky2->tx_pending - tx_inuse(sky2);
 }
 

@@ -1618,8 +1621,7 @@ static unsigned tx_le_req(const struct s
 	return count;
 }
 
-static void sky2_tx_unmap(struct pci_dev *pdev,
-			  const struct tx_ring_info *re)
+static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
 {
 	if (re->flags & TX_MAP_SINGLE)
 		pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),

@@ -1629,6 +1631,7 @@ static void sky2_tx_unmap(struct pci_dev
 		pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
 			       pci_unmap_len(re, maplen),
 			       PCI_DMA_TODEVICE);
+	re->flags = 0;
 }
 
 /*

@@ -1804,7 +1807,8 @@ mapping_error:
 }
 
 /*
- * Free ring elements from starting at tx_cons until "done"
+ * Transmit complete processing
+ * Free ring elements from starting at tx_cons until done index
  *
  * NB:
  *  1. The hardware will tell us about partial completion of multi-part

@@ -1813,11 +1817,14 @@ mapping_error:
  *     looks at the tail of the queue of FIFO (tx_cons), not
  *     the head (tx_prod)
  */
-static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
+static void sky2_tx_done(struct net_device *dev, u16 done)
 {
-	struct net_device *dev = sky2->netdev;
+	struct sky2_port *sky2 = netdev_priv(dev);
 	unsigned idx;
 
+	if (unlikely(!netif_running(dev)))
+		return;
+
 	BUG_ON(done >= sky2->tx_ring_size);
 
 	for (idx = sky2->tx_cons; idx != done;

@@ -1828,6 +1835,8 @@ static void sky2_tx_complete(struct sky2
 		sky2_tx_unmap(sky2->hw->pdev, re);
 
 		if (skb) {
+			re->skb = NULL;
+
 			if (unlikely(netif_msg_tx_done(sky2)))
 				printk(KERN_DEBUG "%s: tx done %u\n",
 				       dev->name, idx);

@@ -1836,13 +1845,10 @@ static void sky2_tx_complete(struct sky2
 			dev->stats.tx_bytes += skb->len;
 
 			dev_kfree_skb_any(skb);
-
-			sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
 		}
 	}
 
 	sky2->tx_cons = idx;
-	smp_mb();
 
 	if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
 		netif_wake_queue(dev);

@@ -1870,6 +1876,21 @@ static void sky2_tx_reset(struct sky2_hw
 	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
 }
 
+static void sky2_tx_clean(struct sky2_port *sky2)
+{
+	u16 idx;
+
+	for (idx = 0; idx < sky2->tx_ring_size; idx++) {
+		struct tx_ring_info *re = sky2->tx_ring + idx;
+
+		sky2_tx_unmap(sky2->hw->pdev, re);
+		if (re->skb) {
+			dev_kfree_skb_any(re->skb);
+			re->skb = NULL;
+		}
+	}
+}
+
 /* Network shutdown */
 static int sky2_down(struct net_device *dev)
 {

@@ -1933,8 +1954,7 @@ static int sky2_down(struct net_device *
 	sky2_tx_reset(hw, port);
 
 	/* Free any pending frames stuck in HW queue */
-	sky2_tx_complete(sky2, sky2->tx_prod);
-
+	sky2_tx_clean(sky2);
 	sky2_rx_clean(sky2);
 
 	sky2_free_buffers(sky2);

@@ -2411,15 +2431,6 @@ error:
 	goto resubmit;
 }
 
-/* Transmit complete */
-static inline void sky2_tx_done(struct net_device *dev, u16 last)
-{
-	struct sky2_port *sky2 = netdev_priv(dev);
-
-	if (netif_running(dev))
-		sky2_tx_complete(sky2, last);
-}
-
 static inline void sky2_skb_rx(const struct sky2_port *sky2,
 			       u32 status, struct sk_buff *skb)
 {

@@ -3176,9 +3187,9 @@ static void sky2_reset(struct sky2_hw *h
 static void sky2_detach(struct net_device *dev)
 {
 	if (netif_running(dev)) {
-		netif_tx_lock(dev);
+		netif_tx_lock_bh(dev);
 		netif_device_detach(dev);	/* stop txq */
-		netif_tx_unlock(dev);
+		netif_tx_unlock_bh(dev);
 		sky2_down(dev);
 	}
 }

@@ -4201,7 +4212,7 @@ static int sky2_debug_show(struct seq_fi
 
 	/* Dump contents of tx ring */
 	sop = 1;
-	for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
+	for (idx = sky2->tx_cons; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
 	     idx = RING_NEXT(idx, sky2->tx_ring_size)) {
 		const struct sky2_tx_le *le = sky2->tx_le + idx;
 		u32 a = le32_to_cpu(le->addr);

@@ -2187,7 +2187,6 @@ struct sky2_port {
 	u16		     tx_ring_size;
 	u16		     tx_cons;		/* next le to check */
 	u16		     tx_prod;		/* next le to use */
-	u16		     tx_next;		/* debug only */
 
 	u16		     tx_pending;
 	u16		     tx_last_mss;

@@ -1596,6 +1596,9 @@ static inline int tx_inuse(const struct
  /* Number of list elements available for next tx */
  static inline int tx_avail(const struct sky2_port *sky2)
  {
+	/* Makes sure update of tx_prod from start_xmit and
+	   tx_cons from tx_done are seen. */
+	smp_mb();
  	return sky2->tx_pending - tx_inuse(sky2);
  }
 

@@ -1618,8 +1621,7 @@ static unsigned tx_le_req(const struct s
  	return count;
  }
 
-static void sky2_tx_unmap(struct pci_dev *pdev,
-			  const struct tx_ring_info *re)
+static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
  {
  	if (re->flags&  TX_MAP_SINGLE)
  		pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),

@@ -1629,6 +1631,7 @@ static void sky2_tx_unmap(struct pci_dev
  		pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
  			       pci_unmap_len(re, maplen),
  			       PCI_DMA_TODEVICE);
+	re->flags = 0;
  }
 
  /*

@@ -1804,7 +1807,8 @@ mapping_error:
  }
 
  /*
- * Free ring elements from starting at tx_cons until "done"
+ * Transmit complete processing
+ * Free ring elements from starting at tx_cons until done index
   *
   * NB:
   *  1. The hardware will tell us about partial completion of multi-part

@@ -1813,11 +1817,14 @@ mapping_error:
   *     looks at the tail of the queue of FIFO (tx_cons), not
   *     the head (tx_prod)
   */
-static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
+static void sky2_tx_done(struct net_device *dev, u16 done)
  {
-	struct net_device *dev = sky2->netdev;
+	struct sky2_port *sky2 = netdev_priv(dev);
  	unsigned idx;
 
+	if (unlikely(!netif_running(dev)))
+		return;
+
  	BUG_ON(done>= sky2->tx_ring_size);
 
  	for (idx = sky2->tx_cons; idx != done;

@@ -1828,6 +1835,8 @@ static void sky2_tx_complete(struct sky2
  		sky2_tx_unmap(sky2->hw->pdev, re);
 
  		if (skb) {
+			re->skb = NULL;
+
  			if (unlikely(netif_msg_tx_done(sky2)))
  				printk(KERN_DEBUG "%s: tx done %u\n",
  				       dev->name, idx);

@@ -1836,13 +1845,10 @@ static void sky2_tx_complete(struct sky2
  			dev->stats.tx_bytes += skb->len;
 
  			dev_kfree_skb_any(skb);
-
-			sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
  		}
  	}
 
  	sky2->tx_cons = idx;
-	smp_mb();
 
  	if (tx_avail(sky2)>  MAX_SKB_TX_LE + 4)
  		netif_wake_queue(dev);

@@ -1870,6 +1876,21 @@ static void sky2_tx_reset(struct sky2_hw
  	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
  }
 
+static void sky2_tx_clean(struct sky2_port *sky2)
+{
+	u16 idx;
+
+	for (idx = 0; idx<  sky2->tx_ring_size; idx++) {
+		struct tx_ring_info *re = sky2->tx_ring + idx;
+
+		sky2_tx_unmap(sky2->hw->pdev, re);
+		if (re->skb) {
+			dev_kfree_skb_any(re->skb);
+			re->skb = NULL;
+		}
+	}
+}
+
  /* Network shutdown */
  static int sky2_down(struct net_device *dev)
  {

@@ -1933,8 +1954,7 @@ static int sky2_down(struct net_device *
  	sky2_tx_reset(hw, port);
 
  	/* Free any pending frames stuck in HW queue */
-	sky2_tx_complete(sky2, sky2->tx_prod);
-
+	sky2_tx_clean(sky2);
  	sky2_rx_clean(sky2);
 
  	sky2_free_buffers(sky2);

@@ -2411,15 +2431,6 @@ error:
  	goto resubmit;
  }
 
-/* Transmit complete */
-static inline void sky2_tx_done(struct net_device *dev, u16 last)
-{
-	struct sky2_port *sky2 = netdev_priv(dev);
-
-	if (netif_running(dev))
-		sky2_tx_complete(sky2, last);
-}
-
  static inline void sky2_skb_rx(const struct sky2_port *sky2,
  			       u32 status, struct sk_buff *skb)
  {

@@ -3176,9 +3187,9 @@ static void sky2_reset(struct sky2_hw *h
  static void sky2_detach(struct net_device *dev)
  {
  	if (netif_running(dev)) {
-		netif_tx_lock(dev);
+		netif_tx_lock_bh(dev);
  		netif_device_detach(dev);	/* stop txq */
-		netif_tx_unlock(dev);
+		netif_tx_unlock_bh(dev);
  		sky2_down(dev);
  	}
  }

@@ -4201,7 +4212,7 @@ static int sky2_debug_show(struct seq_fi
 
  	/* Dump contents of tx ring */
  	sop = 1;
-	for (idx = sky2->tx_next; idx != sky2->tx_prod&&  idx<  sky2->tx_ring_size;
+	for (idx = sky2->tx_cons; idx != sky2->tx_prod&&  idx<  sky2->tx_ring_size;
  	     idx = RING_NEXT(idx, sky2->tx_ring_size)) {
  		const struct sky2_tx_le *le = sky2->tx_le + idx;
  		u32 a = le32_to_cpu(le->addr);

@@ -2187,7 +2187,6 @@ struct sky2_port {
  	u16		     tx_ring_size;
  	u16		     tx_cons;		/* next le to check */
  	u16		     tx_prod;		/* next le to use */
-	u16		     tx_next;		/* debug only */
 
  	u16		     tx_pending;
  	u16		     tx_last_mss;

@@ -1596,6 +1596,9 @@ static inline int tx_inuse(const struct 
 /* Number of list elements available for next tx */
 static inline int tx_avail(const struct sky2_port *sky2)
 {
+	/* Makes sure update of tx_prod from start_xmit and
+	   tx_cons from tx_done are seen. */
+	smp_mb();
 	return sky2->tx_pending - tx_inuse(sky2);
 }
 

@@ -1618,8 +1621,7 @@ static unsigned tx_le_req(const struct s
 	return count;
 }
 
-static void sky2_tx_unmap(struct pci_dev *pdev,
-			  const struct tx_ring_info *re)
+static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
 {
 	if (re->flags & TX_MAP_SINGLE)
 		pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),

@@ -1629,6 +1631,7 @@ static void sky2_tx_unmap(struct pci_dev
 		pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
 			       pci_unmap_len(re, maplen),
 			       PCI_DMA_TODEVICE);
+	re->flags = 0;
 }
 
 /*

@@ -1804,7 +1807,8 @@ mapping_error:
 }
 
 /*
- * Free ring elements from starting at tx_cons until "done"
+ * Transmit complete processing
+ * Free ring elements from starting at tx_cons until done index
  *
  * NB:
  *  1. The hardware will tell us about partial completion of multi-part

@@ -1813,11 +1817,14 @@ mapping_error:
  *     looks at the tail of the queue of FIFO (tx_cons), not
  *     the head (tx_prod)
  */
-static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
+static void sky2_tx_done(struct net_device *dev, u16 done)
 {
-	struct net_device *dev = sky2->netdev;
+	struct sky2_port *sky2 = netdev_priv(dev);
 	unsigned idx;
 
+	if (unlikely(!netif_running(dev)))
+		return;
+
 	BUG_ON(done >= sky2->tx_ring_size);
 
 	for (idx = sky2->tx_cons; idx != done;

@@ -1828,6 +1835,8 @@ static void sky2_tx_complete(struct sky2
 		sky2_tx_unmap(sky2->hw->pdev, re);
 
 		if (skb) {
+			re->skb = NULL;
+
 			if (unlikely(netif_msg_tx_done(sky2)))
 				printk(KERN_DEBUG "%s: tx done %u\n",
 				       dev->name, idx);

@@ -1836,13 +1845,10 @@ static void sky2_tx_complete(struct sky2
 			dev->stats.tx_bytes += skb->len;
 
 			dev_kfree_skb_any(skb);
-
-			sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
 		}
 	}
 
 	sky2->tx_cons = idx;
-	smp_mb();
 
 	if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
 		netif_wake_queue(dev);

@@ -1870,6 +1876,21 @@ static void sky2_tx_reset(struct sky2_hw
 	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
 }
 
+static void sky2_tx_clean(struct sky2_port *sky2)
+{
+	u16 idx;
+
+	for (idx = 0; idx < sky2->tx_ring_size; idx++) {
+		struct tx_ring_info *re = sky2->tx_ring + idx;
+
+		sky2_tx_unmap(sky2->hw->pdev, re);
+		if (re->skb) {
+			dev_kfree_skb_any(re->skb);
+			re->skb = NULL;
+		}
+	}
+}
+
 /* Network shutdown */
 static int sky2_down(struct net_device *dev)
 {

@@ -1933,8 +1954,7 @@ static int sky2_down(struct net_device *
 	sky2_tx_reset(hw, port);
 
 	/* Free any pending frames stuck in HW queue */
-	sky2_tx_complete(sky2, sky2->tx_prod);
-
+	sky2_tx_clean(sky2);
 	sky2_rx_clean(sky2);
 
 	sky2_free_buffers(sky2);

@@ -2411,15 +2431,6 @@ error:
 	goto resubmit;
 }
 
-/* Transmit complete */
-static inline void sky2_tx_done(struct net_device *dev, u16 last)
-{
-	struct sky2_port *sky2 = netdev_priv(dev);
-
-	if (netif_running(dev))
-		sky2_tx_complete(sky2, last);
-}
-
 static inline void sky2_skb_rx(const struct sky2_port *sky2,
 			       u32 status, struct sk_buff *skb)
 {

@@ -3176,9 +3187,9 @@ static void sky2_reset(struct sky2_hw *h
 static void sky2_detach(struct net_device *dev)
 {
 	if (netif_running(dev)) {
-		netif_tx_lock(dev);
+		netif_tx_lock_bh(dev);
 		netif_device_detach(dev);	/* stop txq */
-		netif_tx_unlock(dev);
+		netif_tx_unlock_bh(dev);
 		sky2_down(dev);
 	}
 }

@@ -4201,7 +4212,7 @@ static int sky2_debug_show(struct seq_fi
 
 	/* Dump contents of tx ring */
 	sop = 1;
-	for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
+	for (idx = sky2->tx_cons; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
 	     idx = RING_NEXT(idx, sky2->tx_ring_size)) {
 		const struct sky2_tx_le *le = sky2->tx_le + idx;
 		u32 a = le32_to_cpu(le->addr);

@@ -2187,7 +2187,6 @@ struct sky2_port {
 	u16		     tx_ring_size;
 	u16		     tx_cons;		/* next le to check */
 	u16		     tx_prod;		/* next le to use */
-	u16		     tx_next;		/* debug only */
 
 	u16		     tx_pending;
 	u16		     tx_last_mss;

@@ -1596,6 +1596,9 @@ static inline int tx_inuse(const struct
  /* Number of list elements available for next tx */
  static inline int tx_avail(const struct sky2_port *sky2)
  {
+	/* Makes sure update of tx_prod from start_xmit and
+	   tx_cons from tx_done are seen. */
+	smp_mb();
  	return sky2->tx_pending - tx_inuse(sky2);
  }
 

@@ -1618,8 +1621,7 @@ static unsigned tx_le_req(const struct s
  	return count;
  }
 
-static void sky2_tx_unmap(struct pci_dev *pdev,
-			  const struct tx_ring_info *re)
+static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
  {
  	if (re->flags&  TX_MAP_SINGLE)
  		pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),

@@ -1629,6 +1631,7 @@ static void sky2_tx_unmap(struct pci_dev
  		pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
  			       pci_unmap_len(re, maplen),
  			       PCI_DMA_TODEVICE);
+	re->flags = 0;
  }
 
  /*

@@ -1804,7 +1807,8 @@ mapping_error:
  }
 
  /*
- * Free ring elements from starting at tx_cons until "done"
+ * Transmit complete processing
+ * Free ring elements from starting at tx_cons until done index
   *
   * NB:
   *  1. The hardware will tell us about partial completion of multi-part

@@ -1813,11 +1817,14 @@ mapping_error:
   *     looks at the tail of the queue of FIFO (tx_cons), not
   *     the head (tx_prod)
   */
-static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
+static void sky2_tx_done(struct net_device *dev, u16 done)
  {
-	struct net_device *dev = sky2->netdev;
+	struct sky2_port *sky2 = netdev_priv(dev);
  	unsigned idx;
 
+	if (unlikely(!netif_running(dev)))
+		return;
+
  	BUG_ON(done>= sky2->tx_ring_size);
 
  	for (idx = sky2->tx_cons; idx != done;

@@ -1828,6 +1835,8 @@ static void sky2_tx_complete(struct sky2
  		sky2_tx_unmap(sky2->hw->pdev, re);
 
  		if (skb) {
+			re->skb = NULL;
+
  			if (unlikely(netif_msg_tx_done(sky2)))
  				printk(KERN_DEBUG "%s: tx done %u\n",
  				       dev->name, idx);

@@ -1836,13 +1845,10 @@ static void sky2_tx_complete(struct sky2
  			dev->stats.tx_bytes += skb->len;
 
  			dev_kfree_skb_any(skb);
-
-			sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
  		}
  	}
 
  	sky2->tx_cons = idx;
-	smp_mb();
 
  	if (tx_avail(sky2)>  MAX_SKB_TX_LE + 4)
  		netif_wake_queue(dev);

@@ -1870,6 +1876,21 @@ static void sky2_tx_reset(struct sky2_hw
  	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
  }
 
+static void sky2_tx_clean(struct sky2_port *sky2)
+{
+	u16 idx;
+
+	for (idx = 0; idx<  sky2->tx_ring_size; idx++) {
+		struct tx_ring_info *re = sky2->tx_ring + idx;
+
+		sky2_tx_unmap(sky2->hw->pdev, re);
+		if (re->skb) {
+			dev_kfree_skb_any(re->skb);
+			re->skb = NULL;
+		}
+	}
+}
+
  /* Network shutdown */
  static int sky2_down(struct net_device *dev)
  {

@@ -1933,8 +1954,7 @@ static int sky2_down(struct net_device *
  	sky2_tx_reset(hw, port);
 
  	/* Free any pending frames stuck in HW queue */
-	sky2_tx_complete(sky2, sky2->tx_prod);
-
+	sky2_tx_clean(sky2);
  	sky2_rx_clean(sky2);
 
  	sky2_free_buffers(sky2);

@@ -2411,15 +2431,6 @@ error:
  	goto resubmit;
  }
 
-/* Transmit complete */
-static inline void sky2_tx_done(struct net_device *dev, u16 last)
-{
-	struct sky2_port *sky2 = netdev_priv(dev);
-
-	if (netif_running(dev))
-		sky2_tx_complete(sky2, last);
-}
-
  static inline void sky2_skb_rx(const struct sky2_port *sky2,
  			       u32 status, struct sk_buff *skb)
  {

@@ -3176,9 +3187,9 @@ static void sky2_reset(struct sky2_hw *h
  static void sky2_detach(struct net_device *dev)
  {
  	if (netif_running(dev)) {
-		netif_tx_lock(dev);
+		netif_tx_lock_bh(dev);
  		netif_device_detach(dev);	/* stop txq */
-		netif_tx_unlock(dev);
+		netif_tx_unlock_bh(dev);
  		sky2_down(dev);
  	}
  }

@@ -4201,7 +4212,7 @@ static int sky2_debug_show(struct seq_fi
 
  	/* Dump contents of tx ring */
  	sop = 1;
-	for (idx = sky2->tx_next; idx != sky2->tx_prod&&  idx<  sky2->tx_ring_size;
+	for (idx = sky2->tx_cons; idx != sky2->tx_prod&&  idx<  sky2->tx_ring_size;
  	     idx = RING_NEXT(idx, sky2->tx_ring_size)) {
  		const struct sky2_tx_le *le = sky2->tx_le + idx;
  		u32 a = le32_to_cpu(le->addr);

@@ -2187,7 +2187,6 @@ struct sky2_port {
  	u16		     tx_ring_size;
  	u16		     tx_cons;		/* next le to check */
  	u16		     tx_prod;		/* next le to use */
-	u16		     tx_next;		/* debug only */
 
  	u16		     tx_pending;
  	u16		     tx_last_mss;

@@ -1596,6 +1596,9 @@ static inline int tx_inuse(const struct 
 /* Number of list elements available for next tx */
 static inline int tx_avail(const struct sky2_port *sky2)
 {
+	/* Makes sure update of tx_prod from start_xmit and
+	   tx_cons from tx_done are seen. */
+	smp_mb();
 	return sky2->tx_pending - tx_inuse(sky2);
 }
 

@@ -1618,8 +1621,7 @@ static unsigned tx_le_req(const struct s
 	return count;
 }
 
-static void sky2_tx_unmap(struct pci_dev *pdev,
-			  const struct tx_ring_info *re)
+static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
 {
 	if (re->flags & TX_MAP_SINGLE)
 		pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),

@@ -1629,6 +1631,7 @@ static void sky2_tx_unmap(struct pci_dev
 		pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
 			       pci_unmap_len(re, maplen),
 			       PCI_DMA_TODEVICE);
+	re->flags = 0;
 }
 
 /*

@@ -1804,7 +1807,8 @@ mapping_error:
 }
 
 /*
- * Free ring elements from starting at tx_cons until "done"
+ * Transmit complete processing
+ * Free ring elements from starting at tx_cons until done index
  *
  * NB:
  *  1. The hardware will tell us about partial completion of multi-part

@@ -1813,11 +1817,14 @@ mapping_error:
  *     looks at the tail of the queue of FIFO (tx_cons), not
  *     the head (tx_prod)
  */
-static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
+static void sky2_tx_done(struct net_device *dev, u16 done)
 {
-	struct net_device *dev = sky2->netdev;
+	struct sky2_port *sky2 = netdev_priv(dev);
 	unsigned idx;
 
+	if (!(netif_running(dev) & netif_device_present(dev)))
+		return;
+
 	BUG_ON(done >= sky2->tx_ring_size);
 
 	for (idx = sky2->tx_cons; idx != done;

@@ -1828,6 +1835,8 @@ static void sky2_tx_complete(struct sky2
 		sky2_tx_unmap(sky2->hw->pdev, re);
 
 		if (skb) {
+			re->skb = NULL;
+
 			if (unlikely(netif_msg_tx_done(sky2)))
 				printk(KERN_DEBUG "%s: tx done %u\n",
 				       dev->name, idx);

@@ -1836,16 +1845,12 @@ static void sky2_tx_complete(struct sky2
 			dev->stats.tx_bytes += skb->len;
 
 			dev_kfree_skb_any(skb);
-
-			sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
 		}
 	}
 
 	sky2->tx_cons = idx;
-	smp_mb();
 
-	/* Wake unless it's detached, and called e.g. from sky2_down() */
-	if (tx_avail(sky2) > MAX_SKB_TX_LE + 4 && netif_device_present(dev))
+	if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
 		netif_wake_queue(dev);
 }
 

@@ -1871,6 +1876,21 @@ static void sky2_tx_reset(struct sky2_hw
 	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
 }
 
+static void sky2_tx_clean(struct sky2_port *sky2)
+{
+	u16 idx;
+
+	for (idx = 0; idx < sky2->tx_ring_size; idx++) {
+		struct tx_ring_info *re = sky2->tx_ring + idx;
+
+		sky2_tx_unmap(sky2->hw->pdev, re);
+		if (re->skb) {
+			dev_kfree_skb_any(re->skb);
+			re->skb = NULL;
+		}
+	}
+}
+
 /* Network shutdown */
 static int sky2_down(struct net_device *dev)
 {

@@ -1934,8 +1954,7 @@ static int sky2_down(struct net_device *
 	sky2_tx_reset(hw, port);
 
 	/* Free any pending frames stuck in HW queue */
-	sky2_tx_complete(sky2, sky2->tx_prod);
-
+	sky2_tx_clean(sky2);
 	sky2_rx_clean(sky2);
 
 	sky2_free_buffers(sky2);

@@ -2412,15 +2431,6 @@ error:
 	goto resubmit;
 }
 
-/* Transmit complete */
-static inline void sky2_tx_done(struct net_device *dev, u16 last)
-{
-	struct sky2_port *sky2 = netdev_priv(dev);
-
-	if (netif_running(dev))
-		sky2_tx_complete(sky2, last);
-}
-
 static inline void sky2_skb_rx(const struct sky2_port *sky2,
 			       u32 status, struct sk_buff *skb)
 {

@@ -3177,9 +3187,9 @@ static void sky2_reset(struct sky2_hw *h
 static void sky2_detach(struct net_device *dev)
 {
 	if (netif_running(dev)) {
-		netif_tx_lock(dev);
+		netif_tx_lock_bh(dev);
 		netif_device_detach(dev);	/* stop txq */
-		netif_tx_unlock(dev);
+		netif_tx_unlock_bh(dev);
 		sky2_down(dev);
 	}
 }

@@ -4202,7 +4212,7 @@ static int sky2_debug_show(struct seq_fi
 
 	/* Dump contents of tx ring */
 	sop = 1;
-	for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
+	for (idx = sky2->tx_cons; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
 	     idx = RING_NEXT(idx, sky2->tx_ring_size)) {
 		const struct sky2_tx_le *le = sky2->tx_le + idx;
 		u32 a = le32_to_cpu(le->addr);

@@ -2187,7 +2187,6 @@ struct sky2_port {
 	u16		     tx_ring_size;
 	u16		     tx_cons;		/* next le to check */
 	u16		     tx_prod;		/* next le to use */
-	u16		     tx_next;		/* debug only */
 
 	u16		     tx_pending;
 	u16		     tx_last_mss;

@@ -1596,6 +1596,9 @@ static inline int tx_inuse(const struct 
 /* Number of list elements available for next tx */
 static inline int tx_avail(const struct sky2_port *sky2)
 {
+	/* Makes sure update of tx_prod from start_xmit and
+	   tx_cons from tx_done are seen. */
+	smp_mb();
 	return sky2->tx_pending - tx_inuse(sky2);
 }
 

@@ -1618,8 +1621,7 @@ static unsigned tx_le_req(const struct s
 	return count;
 }
 
-static void sky2_tx_unmap(struct pci_dev *pdev,
-			  const struct tx_ring_info *re)
+static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
 {
 	if (re->flags & TX_MAP_SINGLE)
 		pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),

@@ -1629,6 +1631,7 @@ static void sky2_tx_unmap(struct pci_dev
 		pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
 			       pci_unmap_len(re, maplen),
 			       PCI_DMA_TODEVICE);
+	re->flags = 0;
 }
 
 /*

@@ -1804,7 +1807,8 @@ mapping_error:
 }
 
 /*
- * Free ring elements from starting at tx_cons until "done"
+ * Transmit complete processing
+ * Free ring elements from starting at tx_cons until done index
  *
  * NB:
  *  1. The hardware will tell us about partial completion of multi-part

@@ -1813,11 +1817,14 @@ mapping_error:
  *     looks at the tail of the queue of FIFO (tx_cons), not

  *     the head (tx_prod)
  */
-static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
+static void sky2_tx_done(struct net_device *dev, u16 done)
 {
-	struct net_device *dev = sky2->netdev;
+	struct sky2_port *sky2 = netdev_priv(dev);
 	unsigned idx;
 
+	if (!(netif_running(dev) & netif_device_present(dev)))

+		return;
+
 	BUG_ON(done >= sky2->tx_ring_size);
 
 	for (idx = sky2->tx_cons; idx != done;

@@ -1828,6 +1835,8 @@ static void sky2_tx_complete(struct sky2
 		sky2_tx_unmap(sky2->hw->pdev, re);
 
 		if (skb) {
+			re->skb = NULL;
+
 			if (unlikely(netif_msg_tx_done(sky2)))
 				printk(KERN_DEBUG "%s: tx done %u\n",
 				       dev->name, idx);

@@ -1836,16 +1845,12 @@ static void sky2_tx_complete(struct sky2
 			dev->stats.tx_bytes += skb->len;
 
 			dev_kfree_skb_any(skb);
-
-			sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
 		}
 	}
 
 	sky2->tx_cons = idx;
-	smp_mb();
 
-	/* Wake unless it's detached, and called e.g. from sky2_down() */
-	if (tx_avail(sky2) > MAX_SKB_TX_LE + 4 && netif_device_present(dev))
+	if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
 		netif_wake_queue(dev);
 }
 

@@ -1871,6 +1876,21 @@ static void sky2_tx_reset(struct sky2_hw
 	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
 }
 
+static void sky2_tx_clean(struct sky2_port *sky2)
+{
+	u16 idx;
+
+	for (idx = 0; idx < sky2->tx_ring_size; idx++) {
+		struct tx_ring_info *re = sky2->tx_ring + idx;
+
+		sky2_tx_unmap(sky2->hw->pdev, re);
+		if (re->skb) {
+			dev_kfree_skb_any(re->skb);
+			re->skb = NULL;
+		}
+	}
+}
+
 /* Network shutdown */
 static int sky2_down(struct net_device *dev)
 {

@@ -1934,8 +1954,7 @@ static int sky2_down(struct net_device *
 	sky2_tx_reset(hw, port);
 
 	/* Free any pending frames stuck in HW queue */
-	sky2_tx_complete(sky2, sky2->tx_prod);
-
+	sky2_tx_clean(sky2);
 	sky2_rx_clean(sky2);
 
 	sky2_free_buffers(sky2);

@@ -2412,15 +2431,6 @@ error:
 	goto resubmit;
 }
 
-/* Transmit complete */
-static inline void sky2_tx_done(struct net_device *dev, u16 last)
-{
-	struct sky2_port *sky2 = netdev_priv(dev);
-
-	if (netif_running(dev))
-		sky2_tx_complete(sky2, last);
-}
-
 static inline void sky2_skb_rx(const struct sky2_port *sky2,
 			       u32 status, struct sk_buff *skb)
 {

@@ -3177,9 +3187,9 @@ static void sky2_reset(struct sky2_hw *h
 static void sky2_detach(struct net_device *dev)
 {
 	if (netif_running(dev)) {
-		netif_tx_lock(dev);
+		netif_tx_lock_bh(dev);
 		netif_device_detach(dev);	/* stop txq */
-		netif_tx_unlock(dev);
+		netif_tx_unlock_bh(dev);
 		sky2_down(dev);
 	}
 }

@@ -4202,7 +4212,7 @@ static int sky2_debug_show(struct seq_fi
 
 	/* Dump contents of tx ring */
 	sop = 1;
-	for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
+	for (idx = sky2->tx_cons; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
 	     idx = RING_NEXT(idx, sky2->tx_ring_size)) {
 		const struct sky2_tx_le *le = sky2->tx_le + idx;
 		u32 a = le32_to_cpu(le->addr);

@@ -2187,7 +2187,6 @@ struct sky2_port {
 	u16		     tx_ring_size;
 	u16		     tx_cons;		/* next le to check */
 	u16		     tx_prod;		/* next le to use */
-	u16		     tx_next;		/* debug only */
 
 	u16		     tx_pending;
 	u16		     tx_last_mss;

+	if (!(netif_running(dev) & netif_device_present(dev)))

---
 drivers/net/sky2.c |   13 +++++++++----
 1 files changed, 9 insertions(+), 4 deletions(-)
index d76d907..061f6f2 100644
@@ -1580,6 +1580,8 @@ static int sky2_up(struct net_device *dev)
 	if (netif_msg_ifup(sky2))
 		printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
 
+	netif_start_queue(dev);
+
 	return 0;
 
 err_out:

@@ -1596,6 +1598,8 @@ static inline int tx_inuse(const struct sky2_port *sky2)
 /* Number of list elements available for next tx */
 static inline int tx_avail(const struct sky2_port *sky2)
 {
+	if (unlikely(!sky2->tx_ring))
+		return 0;
 	return sky2->tx_pending - tx_inuse(sky2);
 }
 

@@ -1925,7 +1929,9 @@ static int sky2_down(struct net_device *dev)
 	sky2_read32(hw, B0_IMSK);
 
 	synchronize_irq(hw->pdev->irq);
-	napi_synchronize(&hw->napi);
+	netif_tx_lock_bh(dev);
+	napi_disable(&hw->napi);
+	netif_stop_queue(dev);
 
 	spin_lock_bh(&sky2->phy_lock);
 	sky2_phy_power_down(hw, port);

@@ -1939,6 +1945,8 @@ static int sky2_down(struct net_device *dev)
 	sky2_rx_clean(sky2);
 
 	sky2_free_buffers(sky2);
+	napi_enable(&hw->napi);
+	netif_tx_unlock_bh(dev);
 
 	return 0;
 }

@@ -3177,9 +3185,6 @@ static void sky2_reset(struct sky2_hw *hw)
 static void sky2_detach(struct net_device *dev)
 {
 	if (netif_running(dev)) {
-		netif_tx_lock_bh(dev);
-		netif_device_detach(dev);	/* stop txq */
-		netif_tx_unlock_bh(dev);
 		sky2_down(dev);
 	}
 }

@@ -1596,6 +1598,8 @@ static inline int tx_inuse(const struct sky2_port *sky2)
  /* Number of list elements available for next tx */
  static inline int tx_avail(const struct sky2_port *sky2)
  {
+	if (unlikely(!sky2->tx_ring))
+		return 0;
  	return sky2->tx_pending - tx_inuse(sky2);
  }
 

---
  drivers/net/sky2.c |   13 +++++++++----
  1 files changed, 9 insertions(+), 4 deletions(-)
index d76d907..061f6f2 100644
@@ -1580,6 +1580,8 @@ static int sky2_up(struct net_device *dev)
  	if (netif_msg_ifup(sky2))
  		printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
 
+	netif_start_queue(dev);
+
  	return 0;
 
  err_out:

@@ -1596,6 +1598,8 @@ static inline int tx_inuse(const struct sky2_port *sky2)
  /* Number of list elements available for next tx */
  static inline int tx_avail(const struct sky2_port *sky2)
  {
+	if (unlikely(!sky2->tx_ring))
+		return 0;
  	return sky2->tx_pending - tx_inuse(sky2);
  }
 

@@ -1925,7 +1929,9 @@ static int sky2_down(struct net_device *dev)
  	sky2_read32(hw, B0_IMSK);
 
  	synchronize_irq(hw->pdev->irq);
-	napi_synchronize(&hw->napi);
+	netif_tx_lock_bh(dev);
+	napi_disable(&hw->napi);
+	netif_stop_queue(dev);
 
  	spin_lock_bh(&sky2->phy_lock);
  	sky2_phy_power_down(hw, port);

@@ -1939,6 +1945,8 @@ static int sky2_down(struct net_device *dev)
  	sky2_rx_clean(sky2);
 
  	sky2_free_buffers(sky2);
+	napi_enable(&hw->napi);
+	netif_tx_unlock_bh(dev);
 
  	return 0;
  }

@@ -3177,9 +3185,6 @@ static void sky2_reset(struct sky2_hw *hw)
  static void sky2_detach(struct net_device *dev)
  {
  	if (netif_running(dev)) {
-		netif_tx_lock_bh(dev);
-		netif_device_detach(dev);	/* stop txq */
-		netif_tx_unlock_bh(dev);
  		sky2_down(dev);
  	}
  }
-- 1.5.6.5

+	if (unlikely(!sky2->tx_ring))
+		return 0;
 	return sky2->tx_pending - tx_inuse(sky2);
 }

@@ -1925,7 +1929,9 @@ static int sky2_down(struct net_device *dev)
 	sky2_read32(hw, B0_IMSK);
 
 	synchronize_irq(hw->pdev->irq);
-	napi_synchronize(&hw->napi);
+	netif_tx_lock_bh(dev);
+	napi_disable(&hw->napi);
+	netif_stop_queue(dev);
 
 	spin_lock_bh(&sky2->phy_lock);
 	sky2_phy_power_down(hw, port);

@@ -1939,6 +1945,8 @@ static int sky2_down(struct net_device *dev)
 	sky2_rx_clean(sky2);
 
 	sky2_free_buffers(sky2);
+	napi_enable(&hw->napi);
+	netif_tx_unlock_bh(dev);
 
 	return 0;

@@ -1596,6 +1596,9 @@ static inline int tx_inuse(const struct
  /* Number of list elements available for next tx */
  static inline int tx_avail(const struct sky2_port *sky2)
  {
+	/* Makes sure update of tx_prod from start_xmit and
+	   tx_cons from tx_done are seen. */
+	smp_mb();
  	return sky2->tx_pending - tx_inuse(sky2);
  }
 

@@ -1618,8 +1621,7 @@ static unsigned tx_le_req(const struct s
  	return count;
  }
 
-static void sky2_tx_unmap(struct pci_dev *pdev,
-			  const struct tx_ring_info *re)
+static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
  {
  	if (re->flags&  TX_MAP_SINGLE)
  		pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),

@@ -1629,6 +1631,7 @@ static void sky2_tx_unmap(struct pci_dev
  		pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
  			       pci_unmap_len(re, maplen),
  			       PCI_DMA_TODEVICE);
+	re->flags = 0;
  }
 
  /*

@@ -1804,7 +1807,8 @@ mapping_error:
  }
 
  /*
- * Free ring elements from starting at tx_cons until "done"
+ * Transmit complete processing
+ * Free ring elements from starting at tx_cons until done index
   *
   * NB:
   *  1. The hardware will tell us about partial completion of multi-part

@@ -1813,11 +1817,14 @@ mapping_error:
   *     looks at the tail of the queue of FIFO (tx_cons), not
   *     the head (tx_prod)
   */
-static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
+static void sky2_tx_done(struct net_device *dev, u16 done)
  {
-	struct net_device *dev = sky2->netdev;
+	struct sky2_port *sky2 = netdev_priv(dev);
  	unsigned idx;
 
+	if (!(netif_running(dev)&  netif_device_present(dev)))
+		return;
+
  	BUG_ON(done>= sky2->tx_ring_size);
 
  	for (idx = sky2->tx_cons; idx != done;

@@ -1828,6 +1835,8 @@ static void sky2_tx_complete(struct sky2
  		sky2_tx_unmap(sky2->hw->pdev, re);
 
  		if (skb) {
+			re->skb = NULL;
+
  			if (unlikely(netif_msg_tx_done(sky2)))
  				printk(KERN_DEBUG "%s: tx done %u\n",
  				       dev->name, idx);

@@ -1836,16 +1845,12 @@ static void sky2_tx_complete(struct sky2
  			dev->stats.tx_bytes += skb->len;
 
  			dev_kfree_skb_any(skb);
-
-			sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
  		}
  	}
 
  	sky2->tx_cons = idx;
-	smp_mb();
 
-	/* Wake unless it's detached, and called e.g. from sky2_down() */
-	if (tx_avail(sky2)>  MAX_SKB_TX_LE + 4&&  netif_device_present(dev))
+	if (tx_avail(sky2)>  MAX_SKB_TX_LE + 4)
  		netif_wake_queue(dev);
  }
 

@@ -1871,6 +1876,21 @@ static void sky2_tx_reset(struct sky2_hw
  	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
  }
 
+static void sky2_tx_clean(struct sky2_port *sky2)
+{
+	u16 idx;
+
+	for (idx = 0; idx<  sky2->tx_ring_size; idx++) {
+		struct tx_ring_info *re = sky2->tx_ring + idx;
+
+		sky2_tx_unmap(sky2->hw->pdev, re);
+		if (re->skb) {
+			dev_kfree_skb_any(re->skb);
+			re->skb = NULL;
+		}
+	}
+}
+
  /* Network shutdown */
  static int sky2_down(struct net_device *dev)
  {

@@ -1934,8 +1954,7 @@ static int sky2_down(struct net_device *
  	sky2_tx_reset(hw, port);
 
  	/* Free any pending frames stuck in HW queue */
-	sky2_tx_complete(sky2, sky2->tx_prod);
-
+	sky2_tx_clean(sky2);
  	sky2_rx_clean(sky2);
 
  	sky2_free_buffers(sky2);

@@ -2412,15 +2431,6 @@ error:
  	goto resubmit;
  }
 
-/* Transmit complete */
-static inline void sky2_tx_done(struct net_device *dev, u16 last)
-{
-	struct sky2_port *sky2 = netdev_priv(dev);
-
-	if (netif_running(dev))
-		sky2_tx_complete(sky2, last);
-}
-
  static inline void sky2_skb_rx(const struct sky2_port *sky2,
  			       u32 status, struct sk_buff *skb)
  {

@@ -3177,9 +3187,9 @@ static void sky2_reset(struct sky2_hw *h
  static void sky2_detach(struct net_device *dev)
  {
  	if (netif_running(dev)) {
-		netif_tx_lock(dev);
+		netif_tx_lock_bh(dev);
  		netif_device_detach(dev);	/* stop txq */
-		netif_tx_unlock(dev);
+		netif_tx_unlock_bh(dev);
  		sky2_down(dev);
  	}
  }

@@ -4202,7 +4212,7 @@ static int sky2_debug_show(struct seq_fi
 
  	/* Dump contents of tx ring */
  	sop = 1;
-	for (idx = sky2->tx_next; idx != sky2->tx_prod&&  idx<  sky2->tx_ring_size;
+	for (idx = sky2->tx_cons; idx != sky2->tx_prod&&  idx<  sky2->tx_ring_size;
  	     idx = RING_NEXT(idx, sky2->tx_ring_size)) {
  		const struct sky2_tx_le *le = sky2->tx_le + idx;
  		u32 a = le32_to_cpu(le->addr);

@@ -2187,7 +2187,6 @@ struct sky2_port {
  	u16		     tx_ring_size;
  	u16		     tx_cons;		/* next le to check */
  	u16		     tx_prod;		/* next le to use */
-	u16		     tx_next;		/* debug only */
 
  	u16		     tx_pending;
  	u16		     tx_last_mss;

@@ -1843,9 +1843,6 @@ static void sky2_tx_complete(struct sky2
 
 	sky2->tx_cons = idx;
 	smp_mb();
-
-	if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
-		netif_wake_queue(dev);
 }
 
 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)

@@ -2416,8 +2413,12 @@ static inline void sky2_tx_done(struct n
 {
 	struct sky2_port *sky2 = netdev_priv(dev);
 
-	if (netif_running(dev))
+	if (netif_running(dev) && netif_device_present(dev)) {
 		sky2_tx_complete(sky2, last);
+
+		if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
+			netif_wake_queue(dev);
+	}
 }
 
 static inline void sky2_skb_rx(const struct sky2_port *sky2,

@@ -3197,6 +3198,7 @@ static int sky2_reattach(struct net_devi
 		} else {
 			netif_device_attach(dev);
 			sky2_set_multicast(dev);
+			netif_start_queue(dev);

Regards/Gruss,
    Boris.
Regards/Gruss,
    Boris.
  "One disk to rule them all, One disk to find them. One disk to bring
  them all and in the darkness grind them. In the Land of Redmond
  where the shadows lie." -- The Silicon Valley Tarot
  Henrique Holschuh
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
Sid Boyce ... Hamradio License G3VBV, Licensed Private Pilot
Emeritus IBM/Amdahl Mainframes and Sun/Fujitsu Servers Tech Support
Specialist, Cricket Coach
Microsoft Windows Free Zone - Linux used for all Computing Tasks
Sid Boyce ... Hamradio License G3VBV, Licensed Private Pilot
Emeritus IBM/Amdahl Mainframes and Sun/Fujitsu Servers Tech Support
Specialist, Cricket Coach
Microsoft Windows Free Zone - Linux used for all Computing Tasks
Sid Boyce ... Hamradio License G3VBV, Licensed Private Pilot
Emeritus IBM/Amdahl Mainframes and Sun/Fujitsu Servers Tech Support
Specialist, Cricket Coach
Microsoft Windows Free Zone - Linux used for all Computing Tasks
Sid Boyce ... Hamradio License G3VBV, Licensed Private Pilot
Emeritus IBM/Amdahl Mainframes and Sun/Fujitsu Servers Tech Support
Specialist, Cricket Coach
Microsoft Windows Free Zone - Linux used for all Computing Tasks
Sid Boyce ... Hamradio License G3VBV, Licensed Private Pilot
Emeritus IBM/Amdahl Mainframes and Sun/Fujitsu Servers Tech Support
Specialist, Cricket Coach
Microsoft Windows Free Zone - Linux used for all Computing Tasks
       HDA Intel: /devices/pci0000:00/0000:00:0e.1
       HDA Intel: /devices/pci0000:00/0000:00:0e.1
       HDA Intel: /devices/pci0000:00/0000:00:0e.1
Sid Boyce ... Hamradio License G3VBV, Licensed Private Pilot
Emeritus IBM/Amdahl Mainframes and Sun/Fujitsu Servers Tech Support
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Microsoft Windows Free Zone - Linux used for all Computing Tasks
       HDA Intel: /devices/pci0000:00/0000:00:0e.1
       HDA Intel: /devices/pci0000:00/0000:00:0e.1
Sid Boyce ... Hamradio License G3VBV, Licensed Private Pilot
Emeritus IBM/Amdahl Mainframes and Sun/Fujitsu Servers Tech Support
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Microsoft Windows Free Zone - Linux used for all Computing Tasks
snd_pcm_oss            40102  0
snd_mixer_oss          14822  1 snd_pcm_oss
snd_seq                52843  0
snd_hda_codec_analog    73538  1
snd_hda_intel          23660  0
snd_hda_codec          75402  2 snd_hda_codec_analog,snd_hda_intel
snd_usb_audio          85288  0
snd_usb_lib            16705  1 snd_usb_audio
snd_rawmidi            21568  1 snd_usb_lib
snd_pcm                81892  4
snd_pcm_oss,snd_hda_intel,snd_hda_codec,snd_usb_audio
snd_seq_device          6514  2 snd_seq,snd_rawmidi
snd_hwdep               6346  2 snd_hda_codec,snd_usb_audio
snd_timer              20760  2 snd_seq,snd_pcm
snd                    66395  13
snd_pcm_oss,snd_mixer_oss,snd_seq,snd_hda_codec_analog,snd_hda_intel,snd_hda_codec,snd_usb_audio,snd_usb_lib,snd_rawmidi,snd_pcm,snd_seq_device,snd_hwdep,snd_timer
snd_page_alloc          7873  2 snd_hda_intel,snd_pcm
soundcore               7147  1 snd
usbcore               146206  6
Sid Boyce ... Hamradio License G3VBV, Licensed Private Pilot
Emeritus IBM/Amdahl Mainframes and Sun/Fujitsu Servers Tech Support
Specialist, Cricket Coach
Microsoft Windows Free Zone - Linux used for all Computing Tasks
       HDA Intel: /devices/pci0000:00/0000:00:0e.1
Sid Boyce ... Hamradio License G3VBV, Licensed Private Pilot
Emeritus IBM/Amdahl Mainframes and Sun/Fujitsu Servers Tech Support
Specialist, Cricket Coach
Microsoft Windows Free Zone - Linux used for all Computing Tasks
       HDA Intel: /devices/pci0000:00/0000:00:0e.1
       HDA Intel: /devices/pci0000:00/0000:00:0e.1
Sid Boyce ... Hamradio License G3VBV, Licensed Private Pilot
Emeritus IBM/Amdahl Mainframes and Sun/Fujitsu Servers Tech Support
Specialist, Cricket Coach
Microsoft Windows Free Zone - Linux used for all Computing Tasks
       HDA Intel: /devices/pci0000:00/0000:00:0e.1
Sid Boyce ... Hamradio License G3VBV, Licensed Private Pilot
Emeritus IBM/Amdahl Mainframes and Sun/Fujitsu Servers Tech Support
Specialist, Cricket Coach
Microsoft Windows Free Zone - Linux used for all Computing Tasks
Sid Boyce ... Hamradio License G3VBV, Licensed Private Pilot
Emeritus IBM/Amdahl Mainframes and Sun/Fujitsu Servers Tech Support
Specialist, Cricket Coach
Microsoft Windows Free Zone - Linux used for all Computing Tasks
Sid Boyce ... Hamradio License G3VBV, Licensed Private Pilot
Emeritus IBM/Amdahl Mainframes and Sun/Fujitsu Servers Tech Support
Specialist, Cricket Coach
Microsoft Windows Free Zone - Linux used for all Computing Tasks
Manufacturer:      System manufacturer
Product Name:      System Product Name
Kernel release:    2.6.33-rc5-git2-smp
Operating System:  GNU/Linux
Architecture:      x86_64
Processor:         x86_64
SMP Enabled:       Yes
Driver version:     1.0.21
Library version:    1.0.22
Utilities version:  1.0.22
                      HDA NVidia at 0xfe020000 irq 30
 1 [EMU0404        ]: Audigy2 - E-mu 0404b PCI [MAEM8852]
                      E-mu 0404b PCI [MAEM8852] (rev.0, serial:0x40021102) at 0xec00, irq 16
 2 [USB            ]: USB-Audio - E-MU 0404 | USB
                      E-MU Systems, Inc. E-MU 0404 | USB at usb-0000:00:04.1-1.3, high speed
	Subsystem: 1043:829c
--
01:08.0 0401: 1102:0008
	Subsystem: 1102:4002
	bdl_pos_adj : 32,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1
	beep_mode : 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1
	enable : Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y
	enable_msi : -1
	id : (null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null)
	index : -1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1
	model : (null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null)
	patch : (null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null)
	position_fix : 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
	power_save : 0
	power_save_controller : Y
	probe_mask : -1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1
	probe_only : N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N
	single_cmd : N
	enable : Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y
	enable_ir : N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N,N
	extin : 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
	extout : 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
	id : (null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null)
	index : -1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1
	max_buffer_size : 128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128
	max_synth_voices : 64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64
	seq_ports : 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4
	subsystem : 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
	async_unlink : Y
	device_setup : 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
	enable : Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y
	id : (null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null),(null)
	ignore_ctl_error : N
	index : -1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1
	nrpacks : 8
	pid : -1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1
	vid : -1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1
    rates [0x7ff]: 8000 11025 16000 22050 32000 44100 48000 88200 96000 176400 192000
    bits [0xe]: 16 20 24
    formats [0x1]: PCM
    rates [0x7e0]: 44100 48000 88200 96000 176400 192000
    bits [0xe]: 16 20 24
    formats [0x5]: PCM AC3
  Delay: 3 samples
  Connection: 1
     0x1d
    rates [0x7e0]: 44100 48000 88200 96000 176400 192000
    bits [0xe]: 16 20 24
    formats [0x5]: PCM AC3
  Unsolicited: tag=00, enabled=0
  Delay: 3 samples
  Connection: 1
     0x1c
     0x0c
     0x0d
     0x08* 0x09 0x0f
     0x38 0x39* 0x3a 0x3b 0x3c 0x18 0x24 0x25 0x3d 0x20
     0x38 0x39* 0x3a 0x3b 0x3c 0x18 0x24 0x25 0x3d 0x20
     0x38 0x39* 0x3a 0x3b 0x3c 0x18 0x24 0x25 0x3d 0x20
     0x0e
    Vref caps: HIZ 50 GRD 80 100
  Pin Default 0x02214030: [Jack] HP Out at Ext Front
    Conn = 1/8, Color = Green
    DefAssociation = 0x3, Sequence = 0x0
  Pin-ctls: 0xc0: OUT HP VREF_HIZ
  Unsolicited: tag=00, enabled=0
  Connection: 1
     0x22
    Vref caps: HIZ 50 GRD 80 100
  Pin Default 0x01014010: [Jack] Line Out at Ext Rear
    Conn = 1/8, Color = Green
    DefAssociation = 0x1, Sequence = 0x0
  Pin-ctls: 0x40: OUT VREF_HIZ
  Unsolicited: tag=00, enabled=0
  Connection: 1
     0x29
     0x2d
    Vref caps: HIZ 50 GRD 80 100
  Pin Default 0x02a1902e: [Jack] Mic at Ext Front
    Conn = 1/8, Color = Pink
    DefAssociation = 0x2, Sequence = 0xe
  Pin-ctls: 0x24: IN VREF_80
  Unsolicited: tag=00, enabled=0
  Connection: 1
     0x2b
    Vref caps: HIZ 50 GRD 80 100
  Pin Default 0x01813021: [Jack] Line In at Ext Rear
    Conn = 1/8, Color = Blue
    DefAssociation = 0x2, Sequence = 0x1
  Pin-ctls: 0x20: IN VREF_HIZ
  Unsolicited: tag=00, enabled=0
  Connection: 1
     0x2c
    Vref caps: HIZ 50 GRD 80 100
  Pin Default 0x01011012: [Jack] Line Out at Ext Rear
    Conn = 1/8, Color = Black
    DefAssociation = 0x1, Sequence = 0x2
  Pin-ctls: 0x40: OUT VREF_HIZ
  Unsolicited: tag=00, enabled=0
  Connection: 1
     0x2a
    Vref caps: HIZ 50 GRD 80 100
  Pin Default 0x01a19020: [Jack] Mic at Ext Rear
    Conn = 1/8, Color = Pink
    DefAssociation = 0x2, Sequence = 0x0
  Pin-ctls: 0x24: IN VREF_80
  Unsolicited: tag=00, enabled=0
  Connection: 1
     0x26
     0x20 0x21
     0x02
     0x01 0x0b
     0x36 0x21
     0x39 0x33 0x38 0x3d 0x34 0x3b 0x18 0x1a
     0x20
     0x37 0x21
Node 0x23 [Vendor Defined Widget] wcaps 0xf00100: Mono
  Connection: 18
     0x11* 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x24 0x25 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x20 0x21
     0x27
     0x28
     0x32 0x21
     0x05 0x21
     0x0a 0x21
     0x04 0x21
     0x06 0x21
     0x30 0x21
     0x31 0x21
Node 0x2d [Audio Mixer] wcaps 0x200100: Mono
  Connection: 1
     0x1e
Node 0x2e [Vendor Defined Widget] wcaps 0xf00000: Mono
Node 0x2f [Vendor Defined Widget] wcaps 0xf00100: Mono
  Connection: 6
     0x11* 0x12 0x14 0x15 0x16 0x17
Node 0x30 [Audio Selector] wcaps 0x300101: Stereo
  Connection: 3
     0x03* 0x04 0x06
Node 0x31 [Audio Selector] wcaps 0x300101: Stereo
  Connection: 2
     0x04* 0x0a
Node 0x32 [Audio Selector] wcaps 0x300101: Stereo
  Connection: 2
     0x05* 0x04
Node 0x33 [Audio Selector] wcaps 0x300101: Stereo
  Connection: 3
     0x3a* 0x25 0x24
Node 0x34 [Audio Selector] wcaps 0x300101: Stereo
  Connection: 3
     0x3c* 0x25 0x24
Node 0x35 [Vendor Defined Widget] wcaps 0xf00000: Mono
Node 0x36 [Audio Selector] wcaps 0x300101: Stereo
  Connection: 3
     0x03 0x04* 0x06
Node 0x37 [Audio Selector] wcaps 0x300101: Stereo
  Connection: 3
     0x03 0x04* 0x06
     0x11
     0x14
     0x15
     0x16
     0x17
     0x12
    rates [0x0]:
    bits [0x0]:
    formats [0x0]:
    rates [0xc0]: 48000 88200
    bits [0xf]: 8 16 20 24
    formats [0x1]: PCM
     0x04
    rates [0xc0]: 48000 88200
    bits [0xf]: 8 16 20 24
    formats [0x1]: PCM
     0x06
    rates [0xc0]: 48000 88200
    bits [0xf]: 8 16 20 24
    formats [0x1]: PCM
     0x08
    rates [0xc0]: 48000 88200
    bits [0xf]: 8 16 20 24
    formats [0x1]: PCM
     0x0a
    rates [0xc0]: 48000 88200
    bits [0xf]: 8 16 20 24
    formats [0x1]: PCM
     0x0c
crw-rw----+ 1 root audio 116,  6 Jan 27 11:06 /dev/snd/pcmC2D0c
crw-rw----+ 1 root audio 116,  5 Jan 27 11:06 /dev/snd/pcmC2D0p
crw-rw----+ 1 root audio 116,  4 Jan 27 10:34 /dev/snd/pcmC2D1p
lrwxrwxrwx 1 root root  12 Jan 27 10:34 pci-0000:00:04.1-usb-0:1.3:1.0 -> ../controlC2
lrwxrwxrwx 1 root root  12 Jan 27 10:34 pci-0000:00:07.0 -> ../controlC0
lrwxrwxrwx 1 root root  12 Jan 27 10:34 pci-0000:01:08.0 -> ../controlC1
state.NVidia {
	control.1 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 39'
		comment.dbmin -5850
		comment.dbmax 0
		iface MIXER
		name 'Front Playback Volume'
		value.0 39
		value.1 39
	}
	control.2 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 2
		iface MIXER
		name 'Front Playback Switch'
		value.0 true
		value.1 true
	}
	control.3 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 39'
		comment.dbmin -5850
		comment.dbmax 0
		iface MIXER
		name 'Surround Playback Volume'
		value.0 39
		value.1 39
	}
	control.4 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 2
		iface MIXER
		name 'Surround Playback Switch'
		value.0 true
		value.1 true
	}
	control.5 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 1
		comment.range '0 - 39'
		comment.dbmin -5850
		comment.dbmax 0
		iface MIXER
		name 'Center Playback Volume'
		value 39
	}
	control.6 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 1
		comment.range '0 - 39'
		comment.dbmin -5850
		comment.dbmax 0
		iface MIXER
		name 'LFE Playback Volume'
		value 39
	}
	control.7 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 1
		iface MIXER
		name 'Center Playback Switch'
		value true
	}
	control.8 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 1
		iface MIXER
		name 'LFE Playback Switch'
		value true
	}
	control.9 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 39'
		comment.dbmin -5850
		comment.dbmax 0
		iface MIXER
		name 'Side Playback Volume'
		value.0 39
		value.1 39
	}
	control.10 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 2
		iface MIXER
		name 'Side Playback Switch'
		value.0 true
		value.1 true
	}
	control.11 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 2
		iface MIXER
		name 'Headphone Playback Switch'
		value.0 true
		value.1 true
	}
	control.12 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 31'
		comment.dbmin -3450
		comment.dbmax 1200
		iface MIXER
		name 'Mic Playback Volume'
		value.0 12
		value.1 12
	}
	control.13 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 2
		iface MIXER
		name 'Mic Playback Switch'
		value.0 true
		value.1 true
	}
	control.14 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 3'
		comment.dbmin 0
		comment.dbmax 3000
		iface MIXER
		name 'Mic Boost'
		value.0 1
		value.1 1
	}
	control.15 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 31'
		comment.dbmin -3450
		comment.dbmax 1200
		iface MIXER
		name 'Front Mic Playback Volume'
		value.0 31
		value.1 31
	}
	control.16 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 2
		iface MIXER
		name 'Front Mic Playback Switch'
		value.0 true
		value.1 true
	}
	control.17 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 3'
		comment.dbmin 0
		comment.dbmax 3000
		iface MIXER
		name 'Front Mic Boost'
		value.0 1
		value.1 1
	}
	control.18 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 31'
		comment.dbmin -3450
		comment.dbmax 1200
		iface MIXER
		name 'Line Playback Volume'
		value.0 11
		value.1 11
	}
	control.19 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 2
		iface MIXER
		name 'Line Playback Switch'
		value.0 true
		value.1 true
	}
	control.20 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 31'
		comment.dbmin -3450
		comment.dbmax 1200
		iface MIXER
		name 'Front Line Playback Volume'
		value.0 31
		value.1 31
	}
	control.21 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 2
		iface MIXER
		name 'Front Line Playback Switch'
		value.0 true
		value.1 true
	}
	control.22 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 31'
		comment.dbmin -3450
		comment.dbmax 1200
		iface MIXER
		name 'CD Playback Volume'
		value.0 31
		value.1 31
	}
	control.23 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 2
		iface MIXER
		name 'CD Playback Switch'
		value.0 true
		value.1 true
	}
	control.24 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 31'
		comment.dbmin -3450
		comment.dbmax 1200
		iface MIXER
		name 'Aux Playback Volume'
		value.0 31
		value.1 31
	}
	control.25 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 2
		iface MIXER
		name 'Aux Playback Switch'
		value.0 true
		value.1 true
	}
	control.26 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 31'
		comment.dbmin -4650
		comment.dbmax 0
		iface MIXER
		name 'Analog Mix Playback Volume'
		value.0 31
		value.1 31
	}
	control.27 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 2
		iface MIXER
		name 'Analog Mix Playback Switch'
		value.0 true
		value.1 true
	}
	control.28 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 54'
		comment.dbmin -5850
		comment.dbmax 2250
		iface MIXER
		name 'Capture Volume'
		value.0 54
		value.1 54
	}
	control.29 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 2
		iface MIXER
		name 'Capture Switch'
		value.0 true
		value.1 true
	}
	control.30 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 54'
		comment.dbmin -5850
		comment.dbmax 2250
		iface MIXER
		name 'Capture Volume'
		index 1
		value.0 39
		value.1 39
	}
	control.31 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 2
		iface MIXER
		name 'Capture Switch'
		index 1
		value.0 false
		value.1 false
	}
	control.32 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 54'
		comment.dbmin -5850
		comment.dbmax 2250
		iface MIXER
		name 'Capture Volume'
		index 2
		value.0 39
		value.1 39
	}
	control.33 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 2
		iface MIXER
		name 'Capture Switch'
		index 2
		value.0 false
		value.1 false
	}
	control.34 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Mic
		comment.item.1 'Front Mic'
		comment.item.2 Line
		comment.item.3 'Front Line'
		comment.item.4 CD
		comment.item.5 Aux
		comment.item.6 Mix
		iface MIXER
		name 'Input Source'
		value 'Front Mic'
	}
	control.35 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Mic
		comment.item.1 'Front Mic'
		comment.item.2 Line
		comment.item.3 'Front Line'
		comment.item.4 CD
		comment.item.5 Aux
		comment.item.6 Mix
		iface MIXER
		name 'Input Source'
		index 1
		value Mic
	}
	control.36 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Mic
		comment.item.1 'Front Mic'
		comment.item.2 Line
		comment.item.3 'Front Line'
		comment.item.4 CD
		comment.item.5 Aux
		comment.item.6 Mix
		iface MIXER
		name 'Input Source'
		index 2
		value Mic
	}
	control.37 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 39'
		comment.dbmin -5850
		comment.dbmax 0
		iface MIXER
		name 'IEC958 Playback Volume'
		value.0 39
		value.1 39
	}
	control.38 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 PCM
		comment.item.1 ADC1
		comment.item.2 ADC2
		comment.item.3 ADC3
		iface MIXER
		name 'IEC958 Playback Source'
		value PCM
	}
	control.39 {
		comment.access read
		comment.type IEC958
		comment.count 1
		iface MIXER
		name 'IEC958 Playback Con Mask'
		value '0fff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
	}
	control.40 {
		comment.access read
		comment.type IEC958
		comment.count 1
		iface MIXER
		name 'IEC958 Playback Pro Mask'
		value '0f00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
	}
	control.41 {
		comment.access 'read write'
		comment.type IEC958
		comment.count 1
		iface MIXER
		name 'IEC958 Playback Default'
		value '0400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
	}
	control.42 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 1
		iface MIXER
		name 'IEC958 Playback Switch'
		value true
	}
	control.43 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 1
		iface MIXER
		name 'IEC958 Default PCM Playback Switch'
		value true
	}
	control.44 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 1
		comment.range '0 - 15'
		comment.dbmin -4500
		comment.dbmax 0
		iface MIXER
		name 'Beep Playback Volume'
		value 15
	}
	control.45 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 1
		iface MIXER
		name 'Beep Playback Switch'
		value true
	}
	control.46 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 1
		comment.range '0 - 39'
		comment.dbmin -5850
		comment.dbmax 0
		iface MIXER
		name 'Master Playback Volume'
		value 38
	}
	control.47 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 1
		iface MIXER
		name 'Master Playback Switch'
		value true
	}
	control.48 {
		comment.access read
		comment.type IEC958
		comment.count 1
		iface MIXER
		name 'IEC958 Playback Con Mask'
		index 1
		value '0fff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
	}
	control.49 {
		comment.access read
		comment.type IEC958
		comment.count 1
		iface MIXER
		name 'IEC958 Playback Pro Mask'
		index 1
		value '0f00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
	}
	control.50 {
		comment.access 'read write'
		comment.type IEC958
		comment.count 1
		iface MIXER
		name 'IEC958 Playback Default'
		index 1
		value '0400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
	}
	control.51 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 1
		iface MIXER
		name 'IEC958 Playback Switch'
		index 1
		value false
	}
	control.52 {
		comment.access 'read write user'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 255'
		comment.tlv '0000000100000008ffffec1400000014'
		comment.dbmin -5100
		comment.dbmax 0
		iface MIXER
		name 'PCM Playback Volume'
		value.0 250
		value.1 250
	}
}
state.EMU0404 {
	control.1 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'PCM Front Playback Volume'
		value.0 100
		value.1 100
	}
	control.2 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'PCM Surround Playback Volume'
		value.0 100
		value.1 100
	}
	control.3 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'PCM Side Playback Volume'
		value.0 100
		value.1 100
	}
	control.4 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 1
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'PCM Center Playback Volume'
		value 100
	}
	control.5 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 1
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'PCM LFE Playback Volume'
		value 100
	}
	control.6 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'PCM Playback Volume'
		value.0 100
		value.1 100
	}
	control.7 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'Synth Playback Volume'
		value.0 80
		value.1 80
	}
	control.8 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'PCM Capture Volume'
		value.0 100
		value.1 100
	}
	control.9 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'Synth Capture Volume'
		value.0 100
		value.1 100
	}
	control.10 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'EMU Capture Volume'
		value.0 92
		value.1 92
	}
	control.11 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'Mic Playback Volume'
		value.0 94
		value.1 94
	}
	control.12 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'Mic Capture Volume'
		value.0 99
		value.1 100
	}
	control.13 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'CD Playback Volume'
		value.0 31
		value.1 31
	}
	control.14 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'CD Capture Volume'
		value.0 30
		value.1 30
	}
	control.15 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'IEC958 Optical Playback Volume'
		value.0 0
		value.1 0
	}
	control.16 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'IEC958 Optical Capture Volume'
		value.0 0
		value.1 0
	}
	control.17 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'Line Playback Volume'
		value.0 100
		value.1 97
	}
	control.18 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'Line Capture Volume'
		value.0 100
		value.1 100
	}
	control.19 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'Analog Mix Playback Volume'
		value.0 99
		value.1 99
	}
	control.20 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'Analog Mix Capture Volume'
		value.0 96
		value.1 96
	}
	control.21 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'Aux Playback Volume'
		value.0 0
		value.1 0
	}
	control.22 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'Aux Capture Volume'
		value.0 0
		value.1 0
	}
	control.23 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'Front Playback Volume'
		value.0 100
		value.1 100
	}
	control.24 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'Surround Playback Volume'
		value.0 100
		value.1 100
	}
	control.25 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 1
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'Center Playback Volume'
		value 100
	}
	control.26 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 1
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'LFE Playback Volume'
		value 100
	}
	control.27 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'Side Playback Volume'
		value.0 100
		value.1 100
	}
	control.28 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 40'
		iface MIXER
		name 'Tone Control - Bass'
		value.0 20
		value.1 20
	}
	control.29 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 2
		comment.range '0 - 40'
		iface MIXER
		name 'Tone Control - Treble'
		value.0 20
		value.1 20
	}
	control.30 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 2
		iface MIXER
		name 'Tone Control - Switch'
		value.0 false
		value.1 false
	}
	control.31 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 1
		comment.range '0 - 100'
		comment.dbmin -4000
		comment.dbmax 0
		iface MIXER
		name 'Master Playback Volume'
		value 99
	}
	control.32 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 2
		iface MIXER
		name 'IEC958 Optical Raw Playback Switch'
		value.0 false
		value.1 false
	}
	control.33 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 64
		iface PCM
		device 2
		name 'Captured FX8010 Outputs'
		value.0 false
		value.1 false
		value.2 false
		value.3 false
		value.4 false
		value.5 false
		value.6 false
		value.7 false
		value.8 false
		value.9 false
		value.10 false
		value.11 false
		value.12 false
		value.13 false
		value.14 false
		value.15 false
		value.16 false
		value.17 false
		value.18 false
		value.19 false
		value.20 false
		value.21 false
		value.22 false
		value.23 false
		value.24 false
		value.25 false
		value.26 false
		value.27 false
		value.28 false
		value.29 false
		value.30 false
		value.31 false
		value.32 true
		value.33 true
		value.34 true
		value.35 true
		value.36 true
		value.37 true
		value.38 true
		value.39 true
		value.40 true
		value.41 true
		value.42 true
		value.43 true
		value.44 true
		value.45 true
		value.46 true
		value.47 true
		value.48 true
		value.49 true
		value.50 true
		value.51 true
		value.52 true
		value.53 true
		value.54 true
		value.55 true
		value.56 true
		value.57 true
		value.58 true
		value.59 true
		value.60 true
		value.61 true
		value.62 true
		value.63 true
	}
	control.178 {
		comment.access read
		comment.type IEC958
		comment.count 1
		iface PCM
		name 'IEC958 Playback Mask'
		value ffffffff00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
	}
	control.179 {
		comment.access read
		comment.type IEC958
		comment.count 1
		iface PCM
		name 'IEC958 Playback Mask'
		index 1
		value ffffffff00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
	}
	control.180 {
		comment.access read
		comment.type IEC958
		comment.count 1
		iface PCM
		name 'IEC958 Playback Mask'
		index 2
		value ffffffff00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
	}
	control.181 {
		comment.access 'read write'
		comment.type IEC958
		comment.count 1
		iface PCM
		name 'IEC958 Playback Default'
		value '0492100200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
	}
	control.182 {
		comment.access 'read write'
		comment.type IEC958
		comment.count 1
		iface PCM
		name 'IEC958 Playback Default'
		index 1
		value '0492100200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
	}
	control.183 {
		comment.access 'read write'
		comment.type IEC958
		comment.count 1
		iface PCM
		name 'IEC958 Playback Default'
		index 2
		value '0492100200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
	}
	control.184 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'Dock DAC1 Left Playback Enum'
		value 'DSP 0'
	}
	control.185 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'Dock DAC1 Right Playback Enum'
		value 'DSP 1'
	}
	control.186 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'Dock DAC2 Left Playback Enum'
		value 'DSP 2'
	}
	control.187 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'Dock DAC2 Right Playback Enum'
		value 'DSP 3'
	}
	control.188 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'Dock DAC3 Left Playback Enum'
		value 'DSP 4'
	}
	control.189 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'Dock DAC3 Right Playback Enum'
		value 'DSP 5'
	}
	control.190 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'Dock DAC4 Left Playback Enum'
		value 'DSP 6'
	}
	control.191 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'Dock DAC4 Right Playback Enum'
		value 'DSP 7'
	}
	control.192 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'Dock Phones Left Playback Enum'
		value 'DSP 0'
	}
	control.193 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'Dock Phones Right Playback Enum'
		value 'DSP 1'
	}
	control.194 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'Dock SPDIF Left Playback Enum'
		value 'DSP 0'
	}
	control.195 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'Dock SPDIF Right Playback Enum'
		value 'DSP 1'
	}
	control.196 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name '1010 SPDIF Left Playback Enum'
		value 'DSP 0'
	}
	control.197 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name '1010 SPDIF Right Playback Enum'
		value 'DSP 1'
	}
	control.198 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name '0202 DAC Left Playback Enum'
		value 'Dock ADC1 Left'
	}
	control.199 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name '0202 DAC Right Playback Enum'
		value 'Dock ADC1 Right'
	}
	control.200 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name '1010 ADAT 0 Playback Enum'
		value 'DSP 0'
	}
	control.201 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name '1010 ADAT 1 Playback Enum'
		value 'DSP 1'
	}
	control.202 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name '1010 ADAT 2 Playback Enum'
		value 'DSP 2'
	}
	control.203 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name '1010 ADAT 3 Playback Enum'
		value 'DSP 3'
	}
	control.204 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name '1010 ADAT 4 Playback Enum'
		value 'DSP 4'
	}
	control.205 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name '1010 ADAT 5 Playback Enum'
		value 'DSP 5'
	}
	control.206 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name '1010 ADAT 6 Playback Enum'
		value 'DSP 6'
	}
	control.207 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name '1010 ADAT 7 Playback Enum'
		value 'DSP 7'
	}
	control.208 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'DSP 0 Capture Enum'
		value '0202 ADC Left'
	}
	control.209 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'DSP 1 Capture Enum'
		value '0202 ADC Right'
	}
	control.210 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'DSP 2 Capture Enum'
		value Silence
	}
	control.211 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'DSP 3 Capture Enum'
		value Silence
	}
	control.212 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'DSP 4 Capture Enum'
		value Silence
	}
	control.213 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'DSP 5 Capture Enum'
		value Silence
	}
	control.214 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'DSP 6 Capture Enum'
		value Silence
	}
	control.215 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'DSP 7 Capture Enum'
		value Silence
	}
	control.216 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'DSP 8 Capture Enum'
		value Silence
	}
	control.217 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'DSP 9 Capture Enum'
		value Silence
	}
	control.218 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'DSP A Capture Enum'
		value Silence
	}
	control.219 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'DSP B Capture Enum'
		value Silence
	}
	control.220 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'DSP C Capture Enum'
		value Silence
	}
	control.221 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'DSP D Capture Enum'
		value Silence
	}
	control.222 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'DSP E Capture Enum'
		value Silence
	}
	control.223 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'DSP F Capture Enum'
		value Silence
	}
	control.224 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'DSP 10 Capture Enum'
		value Silence
	}
	control.225 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'DSP 11 Capture Enum'
		value Silence
	}
	control.226 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'DSP 12 Capture Enum'
		value Silence
	}
	control.227 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'DSP 13 Capture Enum'
		value Silence
	}
	control.228 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'DSP 14 Capture Enum'
		value Silence
	}
	control.229 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 Silence
		comment.item.1 'Dock Mic A'
		comment.item.2 'Dock Mic B'
		comment.item.3 'Dock ADC1 Left'
		comment.item.4 'Dock ADC1 Right'
		comment.item.5 'Dock ADC2 Left'
		comment.item.6 'Dock ADC2 Right'
		comment.item.7 'Dock ADC3 Left'
		comment.item.8 'Dock ADC3 Right'
		comment.item.9 '0202 ADC Left'
		comment.item.10 '0202 ADC Right'
		comment.item.11 '0202 SPDIF Left'
		comment.item.12 '0202 SPDIF Right'
		comment.item.13 'ADAT 0'
		comment.item.14 'ADAT 1'
		comment.item.15 'ADAT 2'
		comment.item.16 'ADAT 3'
		comment.item.17 'ADAT 4'
		comment.item.18 'ADAT 5'
		comment.item.19 'ADAT 6'
		comment.item.20 'ADAT 7'
		comment.item.21 'DSP 0'
		comment.item.22 'DSP 1'
		comment.item.23 'DSP 2'
		comment.item.24 'DSP 3'
		comment.item.25 'DSP 4'
		comment.item.26 'DSP 5'
		comment.item.27 'DSP 6'
		comment.item.28 'DSP 7'
		comment.item.29 'DSP 8'
		comment.item.30 'DSP 9'
		comment.item.31 'DSP 10'
		comment.item.32 'DSP 11'
		comment.item.33 'DSP 12'
		comment.item.34 'DSP 13'
		comment.item.35 'DSP 14'
		comment.item.36 'DSP 15'
		comment.item.37 'DSP 16'
		comment.item.38 'DSP 17'
		comment.item.39 'DSP 18'
		comment.item.40 'DSP 19'
		comment.item.41 'DSP 20'
		comment.item.42 'DSP 21'
		comment.item.43 'DSP 22'
		comment.item.44 'DSP 23'
		comment.item.45 'DSP 24'
		comment.item.46 'DSP 25'
		comment.item.47 'DSP 26'
		comment.item.48 'DSP 27'
		comment.item.49 'DSP 28'
		comment.item.50 'DSP 29'
		comment.item.51 'DSP 30'
		comment.item.52 'DSP 31'
		iface MIXER
		name 'DSP 15 Capture Enum'
		value Silence
	}
	control.230 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 1
		iface MIXER
		name 'ADC1 14dB PAD Audio Dock Capture Switch'
		value false
	}
	control.231 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 1
		iface MIXER
		name 'ADC2 14dB PAD Audio Dock Capture Switch'
		value false
	}
	control.232 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 1
		iface MIXER
		name 'ADC3 14dB PAD Audio Dock Capture Switch'
		value false
	}
	control.233 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 1
		iface MIXER
		name 'ADC1 14dB PAD 0202 Capture Switch'
		value false
	}
	control.234 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 1
		iface MIXER
		name 'DAC1 Audio Dock 14dB PAD Playback Switch'
		value true
	}
	control.235 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 1
		iface MIXER
		name 'DAC2 Audio Dock 14dB PAD Playback Switch'
		value true
	}
	control.236 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 1
		iface MIXER
		name 'DAC3 Audio Dock 14dB PAD Playback Switch'
		value true
	}
	control.237 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 1
		iface MIXER
		name 'DAC4 Audio Dock 14dB PAD Playback Switch'
		value true
	}
	control.238 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 1
		iface MIXER
		name 'DAC1 0202 14dB PAD Playback Switch'
		value false
	}
	control.239 {
		comment.access 'read write'
		comment.type ENUMERATED
		comment.count 1
		comment.item.0 '44100'
		comment.item.1 '48000'
		comment.item.2 SPDIF
		comment.item.3 ADAT
		iface MIXER
		name 'Clock Internal Rate'
		value '48000'
	}
}
state.USB {
	control.1 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 1
		iface MIXER
		name 'PCM Playback Switch'
		value true
	}
	control.2 {
		comment.access 'read write'
		comment.type INTEGER
		comment.count 4
		comment.range '0 - 200'
		comment.dbmin 0
		comment.dbmax 0
		iface MIXER
		name 'PCM Playback Volume'
		value.0 200
		value.1 200
		value.2 0
		value.3 0
	}
	control.3 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 1
		iface MIXER
		name 'Extension Unit Switch'
		value false
	}
	control.4 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 1
		iface MIXER
		name 'Extension Unit Switch'
		index 1
		value true
	}
	control.5 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 1
		iface MIXER
		name 'Extension Unit Switch'
		index 2
		value true
	}
	control.6 {
		comment.access 'read write'
		comment.type BOOLEAN
		comment.count 1
		iface MIXER
		name 'Extension Unit Switch'
		index 3
		value true
	}
}
ALSA sound/pci/hda/hda_codec.c:4288:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
ALSA sound/pci/hda/hda_codec.c:4292:    hp_outs=1 (0x11/0x0/0x0/0x0/0x0)
ALSA sound/pci/hda/hda_codec.c:4293:    mono: mono_out=0x0
ALSA sound/pci/hda/hda_codec.c:4296:    dig-out=0x1b/0x0
ALSA sound/pci/hda/hda_codec.c:4304:    inputs: mic=0x17, fmic=0x14, line=0x15, fline=0x0, cd=0x18, aux=0x0
Sid Boyce ... Hamradio License G3VBV, Licensed Private Pilot
Emeritus IBM/Amdahl Mainframes and Sun/Fujitsu Servers Tech Support
Specialist, Cricket Coach
Microsoft Windows Free Zone - Linux used for all Computing Tasks
Regards/Gruss,
    Boris.
For the one fact about the future of which we can be certain is that it
will be utterly fantastic. -- Arthur C. Clarke, 1962
http://selenic.com : development and support for Mercurial and Linux
[email protected] -- Speaking for myself only.
http://selenic.com : development and support for Mercurial and Linux
     LKML: http://lkml.org/lkml/2009/12/26/40
     FDO:  http://bugs.freedesktop.org/show_bug.cgi?id=25809
Nick Bowler, Elliptic Technologies (http://www.elliptictech.com/)
     LKML: http://lkml.org/lkml/2009/12/26/40
     FDO:  http://bugs.freedesktop.org/show_bug.cgi?id=25809
     LKML: http://lkml.org/lkml/2009/12/26/40
     FDO:  http://bugs.freedesktop.org/show_bug.cgi?id=25809
     LKML: http://lkml.org/lkml/2009/12/26/40
     FDO:  http://bugs.freedesktop.org/show_bug.cgi?id=25809
Nick Bowler, Elliptic Technologies (http://www.elliptictech.com/)