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Use PIPE_CONTROL where possible

PATCH In review Jesse Barnes 2 participants 10 messages Apr 21, 2010 – May 3, 2010

Subsystems (2)
DRM drivers Intel i915
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Jesse Barnes

author
#0 lore raw

Recent hardware supports the PIPE_CONTROL command. It seems to be necessary for stability on Ironlake at least, and should be a performance win on other platforms. This patchset (tested on Ironlake only) adds support for the PIPE_CONTROL command and changes GEM to use it by default.

There's a stray FBC cleanup patch in here as well, since I was working on debugging some leftover DMA mappings at unload. Of course, since I was testing on Ironlake, the FBC cleanup has no effect, but it's a good patch anyway.

Thanks,
Jesse

author
#1 lore raw

PATCH 1/5 drm/i915: cleanup FBC buffers at unload time

This keeps the memory manager from complaining when we take it down.

Signed-off-by Jesse Barnes <[email protected]>
---
 drivers/gpu/drm/i915/i915_dma.c |   14 ++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h |    3 +++
 2 files changed, 17 insertions(+), 0 deletions(-)
drivers/gpu/drm/i915/i915_dma.c +14 -0
index 75248be..5853d57 100644
@@ -1356,6 +1356,8 @@ static void i915_setup_compression(struct drm_device *dev, int size)
 
 	dev_priv->cfb_size = size;
 
+	dev_priv->compressed_fb = compressed_fb;
+
 	if (IS_GM45(dev)) {
 		g4x_disable_fbc(dev);
 		I915_WRITE(DPFC_CB_BASE, compressed_fb->start);

@@ -1363,12 +1365,22 @@ static void i915_setup_compression(struct drm_device *dev, int size)
 		i8xx_disable_fbc(dev);
 		I915_WRITE(FBC_CFB_BASE, cfb_base);
 		I915_WRITE(FBC_LL_BASE, ll_base);
+		dev_priv->compressed_llb = compressed_llb;
 	}
 
 	DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
 		  ll_base, size >> 20);
 }
 
+static void i915_cleanup_compression(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	drm_mm_put_block(dev_priv->compressed_fb);
+	if (!IS_GM45(dev))
+		drm_mm_put_block(dev_priv->compressed_llb);
+}
+
 /* true = enable decode, false = disable decoder */
 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 {

@@ -1788,6 +1800,8 @@ int i915_driver_unload(struct drm_device *dev)
 		mutex_lock(&dev->struct_mutex);
 		i915_gem_cleanup_ringbuffer(dev);
 		mutex_unlock(&dev->struct_mutex);
+		if (I915_HAS_FBC(dev) && i915_powersave)
+			i915_cleanup_compression(dev);
 		drm_mm_takedown(&dev_priv->vram);
 		i915_gem_lastclose(dev);
drivers/gpu/drm/i915/i915_drv.h +3 -0
index 790fef3..b3e6678 100644
@@ -638,6 +638,9 @@ typedef struct drm_i915_private {
 	u8 max_delay;
 
 	enum no_fbc_reason no_fbc_reason;
+
+	struct drm_mm_node *compressed_fb;
+	struct drm_mm_node *compressed_llb;
 } drm_i915_private_t;
 
 /** driver private structure attached to each drm_gem_object */
Signature · 1 line
1.7.0.1
author
#2 lore raw

PATCH 2/5 drm/i915: use PIPE_CONTROL instruction on Ironlake and Sandy Bridge

In reply to Jesse Barnes

Since 965, the hardware has supported the PIPE_CONTROL command, which provides fine grained GPU cache flushing control. On recent chipsets, this instruction is required for reliable interrupt and sequence number reporting in the driver.

So add support for this instruction, including workarounds, on Ironlake and Sandy Bridge hardware.

Signed-off-by Jesse Barnes <[email protected]>
---
 drivers/gpu/drm/i915/i915_drv.h |    4 +
 drivers/gpu/drm/i915/i915_gem.c |  145 +++++++++++++++++++++++++++++++++++---
 drivers/gpu/drm/i915/i915_irq.c |    8 +-
 drivers/gpu/drm/i915/i915_reg.h |   11 +++
 4 files changed, 152 insertions(+), 16 deletions(-)
drivers/gpu/drm/i915/i915_drv.h +4 -0
index b3e6678..71ae2f1 100644
@@ -240,11 +240,14 @@ typedef struct drm_i915_private {
 
 	drm_dma_handle_t *status_page_dmah;
 	void *hw_status_page;
+	void *seqno_page;
 	dma_addr_t dma_status_page;
 	uint32_t counter;
 	unsigned int status_gfx_addr;
+	unsigned int seqno_gfx_addr;
 	drm_local_map_t hws_map;
 	struct drm_gem_object *hws_obj;
+	struct drm_gem_object *seqno_obj;
 	struct drm_gem_object *pwrctx;
 
 	struct resource mch_res;

@@ -1153,6 +1156,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 
 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
+#define HAS_PIPE_CONTROL(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev))
 
 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
drivers/gpu/drm/i915/i915_gem.c +133 -12

201 lines not on this page · raw message

drivers/gpu/drm/i915/i915_irq.c +4 -4
index 7701cbd..06a743f 100644
@@ -352,7 +352,7 @@ irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 				READ_BREADCRUMB(dev_priv);
 	}
 
-	if (gt_iir & GT_USER_INTERRUPT) {
+	if (gt_iir & GT_PIPE_NOTIFY) {
 		u32 seqno = i915_get_gem_seqno(dev);
 		dev_priv->mm.irq_gem_seqno = seqno;
 		trace_i915_gem_request_complete(dev, seqno);

@@ -1009,7 +1009,7 @@ void i915_user_irq_get(struct drm_device *dev)
 	spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 	if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
 		if (HAS_PCH_SPLIT(dev))
-			ironlake_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
+			ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
 		else
 			i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 	}

@@ -1025,7 +1025,7 @@ void i915_user_irq_put(struct drm_device *dev)
 	BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
 	if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
 		if (HAS_PCH_SPLIT(dev))
-			ironlake_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
+			ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
 		else
 			i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 	}

@@ -1309,7 +1309,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
 	/* enable kind of interrupts always enabled */
 	u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
 			   DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
-	u32 render_mask = GT_USER_INTERRUPT;
+	u32 render_mask = GT_PIPE_NOTIFY;
 	u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
 			   SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
drivers/gpu/drm/i915/i915_reg.h +11 -0
index 527d30a..7256a46 100644
@@ -230,6 +230,16 @@
 #define   ASYNC_FLIP                (1<<22)
 #define   DISPLAY_PLANE_A           (0<<20)
 #define   DISPLAY_PLANE_B           (1<<20)
+#define GFX_OP_PIPE_CONTROL	((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
+#define   PIPE_CONTROL_QW_WRITE	(1<<14)
+#define   PIPE_CONTROL_DEPTH_STALL (1<<13)
+#define   PIPE_CONTROL_WC_FLUSH	(1<<12)
+#define   PIPE_CONTROL_IS_FLUSH	(1<<11) /* MBZ on Ironlake */
+#define   PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */
+#define   PIPE_CONTROL_ISP_DIS	(1<<9)
+#define   PIPE_CONTROL_NOTIFY	(1<<8)
+#define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
+#define   PIPE_CONTROL_STALL_EN	(1<<1) /* in addr word, Ironlake+ only */
 
 /*
  * Fence registers

@@ -2339,6 +2349,7 @@
 #define DEIER   0x4400c
 
 /* GT interrupt */
+#define GT_PIPE_NOTIFY		(1 << 4)
 #define GT_SYNC_STATUS          (1 << 2)
 #define GT_USER_INTERRUPT       (1 << 0)
Signature · 1 line
1.7.0.1
author
#3 lore raw

PATCH 3/5 drm/i915: use PIPE_CONTROL to retire commands

In reply to Jesse Barnes

This allows us to do less cache flushing on 965+ chipsets.

Signed-off-by Jesse Barnes <[email protected]>
---
 drivers/gpu/drm/i915/i915_gem.c |   25 +++++++++++++++++--------
 1 files changed, 17 insertions(+), 8 deletions(-)
drivers/gpu/drm/i915/i915_gem.c +17 -8
index e7fc200..21bfaae 100644
@@ -1707,17 +1707,26 @@ static uint32_t
 i915_retire_commands(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
-	uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 	uint32_t flush_domains = 0;
 	RING_LOCALS;
 
-	/* The sampler always gets flushed on i965 (sigh) */
-	if (IS_I965G(dev))
-		flush_domains |= I915_GEM_DOMAIN_SAMPLER;
-	BEGIN_LP_RING(2);
-	OUT_RING(cmd);
-	OUT_RING(0); /* noop */
-	ADVANCE_LP_RING();
+	if (HAS_PIPE_CONTROL(dev)) {
+		/* PIPE_CONTROL flushes sampler & vertex by default on 965*/
+		if (!(IS_G4X(dev) || IS_IRONLAKE(dev)))
+			flush_domains |= I915_GEM_DOMAIN_SAMPLER |
+				I915_GEM_DOMAIN_VERTEX	;
+		BEGIN_LP_RING(4);
+		OUT_RING(GFX_OP_PIPE_CONTROL);
+		OUT_RING(0); /* unused addr */
+		OUT_RING(0); /* unused data */
+		OUT_RING(0); /* unused data */
+		ADVANCE_LP_RING();
+	} else {
+		BEGIN_LP_RING(2);
+		OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH);
+		OUT_RING(0); /* noop */
+		ADVANCE_LP_RING();
+	}
 	return flush_domains;
 }
Signature · 1 line
1.7.0.1
#4 lore raw

Re: [PATCH 3/5] drm/i915: use PIPE_CONTROL to retire commands

Quoted 1 line · Jesse Barnes

This allows us to do less cache flushing on 965+ chipsets.

I don't think this commit is correct. The ring processing will continue past the PIPE_CONTROL and on to the MI_USER_INTERRUPT before the pipeline is flushed.

I suspect that squashing this with later commits may make for a correct change, though.

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

author
#5 lore raw

Re: [PATCH 3/5] drm/i915: use PIPE_CONTROL to retire commands

Quoted 10 lines · On Thu, 29 Apr 2010 14:26:38 -0700 Eric Anholt <[email protected]> wrote:
Quoted 1 line · Jesse Barnes

This allows us to do less cache flushing on 965+ chipsets.

I don't think this commit is correct. The ring processing will continue past the PIPE_CONTROL and on to the MI_USER_INTERRUPT before the pipeline is flushed.

I suspect that squashing this with later commits may make for a correct change, though.

Sorry I didn't split these very well; squash them if needed or kick them back to me and I'll repost.

Thanks,
Jesse

author
#6 lore raw

PATCH 4/5 drm/i915: use PIPE_CONTROL for GEM domain flushing

In reply to Jesse Barnes

This gives us finer grained cache control, so should be higher performance.

Signed-off-by Jesse Barnes <[email protected]>
---
 drivers/gpu/drm/i915/i915_gem.c |   52 +++++++++++++++++++++++++++++---------
 1 files changed, 39 insertions(+), 13 deletions(-)
drivers/gpu/drm/i915/i915_gem.c +39 -13
index 21bfaae..e6a1cc0 100644
@@ -1983,29 +1983,55 @@ i915_gem_flush(struct drm_device *dev,
 		 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 		 * are flushed at any MI_FLUSH.
 		 */
+		if (HAS_PIPE_CONTROL(dev)) {
+			cmd = GFX_OP_PIPE_CONTROL;
 
-		cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
-		if ((invalidate_domains|flush_domains) &
-		    I915_GEM_DOMAIN_RENDER)
-			cmd &= ~MI_NO_WRITE_FLUSH;
-		if (!IS_I965G(dev)) {
+			/*
+			 * Different chips support different flush bits, so
+			 * be careful here.  See 3D pipeline volume for
+			 * flush tables.
+			 */
+			if ((invalidate_domains|flush_domains) &
+			    I915_GEM_DOMAIN_RENDER)
+				cmd |= PIPE_CONTROL_WC_FLUSH;
+
+			if ((IS_G4X(dev) || IS_IRONLAKE(dev)) &&
+			    invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
+				cmd |= PIPE_CONTROL_TC_FLUSH;
+
+			if (!IS_IRONLAKE(dev) &&
+			    invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
+				cmd |= PIPE_CONTROL_IS_FLUSH;
+
+			BEGIN_LP_RING(4);
+			OUT_RING(cmd);
+			OUT_RING(0); /* unused addr */
+			OUT_RING(0); /* unused data */
+			OUT_RING(0); /* unused data */
+			ADVANCE_LP_RING();
+		} else {
+			cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
+			if ((invalidate_domains|flush_domains) &
+			    I915_GEM_DOMAIN_RENDER)
+				cmd &= ~MI_NO_WRITE_FLUSH;
 			/*
 			 * On the 965, the sampler cache always gets flushed
 			 * and this bit is reserved.
 			 */
 			if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 				cmd |= MI_READ_FLUSH;
-		}
-		if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
-			cmd |= MI_EXE_FLUSH;
+			if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
+				cmd |= MI_EXE_FLUSH;
 
 #if WATCH_EXEC
-		DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
+			DRM_INFO("%s: queue flush %08x to ring\n", __func__,
+				 cmd);
 #endif
-		BEGIN_LP_RING(2);
-		OUT_RING(cmd);
-		OUT_RING(MI_NOOP);
-		ADVANCE_LP_RING();
+			BEGIN_LP_RING(2);
+			OUT_RING(cmd);
+			OUT_RING(MI_NOOP);
+			ADVANCE_LP_RING();
+		}
 	}
 }
Signature · 1 line
1.7.0.1
author
#7 lore raw

PATCH 5/5 drm/i915: enable PIPE_CONTROL on all 965 class chips

In reply to Jesse Barnes

Since it's supported on 965 and G4x, enable it there as well.

Signed-off-by Jesse Barnes <[email protected]>
---
 drivers/gpu/drm/i915/i915_drv.h |    2 +-
 drivers/gpu/drm/i915/i915_irq.c |   33 ++++++++++++++++++++++++++-------
 2 files changed, 27 insertions(+), 8 deletions(-)
drivers/gpu/drm/i915/i915_drv.h +1 -1
index 71ae2f1..4b9a12f 100644
@@ -1156,7 +1156,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 
 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
-#define HAS_PIPE_CONTROL(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev))
+#define HAS_PIPE_CONTROL(dev) (IS_I965G(dev))
 
 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
drivers/gpu/drm/i915/i915_irq.c +26 -7
index 06a743f..f1e85b6 100644
@@ -51,9 +51,6 @@
 	 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |	\
 	 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 
-/** Interrupts that we mask and unmask at runtime. */
-#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
-
 #define I915_PIPE_VBLANK_STATUS	(PIPE_START_VBLANK_INTERRUPT_STATUS |\
 				 PIPE_VBLANK_INTERRUPT_STATUS)
 

@@ -922,8 +919,13 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 					READ_BREADCRUMB(dev_priv);
 		}
 
-		if (iir & I915_USER_INTERRUPT) {
+		if (iir &
+		    (I915_USER_INTERRUPT | I915_PIPE_CONTROL_NOTIFY_INTERRUPT)) {
 			u32 seqno = i915_get_gem_seqno(dev);
+
+			if (IS_I965G(dev) && (iir & I915_USER_INTERRUPT))
+				DRM_DEBUG_DRIVER("unexpected user interrupt\n");
+
 			dev_priv->mm.irq_gem_seqno = seqno;
 			trace_i915_gem_request_complete(dev, seqno);
 			DRM_WAKEUP(&dev_priv->irq_queue);

@@ -1005,13 +1007,19 @@ void i915_user_irq_get(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	unsigned long irqflags;
+	u32 irq;
+
+	if (IS_I965G(dev))
+		irq = I915_PIPE_CONTROL_NOTIFY_INTERRUPT;
+	else
+		irq = I915_USER_INTERRUPT;
 
 	spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 	if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
 		if (HAS_PCH_SPLIT(dev))
 			ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
 		else
-			i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
+			i915_enable_irq(dev_priv, irq);
 	}
 	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 }

@@ -1020,6 +1028,12 @@ void i915_user_irq_put(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	unsigned long irqflags;
+	u32 irq;
+
+	if (IS_I965G(dev))
+		irq = I915_PIPE_CONTROL_NOTIFY_INTERRUPT;
+	else
+		irq = I915_USER_INTERRUPT;
 
 	spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 	BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);

@@ -1027,7 +1041,7 @@ void i915_user_irq_put(struct drm_device *dev)
 		if (HAS_PCH_SPLIT(dev))
 			ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
 		else
-			i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
+			i915_disable_irq(dev_priv, irq);
 	}
 	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 }

@@ -1383,7 +1397,7 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
 int i915_driver_irq_postinstall(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-	u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
+	u32 enable_mask = I915_INTERRUPT_ENABLE_FIX;
 	u32 error_mask;
 
 	DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);

@@ -1393,6 +1407,11 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
 	if (HAS_PCH_SPLIT(dev))
 		return ironlake_irq_postinstall(dev);
 
+	if (IS_I965G(dev))
+		enable_mask |= I915_PIPE_CONTROL_NOTIFY_INTERRUPT;
+	else
+		enable_mask |= I915_USER_INTERRUPT;
+
 	/* Unmask the interrupts that we always want on. */
 	dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
Signature · 1 line
1.7.0.1
author
#8 lore raw

PATCH 1/1 drm/i915: avoid unnecessary PIPE_CONTROL flushing on non-Ironlake

Avoid unnecessary PIPE_CONTROL flushing on non-Ironlake platforms where it shouldn't be needed.

Signed-off-by Jesse Barnes <[email protected]>
drivers/gpu/drm/i915/i915_gem.c +11 -1
index e6a1cc0..56ff905 100644
@@ -1628,7 +1628,7 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
 	if (dev_priv->mm.next_gem_seqno == 0)
 		dev_priv->mm.next_gem_seqno++;
 
-	if (HAS_PIPE_CONTROL(dev)) {
+	if (HAS_PIPE_CONTROL(dev) && IS_IRONLAKE(dev)) {
 		u32 scratch_addr = dev_priv->seqno_gfx_addr + 128;
 
 		/*

@@ -1660,6 +1660,16 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
 		OUT_RING(seqno);
 		OUT_RING(0);
 		ADVANCE_LP_RING();
+	} else if (HAS_PIPE_CONTROL(dev)) {
+		/* Don't penalize non-ilk parts with the extra writes */
+		BEGIN_LP_RING(4);
+		OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
+			 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
+			 PIPE_CONTROL_NOTIFY);
+		OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
+		OUT_RING(seqno);
+		OUT_RING(0);
+		ADVANCE_LP_RING();
 	} else {
 		BEGIN_LP_RING(4);
 		OUT_RING(MI_STORE_DWORD_INDEX);
author
#9 lore raw

PATCH 1/1 drm/i915: remove unnecessary PIPE_CONTROL cache flushing

In reply to Jesse Barnes

Was better safe than sorry, but it appears these bits aren't necessary.

Signed-off-by Jesse Barnes <[email protected]>
---
 drivers/gpu/drm/i915/i915_gem.c |    5 +----
 1 files changed, 1 insertions(+), 4 deletions(-)
drivers/gpu/drm/i915/i915_gem.c +1 -4
index 56ff905..5a34b71 100644
@@ -1637,8 +1637,7 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
 		 * an interrupt.
 		 */
 		BEGIN_LP_RING(32);
-		OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
-			 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
+		OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE);
 		OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
 		OUT_RING(seqno);
 		OUT_RING(0);

@@ -1654,7 +1653,6 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
 		scratch_addr += 128;
 		PIPE_CONTROL_FLUSH(scratch_addr);
 		OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
-			 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
 			 PIPE_CONTROL_NOTIFY);
 		OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
 		OUT_RING(seqno);

@@ -1664,7 +1662,6 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
 		/* Don't penalize non-ilk parts with the extra writes */
 		BEGIN_LP_RING(4);
 		OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
-			 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
 			 PIPE_CONTROL_NOTIFY);
 		OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
 		OUT_RING(seqno);
Signature · 1 line
1.7.0.1