drm/i915: interlaced mode support (G35 VGA/SDVO)
Subsystems (2)
cover drm/i915: interlaced mode support (G35 VGA/SDVO)
This patch set enables enables interlaced mode output on the VGA and SDVO connectors of the G35 chipset.
History here: https://bugs.freedesktop.org/show_bug.cgi?id=11220
I have tested the changes on an ASUS P5E-VM-HDMI mainboard with VGA and HDMI CRTs attached. The G45 and SB documentation suggests that this will also work on those chipsets. (Wording of the vertical timing registers is near identical). Feedback welcome.
Peter Ross (2):
drm/i915: specify vertical timings in frame units for interlaced
modes (gen4+)
drm/i915: allow interlaced mode output on the SDVO connector
drivers/gpu/drm/i915/intel_display.c | 8 ++++++++ drivers/gpu/drm/i915/intel_sdvo.c | 2 +- 2 files changed, 9 insertions(+), 1 deletions(-)
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1.7.5.4 -- Peter (A907 E02F A6E5 0CD2 34CD 20D2 6760 79C5 AC40 DD6B)
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PATCH 1/2 drm/i915: specify vertical timings in frame units for interlaced modes (gen4+)
The G35/G45/SandyBridge chipsets expect vertical timings in frame units, whereas the DRM subsystem uses field units internally for interlaced modes.
--- drivers/gpu/drm/i915/intel_display.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-)
drivers/gpu/drm/i915/intel_display.c +8 -0
@@ -5316,6 +5316,14 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, adjusted_mode->crtc_vblank_end -=1 ; adjusted_mode->crtc_vsync_end -=1 ; adjusted_mode->crtc_vsync_start -=1 ; +if (INTEL_INFO (dev)->gen >=4 ) { + adjusted_mode->crtc_vdisplay *=2 ; + adjusted_mode->crtc_vtotal *=2 ; + adjusted_mode->crtc_vblank_start *=2 ; + adjusted_mode->crtc_vblank_end *=2 ; + adjusted_mode->crtc_vsync_end *=2 ; + adjusted_mode->crtc_vsync_start *=2 ; + } }else pipeconf &= ~PIPECONF_INTERLACE_MASK ;/* progressive */
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1.7.5.4 -- Peter (A907 E02F A6E5 0CD2 34CD 20D2 6760 79C5 AC40 DD6B)
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Re: [PATCH 1/2] drm/i915: specify vertical timings in frame units for interlaced modes (gen4+)
Quoted 16 lines · On Sun, 15 Jan 2012 01:52:11 +1100 Peter Ross <[email protected]> wrote:
The G35/G45/SandyBridge chipsets expect vertical timings in frame units, whereas the DRM subsystem uses field units internally for interlaced modes.
Signed-off-by Peter Ross <[email protected]>--- drivers/gpu/drm/i915/intel_display.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-)drivers/gpu/drm/i915/intel_display.c +0
-0@@ -5316,6 +5316,14 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, adjusted_mode->crtc_vblank_end -=1 ; adjusted_mode->crtc_vsync_end -=1 ; adjusted_mode->crtc_vsync_start -=1 ;
drivers/gpu/drm/i915/intel_display.c static int i9xx_crtc_mode_set(struct drm_crtc *crtc, · line 5328
Quoted 10 lines
drivers/gpu/drm/i915/intel_display.c +8
-0+if (INTEL_INFO (dev)->gen >=4 ) { + adjusted_mode->crtc_vdisplay *=2 ; + adjusted_mode->crtc_vtotal *=2 ; + adjusted_mode->crtc_vblank_start *=2 ; + adjusted_mode->crtc_vblank_end *=2 ; + adjusted_mode->crtc_vsync_end *=2 ; + adjusted_mode->crtc_vsync_start *=2 ; + } }else pipeconf &= ~PIPECONF_INTERLACE_MASK ;/* progressive */
I *think* this looks ok. It'll only affect pre-ILK chipsets though and interlaced modes.
Do we get the ILK+ side right here?
I'm with Eugeni; I'd like to see some tested-bys on this, otherwise it looks good.
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Jesse Barnes, Intel Open Source Technology Center
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Re: [PATCH 1/2] drm/i915: specify vertical timings in frame units for interlaced modes (gen4+)
Quoted 4 lines · Jesse Barnes
Do we get the ILK+ side right here?
From the specs, looks like ILK and SNB+ share same logic for this part.
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Eugeni Dodonov <http://eugeni.dodonov.net/>
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Re: [PATCH 1/2] drm/i915: specify vertical timings in frame units for interlaced modes (gen4+)
In reply to Peter RossQuoted 4 lines · Peter Ross
The G35/G45/SandyBridge chipsets expect vertical timings in frame units, whereas the DRM subsystem uses field units internally for interlaced modes.
Signed-off-by Peter Ross <[email protected]>
On a quick look at the patch it have a confusion about chipset generations. We generally call g35 i965 to avoid confusion with the gen3 device g33. Also i9xx_crtc_mode_set is only used on pre-ironlake (=gen5) and hence does not include snb. You might want to fix up ironlake_crtc_mode_set, too.
When quickly discussing this with Jesse on irc we concluded that this is fine if it comes with a tested-by (for both patches) attached, preferrably with quick details on which machines this was tested on. -Daniel
Quoted 35 lines
--- drivers/gpu/drm/i915/intel_display.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-)drivers/gpu/drm/i915/intel_display.c +8
-0@@ -5316,6 +5316,14 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, adjusted_mode->crtc_vblank_end -=1 ; adjusted_mode->crtc_vsync_end -=1 ; adjusted_mode->crtc_vsync_start -=1 ; +if (INTEL_INFO (dev)->gen >=4 ) { + adjusted_mode->crtc_vdisplay *=2 ; + adjusted_mode->crtc_vtotal *=2 ; + adjusted_mode->crtc_vblank_start *=2 ; + adjusted_mode->crtc_vblank_end *=2 ; + adjusted_mode->crtc_vsync_end *=2 ; + adjusted_mode->crtc_vsync_start *=2 ; + } }else pipeconf &= ~PIPECONF_INTERLACE_MASK ;/* progressive */ Signature · 11 lines
1.7.5.4 -- Peter (A907 E02F A6E5 0CD2 34CD 20D2 6760 79C5 AC40 DD6B) _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Daniel Vetter Mail: [email protected] Mobile: +41 (0)79 365 57 48
PATCH 2/2 drm/i915: allow interlaced mode output on the SDVO connector
In reply to Peter Ross--- drivers/gpu/drm/i915/intel_sdvo.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
drivers/gpu/drm/i915/intel_sdvo.c +1 -1
@@ -1987,7 +1987,7 @@ intel_sdvo_connector_init(struct intel_sdvo_connector *connector,drm_connector_helper_add (&connector->base.base, &intel_sdvo_connector_helper_funcs); - connector->base.base.interlace_allowed =0 ; + connector->base.base.interlace_allowed =1 ; connector->base.base.doublescan_allowed =0 ; connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
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1.7.5.4 -- Peter (A907 E02F A6E5 0CD2 34CD 20D2 6760 79C5 AC40 DD6B)
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Quoted 10 lines · Peter Ross
This patch set enables enables interlaced mode output on the VGA and SDVO connectors of the G35 chipset.
History here: https://bugs.freedesktop.org/show_bug.cgi?id=11220
I have tested the changes on an ASUS P5E-VM-HDMI mainboard with VGA and HDMI CRTs attached. The G45 and SB documentation suggests that this will also work on those chipsets. (Wording of the vertical timing registers is near identical). Feedback welcome.
Quoted 9 lines
Peter Ross (2):
drm/i915: specify vertical timings in frame units for interlaced
modes (gen4+)
drm/i915: allow interlaced mode output on the SDVO connectordrivers/gpu/drm/i915/intel_display.c | 8 ++++++++ drivers/gpu/drm/i915/intel_sdvo.c | 2 +- 2 files changed, 9 insertions(+), 1 deletions(-)
I am not very familiar with this area, but both patches look correct to me and are according to the specs as far as I can see.
So, for both of them:
Thanks!
P.S.: it would be interested to gather some Tested-by's for this though..
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Eugeni Dodonov <http://eugeni.dodonov.net/>
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