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ARM: Initial support for Cortex-M3

PATCH Superseded Uwe Kleine-König 4 participants 17 messages Mar 14, 2012

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Arm (32-bit) ptrace support

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Uwe Kleine-König

author
#0 lore raw

v3 cover ARM: Initial support for Cortex-M3

Hello,

this is the result of reworking Catalin's exception handling patch to stick to the current pt_regs layout. I extended it by two words to save the exception return value. (The 2nd word is unused and only to maintain stack alignment.)

Other than that only minor cleanups were done (some of them were suggested by Catalin in reply to my v2 series).

These patches are available at

git://git.pengutronix.de/git/ukl/linux.git cortexm3-for-rmk

basing on 3.3-rc7. There are some bits missing to allow a Cortex-M3 to boot. They are contained in the branch efm32 in the same repository together with support for the efm32 SoC if you're interested. The most important parts missing (apart from SoC specific stuff) are interrupt support and Makefile/Kconfig glue.

I'd be happy if these patches made it into 3.4-rc1. Any constructive feedback welcome.

Best regards
Uwe

Signature · 2 lines
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
author
#1 lore raw

PATCH v3 1/5 ARM: protect usage of cr_alignment by #ifdef CONFIG_CPU_CP15

Signed-off-by Uwe Kleine-K?nig <[email protected]>
---
 arch/arm/include/asm/system.h |    2 ++
 arch/arm/kernel/entry-armv.S  |    4 ++++
 arch/arm/kernel/head-common.S |   10 ++++++++--
 arch/arm/kernel/setup.c       |    8 ++++++--
 arch/arm/mm/alignment.c       |    6 ++++++
 arch/arm/mm/mmu.c             |    8 +++++++-
 6 files changed, 33 insertions(+), 5 deletions(-)
arch/arm/include/asm/system.h +2 -0
index e4c96cc..de46477 100644
@@ -185,6 +185,7 @@ extern unsigned int user_debug;
 #define set_mb(var, value)	do { var = value; smp_mb(); } while (0)
 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
 
+#ifdef CONFIG_CPU_CP15
 extern unsigned long cr_no_alignment;	/* defined in entry-armv.S */
 extern unsigned long cr_alignment;	/* defined in entry-armv.S */
 

@@ -224,6 +225,7 @@ static inline void set_copro_access(unsigned int val)
 	  : : "r" (val) : "cc");
 	isb();
 }
+#endif
 
 /*
  * switch_mm() may do a full cache flush over the context switch,
arch/arm/kernel/entry-armv.S +4 -0
index be16a48..a6f2ef5 100644
@@ -314,8 +314,10 @@ __pabt_svc:
 ENDPROC(__pabt_svc)
 
 	.align	5
+#ifdef CONFIG_CPU_CP15
 .LCcralign:
 	.word	cr_alignment
+#endif
 #ifdef MULTI_DABORT
 .LCprocfns:
 	.word	processor

@@ -1146,12 +1148,14 @@ __vectors_end:
 
 	.data
 
+#ifdef CONFIG_CPU_CP15
 	.globl	cr_alignment
 	.globl	cr_no_alignment
 cr_alignment:
 	.space	4
 cr_no_alignment:
 	.space	4
+#endif
 
 #ifdef CONFIG_MULTI_IRQ_HANDLER
 	.globl	handle_arch_irq
arch/arm/kernel/head-common.S +8 -2
index 854bd22..efeb2d0 100644
@@ -98,8 +98,10 @@ __mmap_switched:
 	str	r9, [r4]			@ Save processor ID
 	str	r1, [r5]			@ Save machine type
 	str	r2, [r6]			@ Save atags pointer
-	bic	r4, r0, #CR_A			@ Clear 'A' bit
-	stmia	r7, {r0, r4}			@ Save control register values
+	cmp	r7, #0
+	itt	ne
+	bicne	r4, r0, #CR_A			@ Clear 'A' bit
+	stmneia	r7, {r0, r4}			@ Save control register values
 	b	start_kernel
 ENDPROC(__mmap_switched)
 

@@ -113,7 +115,11 @@ __mmap_switched_data:
 	.long	processor_id			@ r4
 	.long	__machine_arch_type		@ r5
 	.long	__atags_pointer			@ r6
+#ifdef CONFIG_CPU_CP15
 	.long	cr_alignment			@ r7
+#else
+	.long	0				@ r7
+#endif
 	.long	init_thread_union + THREAD_START_SP @ sp
 	.size	__mmap_switched_data, . - __mmap_switched_data
arch/arm/kernel/setup.c +6 -2
index a255c39..50d3df8 100644
@@ -472,9 +472,13 @@ static void __init setup_processor(void)
 	cpu_cache = *list->cache;
 #endif
 
-	printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
+	printk("CPU: %s [%08x] revision %d (ARMv%s)",
 	       cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
-	       proc_arch[cpu_architecture()], cr_alignment);
+	       proc_arch[cpu_architecture()]);
+
+#ifdef CONFIG_CPU_CP15
+	printk(KERN_CONT ", cr=%08lx\n", cr_alignment);
+#endif
 
 	snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c",
 		 list->arch_name, ENDIANNESS);
arch/arm/mm/alignment.c +6 -0
index caf14dc..119d178 100644
@@ -89,7 +89,11 @@ core_param(alignment, ai_usermode, int, 0600);
 /* Return true if and only if the ARMv6 unaligned access model is in use. */
 static bool cpu_is_v6_unaligned(void)
 {
+#ifdef CONFIG_CPU_CP15
 	return cpu_architecture() >= CPU_ARCH_ARMv6 && (cr_alignment & CR_U);
+#else
+	return 0;
+#endif
 }
 
 static int safe_usermode(int new_usermode, bool warn)

@@ -961,12 +965,14 @@ static int __init alignment_init(void)
 		return -ENOMEM;
 #endif
 
+#ifdef CONFIG_CPU_CP15
 	if (cpu_is_v6_unaligned()) {
 		cr_alignment &= ~CR_A;
 		cr_no_alignment &= ~CR_A;
 		set_cr(cr_alignment);
 		ai_usermode = safe_usermode(ai_usermode, false);
 	}
+#endif
 
 	hook_fault_code(FAULT_CODE_ALIGNMENT, do_alignment, SIGBUS, BUS_ADRALN,
 			"alignment exception");
arch/arm/mm/mmu.c +7 -1
index 94c5a0c..f6dbe1a 100644
@@ -109,8 +109,10 @@ static int __init early_cachepolicy(char *p)
 
 		if (memcmp(p, cache_policies[i].policy, len) == 0) {
 			cachepolicy = i;
+#ifdef CONFIG_CPU_CP15
 			cr_alignment &= ~cache_policies[i].cr_mask;
 			cr_no_alignment &= ~cache_policies[i].cr_mask;
+#endif
 			break;
 		}
 	}

@@ -128,7 +130,9 @@ static int __init early_cachepolicy(char *p)
 		cachepolicy = CPOLICY_WRITEBACK;
 	}
 	flush_cache_all();
+#ifdef CONFIG_CPU_CP15
 	set_cr(cr_alignment);
+#endif
 	return 0;
 }
 early_param("cachepolicy", early_cachepolicy);

@@ -163,6 +167,7 @@ static int __init early_ecc(char *p)
 early_param("ecc", early_ecc);
 #endif
 
+#ifdef CONFIG_CPU_CP15
 static int __init noalign_setup(char *__unused)
 {
 	cr_alignment &= ~CR_A;

@@ -171,8 +176,9 @@ static int __init noalign_setup(char *__unused)
 	return 1;
 }
 __setup("noalign", noalign_setup);
+#endif
 
-#ifndef CONFIG_SMP
+#if !defined(CONFIG_SMP) && defined(CONFIG_CPU_CP15)
 void adjust_cr(unsigned long mask, unsigned long set)
 {
 	unsigned long flags;
Signature · 1 line
1.7.9.1
#2 lore raw

PATCH v3 1/5 ARM: protect usage of cr_alignment by #ifdef CONFIG_CPU_CP15

Quoted 1 line · Uwe Kleine-K?nig
Signed-off-by Uwe Kleine-K?nig <[email protected]>

I think you could reduce the amount of #ifdef's significantly here. While the cr_alignment variable and its sister are of no use in a no-CP15 system, you could still leave them there initialized to zero and only conditionally compile out the CP15 modifyers with a dummy version. This is only 2 words wasted in your kernel image to keep the code cleaner.

More comments below.

arch/arm/kernel/head-common.S __mmap_switched: · line 104

Quoted 13 lines

index 854bd22..efeb2d0 100644

arch/arm/kernel/head-common.S +4 -2
@@ -98,8 +98,10 @@ __mmap_switched:
 	str	r9, [r4]			@ Save processor ID
 	str	r1, [r5]			@ Save machine type
 	str	r2, [r6]			@ Save atags pointer
-	bic	r4, r0, #CR_A			@ Clear 'A' bit
-	stmia	r7, {r0, r4}			@ Save control register values
+	cmp	r7, #0
+	itt	ne
+	bicne	r4, r0, #CR_A			@ Clear 'A' bit
+	stmneia	r7, {r0, r4}			@ Save control register values

The kernel is compiled with -mimplicit-it so you do not need to specify any it here.

Quoted 7 lines

index a255c39..50d3df8 100644

arch/arm/kernel/setup.c +0 -0
@@ -472,9 +472,13 @@ static void __init setup_processor(void)
 	cpu_cache = *list->cache;
 #endif

arch/arm/kernel/setup.c static void __init setup_processor(void) · line 482

Quoted 10 lines
arch/arm/kernel/setup.c +6 -2
-	printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
+	printk("CPU: %s [%08x] revision %d (ARMv%s)",
 	       cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
-	       proc_arch[cpu_architecture()], cr_alignment);
+	       proc_arch[cpu_architecture()]);
+
+#ifdef CONFIG_CPU_CP15
+	printk(KERN_CONT ", cr=%08lx\n", cr_alignment);
+#endif

Again, you could just leave the original display, with cr=00000000 which is a fairly good representation of reality.

Quoted 5 lines
arch/arm/mm/alignment.c +0 -0
index caf14dc..119d178 100644

arch/arm/mm/alignment.c core_param(alignment, ai_usermode, int, 0600); · line 97

Quoted 9 lines
arch/arm/mm/alignment.c +4 -0
@@ -89,7 +89,11 @@ core_param(alignment, ai_usermode, int, 0600);
 /* Return true if and only if the ARMv6 unaligned access model is in use. */
 static bool cpu_is_v6_unaligned(void)
 {
+#ifdef CONFIG_CPU_CP15
 	return cpu_architecture() >= CPU_ARCH_ARMv6 && (cr_alignment & CR_U);
+#else
+	return 0;
+#endif
 }

Same here. With cr_alignment set to zero, you don't need the above #ifdef.

arch/arm/mm/alignment.c static int __init alignment_init(void) · line 975

Quoted 13 lines
arch/arm/mm/alignment.c +2 -0
 static int safe_usermode(int new_usermode, bool warn)

@@ -961,12 +965,14 @@ static int __init alignment_init(void)
 		return -ENOMEM;
 #endif
 
+#ifdef CONFIG_CPU_CP15
 	if (cpu_is_v6_unaligned()) {
 		cr_alignment &= ~CR_A;
 		cr_no_alignment &= ~CR_A;
 		set_cr(cr_alignment);
 		ai_usermode = safe_usermode(ai_usermode, false);
 	}
+#endif

Here the #ifdef is probably legitimate.

Quoted 7 lines
arch/arm/mm/alignment.c +0 -0
 	hook_fault_code(FAULT_CODE_ALIGNMENT, do_alignment, SIGBUS, BUS_ADRALN,
 			"alignment exception");
arch/arm/mm/mmu.c +0 -0
index 94c5a0c..f6dbe1a 100644

arch/arm/mm/mmu.c static int __init early_cachepolicy(char *p) · line 115

Quoted 7 lines
arch/arm/mm/mmu.c +2 -0
@@ -109,8 +109,10 @@ static int __init early_cachepolicy(char *p)
 
 		if (memcmp(p, cache_policies[i].policy, len) == 0) {
 			cachepolicy = i;
+#ifdef CONFIG_CPU_CP15
 			cr_alignment &= ~cache_policies[i].cr_mask;
 			cr_no_alignment &= ~cache_policies[i].cr_mask;
+#endif

Probably here as well.

arch/arm/mm/mmu.c static int __init early_cachepolicy(char *p) · line 135

Quoted 10 lines
arch/arm/mm/mmu.c +2 -0
 			break;
 		}
 	}

@@ -128,7 +130,9 @@ static int __init early_cachepolicy(char *p)
 		cachepolicy = CPOLICY_WRITEBACK;
 	}
 	flush_cache_all();
+#ifdef CONFIG_CPU_CP15
 	set_cr(cr_alignment);
+#endif

However it might be best to provide a dummy set_cr() instead of #ifdef'ing it out everywhere.

Nicolas

author
#3 lore raw

PATCH v3 1/5 ARM: protect usage of cr_alignment by #ifdef CONFIG_CPU_CP15

Quoted 10 lines · Nicolas Pitre
Quoted 1 line · Uwe Kleine-K?nig
Signed-off-by Uwe Kleine-K?nig <[email protected]>

I think you could reduce the amount of #ifdef's significantly here. While the cr_alignment variable and its sister are of no use in a no-CP15 system, you could still leave them there initialized to zero and only conditionally compile out the CP15 modifyers with a dummy version. This is only 2 words wasted in your kernel image to keep the code cleaner.

The main purpose to create this patch is that for v7m I don't compile entry-armv.S. As cr_alignment is defined there I don't "have" this variable. So I have to move the definition to a different file to waste it :-)

Quoted 18 lines

More comments below.

arch/arm/kernel/head-common.S __mmap_switched: · line 104

Quoted 13 lines

index 854bd22..efeb2d0 100644

arch/arm/kernel/head-common.S +4 -2
@@ -98,8 +98,10 @@ __mmap_switched:
 	str	r9, [r4]			@ Save processor ID
 	str	r1, [r5]			@ Save machine type
 	str	r2, [r6]			@ Save atags pointer
-	bic	r4, r0, #CR_A			@ Clear 'A' bit
-	stmia	r7, {r0, r4}			@ Save control register values
+	cmp	r7, #0
+	itt	ne
+	bicne	r4, r0, #CR_A			@ Clear 'A' bit
+	stmneia	r7, {r0, r4}			@ Save control register values

The kernel is compiled with -mimplicit-it so you do not need to specify any it here.

ok

Quoted 7 lines
Quoted 7 lines

index a255c39..50d3df8 100644

arch/arm/kernel/setup.c +0 -0
@@ -472,9 +472,13 @@ static void __init setup_processor(void)
 	cpu_cache = *list->cache;
 #endif
Quoted 13 lines

arch/arm/kernel/setup.c static void __init setup_processor(void) · line 482

Quoted 10 lines
arch/arm/kernel/setup.c +6 -2
-	printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
+	printk("CPU: %s [%08x] revision %d (ARMv%s)",
 	       cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
-	       proc_arch[cpu_architecture()], cr_alignment);
+	       proc_arch[cpu_architecture()]);
+
+#ifdef CONFIG_CPU_CP15
+	printk(KERN_CONT ", cr=%08lx\n", cr_alignment);
+#endif

Again, you could just leave the original display, with cr=00000000 which is a fairly good representation of reality.

Maybe having

	#define cr_alignment 0

for the !CONFIG_CPU_CP15 case would be a nice alternative. This way all places that want to modify cr_alignment fail to compile, but reading gives a "fairly good representation of reality".

Having said that I'm not sure about "fairly good". v7m also supports unaligned accesses. But it's not configured in a cp15 register (obviously) but in a system register. Quoting ARMARM-v7m:

Configuration and Control Register, CCR
[...]
Bit [3] UNALIGN_TRP Controls the trapping of unaligned word or
halfword accesses:
0 = Trapping disabled.
1 = Trapping enabled. Unaligned load-store multiples and word or halfword exclusive accesses always fault.

So we need a more general abstraction to have correct and clean code?

But note I didn't check the two different implementations deeply to be sure not to compare two different things.

Quoted 51 lines
Quoted 5 lines
arch/arm/mm/alignment.c +0 -0
index caf14dc..119d178 100644

arch/arm/mm/alignment.c core_param(alignment, ai_usermode, int, 0600); · line 97

Quoted 9 lines
arch/arm/mm/alignment.c +4 -0
@@ -89,7 +89,11 @@ core_param(alignment, ai_usermode, int, 0600);
 /* Return true if and only if the ARMv6 unaligned access model is in use. */
 static bool cpu_is_v6_unaligned(void)
 {
+#ifdef CONFIG_CPU_CP15
 	return cpu_architecture() >= CPU_ARCH_ARMv6 && (cr_alignment & CR_U);
+#else
+	return 0;
+#endif
 }

Same here. With cr_alignment set to zero, you don't need the above #ifdef.

arch/arm/mm/alignment.c static int __init alignment_init(void) · line 975

Quoted 13 lines
arch/arm/mm/alignment.c +2 -0
 static int safe_usermode(int new_usermode, bool warn)

@@ -961,12 +965,14 @@ static int __init alignment_init(void)
 		return -ENOMEM;
 #endif
 
+#ifdef CONFIG_CPU_CP15
 	if (cpu_is_v6_unaligned()) {
 		cr_alignment &= ~CR_A;
 		cr_no_alignment &= ~CR_A;
 		set_cr(cr_alignment);
 		ai_usermode = safe_usermode(ai_usermode, false);
 	}
+#endif

Here the #ifdef is probably legitimate.

Quoted 7 lines
arch/arm/mm/alignment.c +0 -0
 	hook_fault_code(FAULT_CODE_ALIGNMENT, do_alignment, SIGBUS, BUS_ADRALN,
 			"alignment exception");
arch/arm/mm/mmu.c +0 -0
index 94c5a0c..f6dbe1a 100644

arch/arm/mm/mmu.c static int __init early_cachepolicy(char *p) · line 115

Quoted 7 lines
arch/arm/mm/mmu.c +2 -0
@@ -109,8 +109,10 @@ static int __init early_cachepolicy(char *p)
 
 		if (memcmp(p, cache_policies[i].policy, len) == 0) {
 			cachepolicy = i;
+#ifdef CONFIG_CPU_CP15
 			cr_alignment &= ~cache_policies[i].cr_mask;
 			cr_no_alignment &= ~cache_policies[i].cr_mask;
+#endif

Probably here as well.

Quoted 13 lines

arch/arm/mm/mmu.c static int __init early_cachepolicy(char *p) · line 135

Quoted 10 lines
arch/arm/mm/mmu.c +2 -0
 			break;
 		}
 	}

@@ -128,7 +130,9 @@ static int __init early_cachepolicy(char *p)
 		cachepolicy = CPOLICY_WRITEBACK;
 	}
 	flush_cache_all();
+#ifdef CONFIG_CPU_CP15
 	set_cr(cr_alignment);
+#endif

However it might be best to provide a dummy set_cr() instead of #ifdef'ing it out everywhere.

What should the dummy set_cr do? Print a runtime warning if called with != 0?

Best regards
Uwe

Signature · 2 lines
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
#4 lore raw

PATCH v3 1/5 ARM: protect usage of cr_alignment by #ifdef CONFIG_CPU_CP15

Quoted 10 lines · Uwe Kleine-K?nig
Quoted 2 lines · Nicolas Pitre

Again, you could just leave the original display, with cr=00000000 which is a fairly good representation of reality.

Maybe having

	#define cr_alignment 0

for the !CONFIG_CPU_CP15 case would be a nice alternative. This way all places that want to modify cr_alignment fail to compile, but reading gives a "fairly good representation of reality".

Even better, yes.

Quoted 3 lines

Having said that I'm not sure about "fairly good". v7m also supports unaligned accesses. But it's not configured in a cp15 register (obviously) but in a system register.

Hence having a "control register" displaying as zero is still fairly good.

Quoted 12 lines

Quoting ARMARM-v7m:

Configuration and Control Register, CCR
[...]
Bit [3] UNALIGN_TRP Controls the trapping of unaligned word or
halfword accesses:
0 = Trapping disabled.
1 = Trapping enabled. Unaligned load-store multiples and word or halfword exclusive accesses always fault.

Quoted 1 line

So we need a more general abstraction to have correct and clean code?

In the context of the alignment trap code, yes. Maybe on v7m there is no point having the alignment trap disabled at all. It's been almost forever that gcc is not relying on the side effect of misaligned accesses anymore.

Quoted 9 lines
Quoted 7 lines

arch/arm/mm/mmu.c static int __init early_cachepolicy(char *p) · line 135

Quoted 4 lines
arch/arm/mm/mmu.c +2 -0
 	flush_cache_all();
+#ifdef CONFIG_CPU_CP15
 	set_cr(cr_alignment);
+#endif

However it might be best to provide a dummy set_cr() instead of #ifdef'ing it out everywhere.

What should the dummy set_cr do? Print a runtime warning if called with != 0?

Maybe not. In fact if that code path is used, then something might be wrong at a higher level.

Nicolas

author
#5 lore raw

PATCH v3 1/5 ARM: protect usage of cr_alignment by #ifdef CONFIG_CPU_CP15

Hello Nicolas,

Quoted 9 lines · Nicolas Pitre
Quoted 8 lines · Uwe Kleine-K?nig
Quoted 7 lines · Nicolas Pitre

arch/arm/mm/mmu.c static int __init early_cachepolicy(char *p) · line 135

Quoted 4 lines
arch/arm/mm/mmu.c +2 -0
 	flush_cache_all();
+#ifdef CONFIG_CPU_CP15
 	set_cr(cr_alignment);
+#endif

However it might be best to provide a dummy set_cr() instead of #ifdef'ing it out everywhere.

Quoted 5 lines
Quoted 2 lines

What should the dummy set_cr do? Print a runtime warning if called with != 0?

Maybe not. In fact if that code path is used, then something might be wrong at a higher level.

And that's why I choosed not to implement a dummy set_cr ...

Best regards
Uwe

Signature · 2 lines
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
author
#6 lore raw

PATCH v3 2/5 ARM: Add a printk loglevel modifier

In reply to Uwe Kleine-König

This is a needed followup for

ARM: protect usage of cr_alignment by #ifdef CONFIG_CPU_CP15

otherwise no newline is printed for !CONFIG_CPU_CP15

Signed-off-by Uwe Kleine-K?nig <[email protected]>

---
Should this be folded into the

ARM: protect usage of cr_alignment by #ifdef CONFIG_CPU_CP15

patch? Or should it come before it?

 arch/arm/kernel/setup.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
arch/arm/kernel/setup.c +1 -1
index 50d3df8..23893b1 100644
@@ -325,7 +325,7 @@ static void __init cacheid_init(void)
 		cacheid = CACHEID_VIVT;
 	}
 
-	printk("CPU: %s data cache, %s instruction cache\n",
+	printk(KERN_INFO "CPU: %s data cache, %s instruction cache\n",
 		cache_is_vivt() ? "VIVT" :
 		cache_is_vipt_aliasing() ? "VIPT aliasing" :
 		cache_is_vipt_nonaliasing() ? "PIPT / VIPT nonaliasing" : "unknown",
Signature · 1 line
1.7.9.1
#7 lore raw

PATCH v3 2/5 ARM: Add a printk loglevel modifier

Quoted 6 lines · Uwe Kleine-K?nig

This is a needed followup for

ARM: protect usage of cr_alignment by #ifdef CONFIG_CPU_CP15

otherwise no newline is printed for !CONFIG_CPU_CP15

Quoted 8 lines
Signed-off-by Uwe Kleine-K?nig <[email protected]>

---
Should this be folded into the

ARM: protect usage of cr_alignment by #ifdef CONFIG_CPU_CP15

patch? Or should it come before it?

I think this patch needs a better explanation. It looks to me that it's simply a bug fix, because every printk that is not a continuation of a previous printk needs a KERN_* line. In that case, it should just get applied as a bug fix independent of the other patches.

However, if you sometimes don't have a newline after the previous printk, this patch is actually wrong and should not get applied at all.

Arnd

author
#8 lore raw

PATCH v3 2/5 ARM: Add a printk loglevel modifier

Quoted 16 lines · Arnd Bergmann
Quoted 6 lines · Uwe Kleine-K?nig

This is a needed followup for

ARM: protect usage of cr_alignment by #ifdef CONFIG_CPU_CP15

otherwise no newline is printed for !CONFIG_CPU_CP15

Quoted 8 lines
Signed-off-by Uwe Kleine-K?nig <[email protected]>

---
Should this be folded into the

ARM: protect usage of cr_alignment by #ifdef CONFIG_CPU_CP15

patch? Or should it come before it?

Quoted 8 lines

I think this patch needs a better explanation. It looks to me that it's simply a bug fix, because every printk that is not a continuation of a previous printk needs a KERN_* line. In that case, it should just get applied as a bug fix independent of the other patches.

However, if you sometimes don't have a newline after the previous printk, this patch is actually wrong and should not get applied at all.

I don't get your reasoning here.

An (independant) printk (that is expected to start at a new line) must start with KERN_SOMETHING iff the previous printk always ends in \n? Probably not.

Independently of the correctness of the first patch that splits the printk I'm just taking it as an example:

In this case the two printks in question are:

		printk("CPU: %s [%08x] revision %d (ARMv%s)", ...);
	#ifdef CONFIG_CPU_CP15
		printk(KERN_CONT ", cr=%08lx\n", cr_alignment);
	#endif

and

printk("CPU: %s data cache, %s instruction cache\n", ...)

In this case it's correct to add KERN_INFO to the last printk, isn't it? When would you consider it to be wrong?

If you want to have the first group of printks to always end in \n, I'd have to do:

		printk("CPU: %s [%08x] revision %d (ARMv%s)", ...);
	#ifdef CONFIG_CPU_CP15
		printk(KERN_CONT ", cr=%08lx", cr_alignment);
	#endif
		printk(KERN_CONT "\n");

but ISTR Linus (Torvalds) telling me that KERN_CONT "\n" is wrong and should just be skipped.

Best regards
Uwe

Signature · 2 lines
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
#9 lore raw

PATCH v3 2/5 ARM: Add a printk loglevel modifier

Quoted 16 lines · Uwe Kleine-K?nig

I don't get your reasoning here.

An (independant) printk (that is expected to start at a new line) must start with KERN_SOMETHING iff the previous printk always ends in \n? Probably not.

Independently of the correctness of the first patch that splits the printk I'm just taking it as an example:

In this case the two printks in question are:

                printk("CPU: %s [%08x] revision %d (ARMv%s)", ...);
        #ifdef CONFIG_CPU_CP15
                printk(KERN_CONT ", cr=%08lx\n", cr_alignment);
        #endif
Quoted 6 lines

and

printk("CPU: %s data cache, %s instruction cache\n", ...)

In this case it's correct to add KERN_INFO to the last printk, isn't it? When would you consider it to be wrong?

I forgot about KERN_CONT, which did not exist until a few years ago and is still not all that common. Initially, KERN_CONT was just an empty string that was used to make it clear when a printk was intentionally used as a continuation of the previous line, rather than having no KERN_* at all.

In the example above, the first and the second line should get a KERN_INFO or one of the others.

Quoted 11 lines

If you want to have the first group of printks to always end in \n, I'd have to do:

                printk("CPU: %s [%08x] revision %d (ARMv%s)", ...);
        #ifdef CONFIG_CPU_CP15
                printk(KERN_CONT ", cr=%08lx", cr_alignment);
        #endif
                printk(KERN_CONT "\n");

but ISTR Linus (Torvalds) telling me that KERN_CONT "\n" is wrong and should just be skipped.

Ok, didn't know that.

Arnd

#10 lore raw

PATCH v3 2/5 ARM: Add a printk loglevel modifier

In reply to Uwe Kleine-König
Quoted 6 lines · Uwe Kleine-K?nig

This is a needed followup for

ARM: protect usage of cr_alignment by #ifdef CONFIG_CPU_CP15

otherwise no newline is printed for !CONFIG_CPU_CP15

Quoted 7 lines
Signed-off-by Uwe Kleine-K?nig <[email protected]>

---
Should this be folded into the

ARM: protect usage of cr_alignment by #ifdef CONFIG_CPU_CP15

patch? Or should it come before it?

Given my comments on that other patch, this one could be dropped altogether.

Nicolas

author
#11 lore raw

PATCH v3 3/5 ARM: force branch instructions to use long distance encoding

In reply to Uwe Kleine-König

This fixes a linker error when the kernel image gets bigger than approx. 1 MiB.

This is done analogous to the change to head.S in commit

a75e524 (ARM: 6504/1: Thumb-2: Fix long-distance conditional branches in head.S for Thumb-2.)

Signed-off-by Uwe Kleine-K?nig <[email protected]>
---
 arch/arm/kernel/head-nommu.S |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)
arch/arm/kernel/head-nommu.S +1 -0
index d46f259..1aca35d 100644
@@ -51,6 +51,7 @@ ENTRY(stext)
 #endif
 	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
 	movs	r10, r5				@ invalid processor (r5=0)?
+	it	eq
 	beq	__error_p				@ yes, error 'p'
 
 	adr	lr, BSYM(__after_proc_init)	@ return (PIC) address
Signature · 1 line
1.7.9.1
#12 lore raw

PATCH v3 3/5 ARM: force branch instructions to use long distance encoding

Quoted 6 lines · Uwe Kleine-K?nig

This fixes a linker error when the kernel image gets bigger than approx. 1 MiB.

This is done analogous to the change to head.S in commit

	a75e524 (ARM: 6504/1: Thumb-2: Fix long-distance conditional

branches in head.S for Thumb-2.)

Quoted 11 lines
Signed-off-by Uwe Kleine-K?nig <[email protected]>
---
 arch/arm/kernel/head-nommu.S |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)
arch/arm/kernel/head-nommu.S +0 -0
index d46f259..1aca35d 100644

arch/arm/kernel/head-nommu.S ENTRY(stext) · line 54

Quoted 4 lines
arch/arm/kernel/head-nommu.S +1 -0
@@ -51,6 +51,7 @@ ENTRY(stext)
 #endif
 	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
 	movs	r10, r5				@ invalid processor (r5=0)?
+	it	eq

Like in the other cases, please add a short comment on that line justifying it, otherwise it may look redundant.

Nicolas

author
#13 lore raw

PATCH v3 4/5 Cortex-M3: Add base support for Cortex-M3

In reply to Uwe Kleine-König

From: Catalin Marinas <[email protected]>

This patch adds the base support for the Cortex-M3 processor (ARMv7-M architecture). It consists of the corresponding arch/arm/mm/ files and various #ifdef's around the kernel. Exception handling is implemented by a subsequent patch.

[ukleinek: squash in some changes originating from commit

b5717ba (Cortex-M3: Add support for the Microcontroller Prototyping System)

from the v2.6.33-arm1 patch stack, port to post 3.2, drop zImage support, drop reorganisation of pt_regs, and a few cosmetic changes]

Signed-off-by Catalin Marinas <[email protected]>
Signed-off-by Uwe Kleine-K?nig <[email protected]>
---
 arch/arm/include/asm/assembler.h  |   13 +++-
 arch/arm/include/asm/cputype.h    |    3 +
 arch/arm/include/asm/glue-cache.h |   24 ++++++
 arch/arm/include/asm/glue-df.h    |    8 ++
 arch/arm/include/asm/glue-proc.h  |    9 ++
 arch/arm/include/asm/irqflags.h   |   51 +++++++++++-
 arch/arm/include/asm/processor.h  |    7 ++
 arch/arm/include/asm/ptrace.h     |   20 +++++-
 arch/arm/include/asm/system.h     |    3 +
 arch/arm/kernel/asm-offsets.c     |    3 +
 arch/arm/kernel/head-nommu.S      |    9 ++-
 arch/arm/kernel/setup.c           |   13 +++-
 arch/arm/kernel/traps.c           |    2 +
 arch/arm/mm/nommu.c               |    2 +
 arch/arm/mm/proc-v7m.S            |  161 +++++++++++++++++++++++++++++++++++++
 15 files changed, 320 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/mm/proc-v7m.S
arch/arm/include/asm/assembler.h +12 -1
index 23371b1..51f3ff7 100644
@@ -133,7 +133,11 @@
  * assumes FIQs are enabled, and that the processor is in SVC mode.
  */
 	.macro	save_and_disable_irqs, oldcpsr
+#ifdef CONFIG_CPU_V7M
+	mrs	\oldcpsr, primask
+#else
 	mrs	\oldcpsr, cpsr
+#endif
 	disable_irq
 	.endm
 

@@ -147,7 +151,11 @@
  * guarantee that this will preserve the flags.
  */
 	.macro	restore_irqs_notrace, oldcpsr
+#ifdef CONFIG_CPU_V7M
+	msr	primask, \oldcpsr
+#else
 	msr	cpsr_c, \oldcpsr
+#endif
 	.endm
 
 	.macro restore_irqs, oldcpsr

@@ -226,7 +234,10 @@
 #endif
 	.endm
 
-#ifdef CONFIG_THUMB2_KERNEL
+#if defined(CONFIG_CPU_V7M)
+	.macro	setmode, mode, reg
+	.endm
+#elif defined(CONFIG_THUMB2_KERNEL)
 	.macro	setmode, mode, reg
 	mov	\reg, #\mode
 	msr	cpsr_c, \reg
arch/arm/include/asm/cputype.h +3 -0
index cb47d28..5bd8cb6 100644
@@ -46,6 +46,9 @@ extern unsigned int processor_id;
 		    : "cc");						\
 		__val;							\
 	})
+#elif defined(CONFIG_CPU_V7M)
+#define read_cpuid(reg) (*(unsigned int *)0xe000ed00)
+#define read_cpuid_ext(reg) 0
 #else
 #define read_cpuid(reg) (processor_id)
 #define read_cpuid_ext(reg) 0
arch/arm/include/asm/glue-cache.h +24 -0
index 7e30874..6a5fd0b 100644
@@ -125,10 +125,34 @@
 //# endif
 #endif
 
+#if defined(CONFIG_CPU_V7M)
+# ifdef _CACHE
+#  error "Multi-cache not supported on ARMv7-M"
+# else
+#  define _CACHE nop
+# endif
+#endif
+
 #if !defined(_CACHE) && !defined(MULTI_CACHE)
 #error Unknown cache maintenance model
 #endif
 
+#ifndef __ASSEMBLER__
+static inline void nop_flush_icache_all(void) { }
+static inline void nop_flush_kern_cache_all(void) { }
+static inline void nop_flush_user_cache_all(void) { }
+static inline void nop_flush_user_cache_range(unsigned long a, unsigned long b, unsigned int c) { }
+
+static inline void nop_coherent_kern_range(unsigned long a, unsigned long b) { }
+static inline void nop_coherent_user_range(unsigned long a, unsigned long b) { }
+static inline void nop_flush_kern_dcache_area(void *a, size_t s) { }
+
+static inline void nop_dma_flush_range(const void *a, const void *b) { }
+
+static inline void nop_dma_map_area(const void *s, size_t l, int f) { }
+static inline void nop_dma_unmap_area(const void *s, size_t l, int f) { }
+#endif
+
 #ifndef MULTI_CACHE
 #define __cpuc_flush_icache_all		__glue(_CACHE,_flush_icache_all)
 #define __cpuc_flush_kern_all		__glue(_CACHE,_flush_kern_cache_all)
arch/arm/include/asm/glue-df.h +8 -0
index 354d571..26be71c 100644
@@ -103,6 +103,14 @@
 # endif
 #endif
 
+#ifdef CONFIG_CPU_ABRT_NOMMU
+# ifdef CPU_DABORT_HANDLER
+#  define MULTI_DABORT 1
+# else
+#  define CPU_DABORT_HANDLER nommu_early_abort
+# endif
+#endif
+
 #ifndef CPU_DABORT_HANDLER
 #error Unknown data abort handler type
 #endif
arch/arm/include/asm/glue-proc.h +9 -0
index e2be7f1..8f9991b 100644
@@ -248,6 +248,15 @@
 # endif
 #endif
 
+#ifdef CONFIG_CPU_V7M
+# ifdef CPU_NAME
+#  undef  MULTI_CPU
+#  define MULTI_CPU
+# else
+#  define CPU_NAME cpu_v7m
+# endif
+#endif
+
 #ifndef MULTI_CPU
 #define cpu_proc_init			__glue(CPU_NAME,_proc_init)
 #define cpu_proc_fin			__glue(CPU_NAME,_proc_fin)
arch/arm/include/asm/irqflags.h +49 -2

72 lines not on this page · raw message

arch/arm/include/asm/processor.h +7 -0
index cb8d638..2c22bcc 100644
@@ -50,7 +50,14 @@ struct thread_struct {
 #ifdef CONFIG_MMU
 #define nommu_start_thread(regs) do { } while (0)
 #else
+#ifndef CONFIG_CPU_V7M
 #define nommu_start_thread(regs) regs->ARM_r10 = current->mm->start_data
+#else
+#define nommu_start_thread(regs) do {					\
+	regs->ARM_r10 = current->mm->start_data;			\
+	regs->ARM_EXC_RET = 0xfffffffdL;				\
+} while (0)
+#endif
 #endif
 
 #define start_thread(regs,pc,sp)					\
arch/arm/include/asm/ptrace.h +19 -1
index 451808b..696bbf4 100644
@@ -39,16 +39,25 @@
 #define FIQ26_MODE	0x00000001
 #define IRQ26_MODE	0x00000002
 #define SVC26_MODE	0x00000003
+#ifndef CONFIG_CPU_V7M
 #define USR_MODE	0x00000010
+#define SVC_MODE	0x00000013
+#else
+#define USR_MODE	0x00000000
+#define SVC_MODE	0x00000000
+#endif
 #define FIQ_MODE	0x00000011
 #define IRQ_MODE	0x00000012
-#define SVC_MODE	0x00000013
 #define ABT_MODE	0x00000017
 #define UND_MODE	0x0000001b
 #define SYSTEM_MODE	0x0000001f
 #define MODE32_BIT	0x00000010
 #define MODE_MASK	0x0000001f
+#ifndef CONFIG_CPU_V7M
 #define PSR_T_BIT	0x00000020
+#else
+#define PSR_T_BIT	0x01000000
+#endif
 #define PSR_F_BIT	0x00000040
 #define PSR_I_BIT	0x00000080
 #define PSR_A_BIT	0x00000100

@@ -106,7 +115,11 @@ struct pt_regs {
 };
 #else /* __KERNEL__ */
 struct pt_regs {
+#ifdef CONFIG_CPU_V7M
+	unsigned long uregs[20];
+#else
 	unsigned long uregs[18];
+#endif
 };
 #endif /* __KERNEL__ */
 

@@ -128,6 +141,7 @@ struct pt_regs {
 #define ARM_r1		uregs[1]
 #define ARM_r0		uregs[0]
 #define ARM_ORIG_r0	uregs[17]
+#define ARM_EXC_RET	uregs[18]
 
 /*
  * The size of the user-visible VFP state as seen by PTRACE_GET/SETVFPREGS

@@ -165,6 +179,7 @@ struct pt_regs {
  */
 static inline int valid_user_regs(struct pt_regs *regs)
 {
+#ifndef CONFIG_CPU_V7M
 	unsigned long mode = regs->ARM_cpsr & MODE_MASK;
 
 	/*

@@ -187,6 +202,9 @@ static inline int valid_user_regs(struct pt_regs *regs)
 		regs->ARM_cpsr |= USR_MODE;
 
 	return 0;
+#else /* ifndef CONFIG_CPU_V7M */
+	return 1;
+#endif
 }
 
 static inline long regs_return_value(struct pt_regs *regs)
arch/arm/include/asm/system.h +3 -0
index de46477..16117ed 100644
@@ -13,6 +13,7 @@
 #define CPU_ARCH_ARMv5TEJ	7
 #define CPU_ARCH_ARMv6		8
 #define CPU_ARCH_ARMv7		9
+#define CPU_ARCH_ARMv7M		10
 
 /*
  * CR1 bits (CP#15 CR1)

@@ -232,7 +233,9 @@ static inline void set_copro_access(unsigned int val)
  * so enable interrupts over the context switch to avoid high
  * latency.
  */
+#ifndef CONFIG_CPU_V7M
 #define __ARCH_WANT_INTERRUPTS_ON_CTXSW
+#endif
 
 /*
  * switch_to(prev, next) should switch from task `prev' to `next'
arch/arm/kernel/asm-offsets.c +3 -0
index 1429d89..6f6b5b6 100644
@@ -91,6 +91,9 @@ int main(void)
   DEFINE(S_PC,			offsetof(struct pt_regs, ARM_pc));
   DEFINE(S_PSR,			offsetof(struct pt_regs, ARM_cpsr));
   DEFINE(S_OLD_R0,		offsetof(struct pt_regs, ARM_ORIG_r0));
+#ifdef CONFIG_CPU_V7M
+  DEFINE(S_EXC_RET,		offsetof(struct pt_regs, ARM_EXC_RET));
+#endif
   DEFINE(S_FRAME_SIZE,		sizeof(struct pt_regs));
   BLANK();
 #ifdef CONFIG_CACHE_L2X0
arch/arm/kernel/head-nommu.S +6 -3
index 1aca35d..61ba029 100644
@@ -44,10 +44,13 @@ ENTRY(stext)
 
 	setmode	PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
 						@ and irqs disabled
-#ifndef CONFIG_CPU_CP15
-	ldr	r9, =CONFIG_PROCESSOR_ID
-#else
+#if defined(CONFIG_CPU_CP15)
 	mrc	p15, 0, r9, c0, c0		@ get processor id
+#elif defined(CONFIG_CPU_V7M)
+	ldr	r9, =0xe000ed00			@ CPUID register address
+	ldr	r9, [r9]
+#else
+	ldr	r9, =CONFIG_PROCESSOR_ID
 #endif
 	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
 	movs	r10, r5				@ invalid processor (r5=0)?
arch/arm/kernel/setup.c +12 -1
index 23893b1..d0fc5b8 100644
@@ -132,7 +132,9 @@ struct stack {
 	u32 und[3];
 } ____cacheline_aligned;
 
+#ifndef CONFIG_CPU_V7M
 static struct stack stacks[NR_CPUS];
+#endif
 
 char elf_platform[ELF_PLATFORM_SIZE];
 EXPORT_SYMBOL(elf_platform);

@@ -212,7 +214,7 @@ static const char *proc_arch[] = {
 	"5TEJ",
 	"6TEJ",
 	"7",
-	"?(11)",
+	"7M",
 	"?(12)",
 	"?(13)",
 	"?(14)",

@@ -221,6 +223,12 @@ static const char *proc_arch[] = {
 	"?(17)",
 };
 
+#ifdef CONFIG_CPU_V7M
+static int __get_cpu_architecture(void)
+{
+	return CPU_ARCH_ARMv7M;
+}
+#else
 static int __get_cpu_architecture(void)
 {
 	int cpu_arch;

@@ -253,6 +261,7 @@ static int __get_cpu_architecture(void)
 
 	return cpu_arch;
 }
+#endif
 
 int __pure cpu_architecture(void)
 {

@@ -380,6 +389,7 @@ static void __init feat_v6_fixup(void)
  */
 void cpu_init(void)
 {
+#ifndef CONFIG_CPU_V7M
 	unsigned int cpu = smp_processor_id();
 	struct stack *stk = &stacks[cpu];
 

@@ -424,6 +434,7 @@ void cpu_init(void)
 	      "I" (offsetof(struct stack, und[0])),
 	      PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
 	    : "r14");
+#endif
 }
 
 int __cpu_logical_map[NR_CPUS];
arch/arm/kernel/traps.c +2 -0
index f84dfe6..ce7a624 100644
@@ -786,6 +786,7 @@ static void __init kuser_get_tls_init(unsigned long vectors)
 
 void __init early_trap_init(void)
 {
+#ifndef CONFIG_CPU_V7M
 #if defined(CONFIG_CPU_USE_DOMAINS)
 	unsigned long vectors = CONFIG_VECTORS_BASE;
 #else

@@ -821,4 +822,5 @@ void __init early_trap_init(void)
 
 	flush_icache_range(vectors, vectors + PAGE_SIZE);
 	modify_domain(DOMAIN_USER, DOMAIN_CLIENT);
+#endif
 }
arch/arm/mm/nommu.c +2 -0
index 4fc6794..fdd49ac 100644
@@ -19,12 +19,14 @@
 
 void __init arm_mm_memblock_reserve(void)
 {
+#ifndef CONFIG_CPU_V7M
 	/*
 	 * Register the exception vector page.
 	 * some architectures which the DRAM is the exception vector to trap,
 	 * alloc_page breaks with error, although it is not NULL, but "0."
 	 */
 	memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE);
+#endif
 }
 
 void __init sanity_check_meminfo(void)
arch/arm/mm/proc-v7m.S new file +161 -0

161 lines not on this page · raw message

Signature · 1 line
1.7.9.1
author
#14 lore raw

PATCH v3 5/5 Cortex-M3: Add support for exception handling

In reply to Uwe Kleine-König

This patch implements the exception handling for the ARMv7-M architecture (pretty different from the A or R profiles).

It bases on work done earlier by Catalin for 2.6.33 but was nearly completely rewritten to use a pt_regs layout compatible to the A profile.

Signed-off-by Catalin Marinas <[email protected]>
Signed-off-by Uwe Kleine-K?nig <[email protected]>
---
 arch/arm/kernel/entry-common.S |    4 +
 arch/arm/kernel/entry-header.S |  148 ++++++++++++++++++++++++++++++++++++++++
 arch/arm/kernel/entry-v7m.S    |  134 ++++++++++++++++++++++++++++++++++++
 arch/arm/kernel/process.c      |    8 ++
 arch/arm/kernel/ptrace.c       |    3 +
 arch/arm/kernel/signal.c       |   13 ++++
 arch/arm/kernel/sys_arm.c      |    1 +
 7 files changed, 311 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/kernel/entry-v7m.S
arch/arm/kernel/entry-common.S +4 -0
index 9fd0ba9..cf54fd1 100644
@@ -345,6 +345,9 @@ ENDPROC(ftrace_stub)
 
 	.align	5
 ENTRY(vector_swi)
+#ifdef CONFIG_CPU_V7M
+	v7m_exception_entry
+#else
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}			@ Calling r0 - r12
  ARM(	add	r8, sp, #S_PC		)

@@ -355,6 +358,7 @@ ENTRY(vector_swi)
 	str	lr, [sp, #S_PC]			@ Save calling PC
 	str	r8, [sp, #S_PSR]		@ Save CPSR
 	str	r0, [sp, #S_OLD_R0]		@ Save OLD_R0
+#endif
 	zero_fp
 
 	/*
arch/arm/kernel/entry-header.S +148 -0

166 lines not on this page · raw message

arch/arm/kernel/entry-v7m.S new file +134 -0

134 lines not on this page · raw message

arch/arm/kernel/process.c +8 -0
index 971d65c..38d9fde 100644
@@ -452,7 +452,11 @@ asm(	".pushsection .text\n"
 #ifdef CONFIG_TRACE_IRQFLAGS
 "	bl	trace_hardirqs_on\n"
 #endif
+#ifdef CONFIG_CPU_V7M
+"	msr	primask, r7\n"
+#else
 "	msr	cpsr_c, r7\n"
+#endif
 "	mov	r0, r4\n"
 "	mov	lr, r6\n"
 "	mov	pc, r5\n"

@@ -491,6 +495,10 @@ pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
 	regs.ARM_r7 = SVC_MODE | PSR_ENDSTATE | PSR_ISETSTATE;
 	regs.ARM_pc = (unsigned long)kernel_thread_helper;
 	regs.ARM_cpsr = regs.ARM_r7 | PSR_I_BIT;
+#if defined CONFIG_CPU_V7M
+	/* Return to Handler mode */
+	regs.ARM_EXC_RET = 0xfffffff1L;
+#endif
 
 	return do_fork(flags|CLONE_VM|CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
 }
arch/arm/kernel/ptrace.c +3 -0
index ede6443..97611fd 100644
@@ -83,6 +83,9 @@ static const struct pt_regs_offset regoffset_table[] = {
 	REG_OFFSET_NAME(pc),
 	REG_OFFSET_NAME(cpsr),
 	REG_OFFSET_NAME(ORIG_r0),
+#ifdef CONFIG_CPU_V7M
+	REG_OFFSET_NAME(EXC_RET),
+#endif
 	REG_OFFSET_END,
 };
arch/arm/kernel/signal.c +13 -0
index 9e617bd..38a6585 100644
@@ -277,6 +277,8 @@ static int restore_sigframe(struct pt_regs *regs, struct sigframe __user *sf)
 	sigset_t set;
 	int err;
 
+	pr_info("%s(regs=%p)\n", __func__, regs);
+
 	err = __copy_from_user(&set, &sf->uc.uc_sigmask, sizeof(set));
 	if (err == 0) {
 		sigdelsetmask(&set, ~_BLOCKABLE);

@@ -327,6 +329,7 @@ asmlinkage int sys_sigreturn(struct pt_regs *regs)
 {
 	struct sigframe __user *frame;
 
+	pr_info("%s(regs=%p)\n", __func__, regs);
 	/* Always make any pending restarted system calls return -EINTR */
 	current_thread_info()->restart_block.fn = do_no_restart_syscall;
 

@@ -357,6 +360,7 @@ asmlinkage int sys_rt_sigreturn(struct pt_regs *regs)
 {
 	struct rt_sigframe __user *frame;
 
+	pr_info("%s(regs=%p)\n", __func__, regs);
 	/* Always make any pending restarted system calls return -EINTR */
 	current_thread_info()->restart_block.fn = do_no_restart_syscall;
 

@@ -441,6 +445,7 @@ get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, int framesize)
 	unsigned long sp = regs->ARM_sp;
 	void __user *frame;
 
+	pr_info("%s(regs=%p)\n", __func__, regs);
 	/*
 	 * This is the X/Open sanctioned signal stack switching.
 	 */

@@ -470,6 +475,8 @@ setup_return(struct pt_regs *regs, struct k_sigaction *ka,
 	int thumb = 0;
 	unsigned long cpsr = regs->ARM_cpsr & ~(PSR_f | PSR_E_BIT);
 
+	pr_info("%s(regs=%p)\n", __func__, regs);
+
 	cpsr |= PSR_ENDSTATE;
 
 	/*

@@ -542,6 +549,8 @@ setup_frame(int usig, struct k_sigaction *ka, sigset_t *set, struct pt_regs *reg
 	struct sigframe __user *frame = get_sigframe(ka, regs, sizeof(*frame));
 	int err = 0;
 
+	pr_info("%s(regs=%p)\n", __func__, regs);
+
 	if (!frame)
 		return 1;
 

@@ -565,6 +574,8 @@ setup_rt_frame(int usig, struct k_sigaction *ka, siginfo_t *info,
 	stack_t stack;
 	int err = 0;
 
+	pr_info("%s(regs=%p)\n", __func__, regs);
+
 	if (!frame)
 		return 1;
 

@@ -609,6 +620,7 @@ handle_signal(unsigned long sig, struct k_sigaction *ka,
 	int usig = sig;
 	int ret;
 
+	pr_info("%s(regs=%p)\n", __func__, regs);
 	/*
 	 * translate the signal
 	 */

@@ -784,6 +796,7 @@ static void do_signal(struct pt_regs *regs, int syscall)
 asmlinkage void
 do_notify_resume(struct pt_regs *regs, unsigned int thread_flags, int syscall)
 {
+	pr_info("%s(regs=%p)\n", __func__, regs);
 	if (thread_flags & _TIF_SIGPENDING)
 		do_signal(regs, syscall);
arch/arm/kernel/sys_arm.c +1 -0
index d2b1779..4d3caca4d 100644
@@ -102,6 +102,7 @@ int kernel_execve(const char *filename,
 	 * We were successful.  We won't be returning to our caller, but
 	 * instead to user space by manipulating the kernel stack.
 	 */
+	pr_info("we were successful\n");
 	asm(	"add	r0, %0, %1\n\t"
 		"mov	r1, %2\n\t"
 		"mov	r2, %3\n\t"
Signature · 1 line
1.7.9.1
#15 lore raw

v3 cover ARM: Initial support for Cortex-M3

In reply to Uwe Kleine-König
Quoted 12 lines · Uwe Kleine-K?nig

this is the result of reworking Catalin's exception handling patch to stick to the current pt_regs layout. I extended it by two words to save the exception return value. (The 2nd word is unused and only to maintain stack alignment.)

Other than that only minor cleanups were done (some of them were suggested by Catalin in reply to my v2 series).

These patches are available at

git://git.pengutronix.de/git/ukl/linux.git cortexm3-for-rmk

Quoted 7 lines

basing on 3.3-rc7. There are some bits missing to allow a Cortex-M3 to boot. They are contained in the branch efm32 in the same repository together with support for the efm32 SoC if you're interested. The most important parts missing (apart from SoC specific stuff) are interrupt support and Makefile/Kconfig glue.

I'd be happy if these patches made it into 3.4-rc1.

That's pretty ambitious. Most maintainers (including Russell) closed their trees by now. You can still aim for 3.5-rc1 and ideally have them in -next a few weeks before (though only once Russell is fine with the patches).

Quoted 1 line

Any constructive feedback welcome.

I'll go through the patches sometime next week.

Signature · 1 line
Catalin
#16 lore raw

v3 cover ARM: Initial support for Cortex-M3

Quoted 6 lines · Catalin Marinas
Quoted 1 line

I'd be happy if these patches made it into 3.4-rc1.

That's pretty ambitious. Most maintainers (including Russell) closed their trees by now. You can still aim for 3.5-rc1 and ideally have them in -next a few weeks before (though only once Russell is fine with the patches).

Right. I don't see anything wrong with the patches, but now is not the time for them. Let's do a proper review after the merge window and then get them in early for 3.5.

Arnd