ARM: perf: support multiple PMUs
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cover ARM: perf: support multiple PMUs
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-----Original Message-----
From: Mark Rutland
System (AKA nest or uncore) PMUs exist on devices which are not affine to a single CPU. They usually cannot be directly associated with individual tasks and are asynchronous with respect to the current execution. Examples of devices which could have system PMUs include L2 cache controllers, GPUs and memory buses.The following patch series refactors the ARM PMU backend, enabling new PMUs to reuse the existing code. This should allow for system PMUs to be supported in future. Further work will be required to get perf to fully understand system PMUs, but this provides something usable.
The framework is intended to be used by system PMUs which hang off core platform components (e.g. L2 cache, AXI bus). If a device is complex enough or separate enough from core functionality to have its own driver, it should implement its own PMU handling using the core perf API directly.
The first patch ("perf: provide PMU when initing events") is currently sitting in the tip tree, but as it's required for event initialization to function (and hence for the PMU to be usable), it's provided here for convenience.
The series is based on Will Deacon's perf-updates branch at:
git://linux-arm.org/linux-2.6-wd.git perf-updates
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An example driver using the framework (supporting the PMU present in L220/PL310 level 2 cache controllers) can be found at:
git://linux-arm.org/linux-2.6-wd.git perf-l2x0-wipAny comments would be welcome.
Thanks,
Mark.
Other than the comments on patch [05/15] and [08/15], this series looks good to me !
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cover ARM: perf: support multiple PMUs
Quoted 5 lines · Ashwin Chaugule
Other than the comments on patch [05/15] and [08/15], this series looks good to me !
Reviewed-by Ashwin Chaugule <[email protected]>
Cracking. Once -rc3 has landed I'll merge this into my perf-updates branch (since some of my PMU refactoring will conflict with fixes going in for -rc3).
Thanks,
Will
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cover ARM: perf: support multiple PMUs
Hello Marc/Will,
[...]
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Subject: [RFC PATCH 00/15] ARM: perf: support multiple PMUs
------------------------From: Mark Rutland <mark.rutland at arm.com<mailto:[email protected]>>
Date: Mon, Aug 15, 2011 at 7:12 PM
To: linux-arm-kernel at lists.infradead.org
[...]
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System (AKA nest or uncore) PMUs exist on devices which are not affine to a single CPU. They usually cannot be directly associated with individual tasks and are asynchronous with respect to the current execution. Examples of devices which could have system PMUs include L2 cache controllers, GPUs and memory buses.
The following patch series refactors the ARM PMU backend, enabling new PMUs to reuse the existing code. This should allow for system PMUs to be supported in future. Further work will be required to get perf to fully understand system PMUs, but this provides something usable.
The framework is intended to be used by system PMUs which hang off core platform components (e.g. L2 cache, AXI bus). If a device is complex enough or separate enough from core functionality to have its own driver, it should implement its own PMU handling using the core perf API directly.
The first patch ("perf: provide PMU when initing events") is currently sitting in the tip tree, but as it's required for event initialization to function (and hence for the PMU to be usable), it's provided here for convenience.
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The series is based on Will Deacon's perf-updates branch at:
git://linux-arm.org/linux-2.6-wd.git perf-updatesAn example driver using the framework (supporting the PMU present in L220/PL310 level 2 cache controllers) can be found at:
git://linux-arm.org/linux-2.6-wd.git perf-l2x0-wip
Do you still maintain this tree? Looks it is empty. I'm wondering if we can make use of this to instrument the PMU counters of L2/pl310.
/srinidhi
cover ARM: perf: support multiple PMUs
Quoted 9 lines · Srinidhi Kasagar
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The series is based on Will Deacon's perf-updates branch at:
git://linux-arm.org/linux-2.6-wd.git perf-updatesAn example driver using the framework (supporting the PMU present in L220/PL310 level 2 cache controllers) can be found at:
git://linux-arm.org/linux-2.6-wd.git perf-l2x0-wipDo you still maintain this tree? Looks it is empty. I'm wondering if we can make use of this to instrument the PMU counters of L2/pl310.
There's an old branch here, but this stuff is pretty bit-rotted and needs reworking as part of the big.LITTLE support:
http://git.kernel.org/?p=linux/kernel/git/will/linux.git;a=shortlog;h=refs/heads/perf/l2x0
Will
cover ARM: perf: support multiple PMUs
Quoted 8 lines · Will Deacon
Quoted 7 lines · Srinidhi Kasagar
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The series is based on Will Deacon's perf-updates branch at:
git://linux-arm.org/linux-2.6-wd.git perf-updatesAn example driver using the framework (supporting the PMU present in L220/PL310 level 2 cache controllers) can be found at:
git://linux-arm.org/linux-2.6-wd.git perf-l2x0-wip
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Do you still maintain this tree? Looks it is empty. I'm wondering if we can make use of this to instrument the PMU counters of L2/pl310.
There's an old branch here, but this stuff is pretty bit-rotted and needs reworking as part of the big.LITTLE support:
http://git.kernel.org/?p=linux/kernel/git/will/linux.git;a=shortlog;h=refs/heads/perf/l2x0
Thanks, will look at it.
/srinidhi