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arm: socfpga: Add initial support for Altera's SOCFPGA HW

RFC PATCH Superseded dinguyen at altera.com 5 participants 17 messages Jul 12, 2012 – Jul 18, 2012

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v2 of 5 Superseded Latest is v5 →

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#0 lore raw

v2 cover arm: socfpga: Add initial support for Altera's SOCFPGA HW

From: Dinh Nguyen <[email protected]>

This patch series add minimal support for Altera's SOCFPGA hardward.

Changes since v1:
- Incorporate changes suggested by Pavel Machek, Thommas Petazzoni, Arnd Bergmann, and Rob Herring
- Reduce the patch to a make as much use of DTS as possible

Dinh Nguyen (2):
ARM: socfpga: initial support for Altera's SOCFPGA platform.
ARM: socfpga: Add board support for Altera's SOCFPGA Cyclone 5 HW

Signature · 1 line
1.7.9.5
#1 lore raw

RFC PATCH v2 1/2 ARM: socfpga: initial support for Altera's SOCFPGA platform.

From: Dinh Nguyen <[email protected]>

Adding core definitions for Altera's SOCFPGA ARM platform.

---
 MAINTAINERS                                      |    5 +++
 arch/arm/Kconfig                                 |   20 ++++++++++
 arch/arm/Makefile                                |    1 +
 arch/arm/mach-socfpga/clock.c                    |   45 ++++++++++++++++++++++
 arch/arm/mach-socfpga/common.h                   |   23 +++++++++++
 arch/arm/mach-socfpga/include/mach/debug-macro.S |   16 ++++++++
 arch/arm/mach-socfpga/include/mach/iomap.h       |   33 ++++++++++++++++
 arch/arm/mach-socfpga/include/mach/irqs.h        |   24 ++++++++++++
 arch/arm/mach-socfpga/include/mach/timex.h       |   19 +++++++++
 arch/arm/mach-socfpga/include/mach/uncompress.h  |    9 +++++
 10 files changed, 195 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/clock.c
 create mode 100644 arch/arm/mach-socfpga/common.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/debug-macro.S
 create mode 100644 arch/arm/mach-socfpga/include/mach/iomap.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/irqs.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/timex.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/uncompress.h
MAINTAINERS +5 -0
index 03df1d1..af6cc9b 100644
@@ -1103,6 +1103,11 @@ S:	Supported
 F:	arch/arm/mach-shmobile/
 F:	drivers/sh/
 
+ARM/SOCFPGA ARCHITECTURE
+M:	Dinh Nguyen <[email protected]>
+S:	Supported
+F:	arch/arm/mach-socfpga/
+
 ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
 M:	Lennert Buytenhek <[email protected]>
 L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
arch/arm/Kconfig +20 -0
index 57eb6ef..01116e5 100644
@@ -250,6 +250,24 @@ choice
 	prompt "ARM system type"
 	default ARCH_VERSATILE
 
+config ARCH_SOCFPGA
+	bool "Altera SOCFPGA family"
+	select ARCH_WANT_OPTIONAL_GPIOLIB
+	select ARM_AMBA
+	select ARM_GIC
+	select CACHE_L2X0
+	select CLKDEV_LOOKUP
+	select CPU_V7
+	select DW_APB_TIMER
+	select DW_APB_TIMER_OF
+	select GENERIC_CLOCKEVENTS
+	select GPIO_PL061 if GPIOLIB
+	select HAVE_ARM_SCU
+	select SPARSE_IRQ
+	select USE_OF
+	help
+	  This enables support for Altera SOCFPGA Cyclone V platform
+
 config ARCH_INTEGRATOR
 	bool "ARM Ltd. Integrator family"
 	select ARM_AMBA
@@ -1057,6 +1075,8 @@ source "arch/arm/mach-sa1100/Kconfig"
 source "arch/arm/plat-samsung/Kconfig"
 source "arch/arm/plat-s3c24xx/Kconfig"
 
+source "arch/arm/mach-socfpga/Kconfig"
+
 source "arch/arm/plat-spear/Kconfig"
 
 source "arch/arm/mach-s3c24xx/Kconfig"
arch/arm/Makefile +1 -0
index 0298b00..1fe5702 100644
@@ -193,6 +193,7 @@ machine-$(CONFIG_MACH_SPEAR310)		:= spear3xx
 machine-$(CONFIG_MACH_SPEAR320)		:= spear3xx
 machine-$(CONFIG_MACH_SPEAR600)		:= spear6xx
 machine-$(CONFIG_ARCH_ZYNQ)		:= zynq
+machine-$(CONFIG_ARCH_SOCFPGA) 	:= socfpga
 
 # Platform directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
arch/arm/mach-socfpga/clock.c new file +45 -0

45 lines not on this page · raw message

arch/arm/mach-socfpga/common.h new file +23 -0
new file mode 100644
index 0000000..e66587f
@@ -0,0 +1,23 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_SOCFPGA_COMMON_H
+#define __MACH_SOCFPGA_COMMON_H
+
+extern struct sys_timer socfpga_timer;
+
+#endif
arch/arm/mach-socfpga/include/mach/debug-macro.S new file +16 -0
new file mode 100644
index 0000000..d6f26d2
@@ -0,0 +1,16 @@
+/*
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+		.macro	addruart, rp, rv, tmp
+		mov	\rp, #DEBUG_LL_UART_OFFSET
+		orr	\rp, \rp, #0x00c00000
+		orr	\rv, \rp, #0xfe000000	@ virtual base
+		orr	\rp, \rp, #0xff000000	@ physical base
+		.endm
+
arch/arm/mach-socfpga/include/mach/iomap.h new file +33 -0
new file mode 100644
index 0000000..d5f8493
@@ -0,0 +1,33 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __MACH_SOCFPGA_IOMAP_H
+#define __MACH_SOCFPGA_IOMAP_H
+
+#include <asm/sizes.h>
+
+/* macro to get at IO space when running virtually */
+/*
+ * Statically mapped addresses:
+ *
+ * 10xx xxxx -> fbxx xxxx
+ * 1exx xxxx -> fdxx xxxx
+ * 1fxx xxxx -> fexx xxxx
+ */
+#define IO_ADDRESS(x)		(((x) & 0x03ffffff) + 0xfb000000)
+#define __io_address(n)		IOMEM(IO_ADDRESS(n))
+
+#endif
arch/arm/mach-socfpga/include/mach/irqs.h new file +24 -0
new file mode 100644
index 0000000..5e344db
@@ -0,0 +1,24 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+#define IRQ_SOCFPGA_GIC_START	32
+#define IRQ_LOCALWDOG		30
+#define MAX_GIC_NR		1
+
+#endif	/* __MACH_IRQS_H */
arch/arm/mach-socfpga/include/mach/timex.h new file +19 -0
new file mode 100644
index 0000000..43df435
@@ -0,0 +1,19 @@
+/*
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#define CLOCK_TICK_RATE		(50000000 / 16)
arch/arm/mach-socfpga/include/mach/uncompress.h new file +9 -0
new file mode 100644
index 0000000..bbe20e6
@@ -0,0 +1,9 @@
+#ifndef __MACH_UNCOMPRESS_H
+#define __MACH_UNCOMPRESS_H
+
+#define putc(c)
+#define flush()
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+
+#endif
Signature · 1 line
1.7.9.5
#2 lore raw

RFC PATCH v2 1/2 ARM: socfpga: initial support for Altera's SOCFPGA platform.

Quoted 6 lines · dinguyen at altera.com

From: Dinh Nguyen <[email protected]>

Adding core definitions for Altera's SOCFPGA ARM platform.

Two comments below, but otherwise:

Quoted 27 lines
arch/arm/mach-socfpga/include/mach/iomap.h new file +21 -0
new file mode 100644
index 0000000..d5f8493
@@ -0,0 +1,33 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __MACH_SOCFPGA_IOMAP_H
+#define __MACH_SOCFPGA_IOMAP_H
+
+#include <asm/sizes.h>
+

arch/arm/mach-socfpga/include/mach/iomap.h line 31

Quoted 10 lines
arch/arm/mach-socfpga/include/mach/iomap.h new file +10 -0
+/* macro to get at IO space when running virtually */
+/*
+ * Statically mapped addresses:
+ *
+ * 10xx xxxx -> fbxx xxxx
+ * 1exx xxxx -> fdxx xxxx
+ * 1fxx xxxx -> fexx xxxx
+ */
+#define IO_ADDRESS(x)		(((x) & 0x03ffffff) + 0xfb000000)
+#define __io_address(n)		IOMEM(IO_ADDRESS(n))

Is this used anywhere?

Quoted 20 lines
arch/arm/mach-socfpga/include/mach/iomap.h new file +2 -0
+
+#endif
arch/arm/mach-socfpga/include/mach/irqs.h new file +12 -0
new file mode 100644
index 0000000..5e344db
@@ -0,0 +1,24 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *

arch/arm/mach-socfpga/include/mach/irqs.h line 22

Quoted 10 lines
arch/arm/mach-socfpga/include/mach/irqs.h new file +10 -0
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+#define IRQ_SOCFPGA_GIC_START	32
+#define IRQ_LOCALWDOG		30
+#define MAX_GIC_NR		1

This header should not be needed.

Quoted 43 lines
arch/arm/mach-socfpga/include/mach/irqs.h new file +2 -0
+
+#endif	/* __MACH_IRQS_H */
arch/arm/mach-socfpga/include/mach/timex.h new file +19 -0
new file mode 100644
index 0000000..43df435
@@ -0,0 +1,19 @@
+/*
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#define CLOCK_TICK_RATE		(50000000 / 16)
arch/arm/mach-socfpga/include/mach/uncompress.h new file +9 -0
new file mode 100644
index 0000000..bbe20e6
@@ -0,0 +1,9 @@
+#ifndef __MACH_UNCOMPRESS_H
+#define __MACH_UNCOMPRESS_H
+
+#define putc(c)
+#define flush()
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+
+#endif
#3 lore raw

RFC PATCH v2 1/2 ARM: socfpga: initial support for Altera's SOCFPGA platform.

In reply to dinguyen at altera.com
Quoted 7 lines · dinguyen at altera.com
arch/arm/Kconfig +7 -0
+config ARCH_SOCFPGA
+	bool "Altera SOCFPGA family"
+	select ARCH_WANT_OPTIONAL_GPIOLIB
+	select ARM_AMBA
+	select ARM_GIC
+	select CACHE_L2X0
+	select CLKDEV_LOOKUP

arch/arm/Kconfig choice · line 269

Quoted 10 lines
arch/arm/Kconfig +10 -0
+	select CPU_V7
+	select DW_APB_TIMER
+	select DW_APB_TIMER_OF
+	select GENERIC_CLOCKEVENTS
+	select GPIO_PL061 if GPIOLIB
+	select HAVE_ARM_SCU
+	select SPARSE_IRQ
+	select USE_OF
+	help
+	  This enables support for Altera SOCFPGA Cyclone V platform

Please select COMMON_CLK as well to use the generic clock implementation.

Quoted 11 lines
arch/arm/mach-socfpga/clock.c new file +4 -0
new file mode 100644
index 0000000..79f3890
@@ -0,0 +1,45 @@
 
+#include <linux/clkdev.h>
+
+#define SOCFPGA_MPU_PERIHCLK_FREQ_HZ			(800000000 / 4)
+#define SOCFPGA_L4_MAIN_CLK					(400000000)

arch/arm/mach-socfpga/clock.c line 30

Quoted 10 lines
arch/arm/mach-socfpga/clock.c new file +10 -0
+
+struct clk {
+	unsigned long		rate;
+};
+
+static struct clk apb_pclk = { .rate = 200000000};
+static struct clk i2c_clk = { .rate = 100000000};
+static struct clk spim_clk = { .rate = 100000000};
+static struct clk mpu_pclk = { .rate = SOCFPGA_MPU_PERIHCLK_FREQ_HZ};
+static struct clk l4_main_clk = { .rate = SOCFPGA_L4_MAIN_CLK};

Then move this file into drivers/clk/ using that code.

Quoted 29 lines
arch/arm/mach-socfpga/include/mach/iomap.h new file +23 -0
new file mode 100644
index 0000000..d5f8493
@@ -0,0 +1,33 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __MACH_SOCFPGA_IOMAP_H
+#define __MACH_SOCFPGA_IOMAP_H
+
+#include <asm/sizes.h>
+
+/* macro to get at IO space when running virtually */
+/*

arch/arm/mach-socfpga/include/mach/iomap.h line 33

Quoted 10 lines
arch/arm/mach-socfpga/include/mach/iomap.h new file +10 -0
+ * Statically mapped addresses:
+ *
+ * 10xx xxxx -> fbxx xxxx
+ * 1exx xxxx -> fdxx xxxx
+ * 1fxx xxxx -> fexx xxxx
+ */
+#define IO_ADDRESS(x)		(((x) & 0x03ffffff) + 0xfb000000)
+#define __io_address(n)		IOMEM(IO_ADDRESS(n))
+
+#endif

This is unused, right? Just remove it.

Quoted 20 lines
arch/arm/mach-socfpga/include/mach/irqs.h new file +14 -0
new file mode 100644
index 0000000..5e344db
@@ -0,0 +1,24 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.

arch/arm/mach-socfpga/include/mach/irqs.h line 24

Quoted 10 lines
arch/arm/mach-socfpga/include/mach/irqs.h new file +10 -0
+*/
+
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+#define IRQ_SOCFPGA_GIC_START	32
+#define IRQ_LOCALWDOG		30
+#define MAX_GIC_NR		1
+
+#endif	/* __MACH_IRQS_H */

Same with this. Since you're using sparse IRQ, this file is not even included anywhere.

Arnd

#4 lore raw

RFC PATCH v2 1/2 ARM: socfpga: initial support for Altera's SOCFPGA platform.

Quoted 29 lines · Arnd Bergmann
Quoted 7 lines · dinguyen at altera.com
arch/arm/Kconfig +7 -0
+config ARCH_SOCFPGA
+	bool "Altera SOCFPGA family"
+	select ARCH_WANT_OPTIONAL_GPIOLIB
+	select ARM_AMBA
+	select ARM_GIC
+	select CACHE_L2X0
+	select CLKDEV_LOOKUP

arch/arm/Kconfig choice · line 269

Quoted 10 lines
arch/arm/Kconfig +10 -0
+	select CPU_V7
+	select DW_APB_TIMER
+	select DW_APB_TIMER_OF
+	select GENERIC_CLOCKEVENTS
+	select GPIO_PL061 if GPIOLIB
+	select HAVE_ARM_SCU
+	select SPARSE_IRQ
+	select USE_OF
+	help
+	  This enables support for Altera SOCFPGA Cyclone V platform

Please select COMMON_CLK as well to use the generic clock implementation.

Quoted 6 lines
arch/arm/mach-socfpga/clock.c new file +0 -0
new file mode 100644
index 0000000..79f3890
@@ -0,0 +1,45 @@
Quoted 16 lines
Quoted 4 lines
arch/arm/mach-socfpga/clock.c new file +4 -0
+#include <linux/clkdev.h>
+
+#define SOCFPGA_MPU_PERIHCLK_FREQ_HZ			(800000000 / 4)
+#define SOCFPGA_L4_MAIN_CLK					(400000000)

arch/arm/mach-socfpga/clock.c line 30

Quoted 10 lines
arch/arm/mach-socfpga/clock.c new file +10 -0
+
+struct clk {
+	unsigned long		rate;
+};
+
+static struct clk apb_pclk = { .rate = 200000000};
+static struct clk i2c_clk = { .rate = 100000000};
+static struct clk spim_clk = { .rate = 100000000};
+static struct clk mpu_pclk = { .rate = SOCFPGA_MPU_PERIHCLK_FREQ_HZ};
+static struct clk l4_main_clk = { .rate = SOCFPGA_L4_MAIN_CLK};

Then move this file into drivers/clk/ using that code.

This doesn't quite make sense to me. You want me to move platform specific information to drivers folder? I only see mxs and spear under drivers/clk. Surely, you don't want me to create another socfpga folder under there, or do you?

thanks,
Dinh

Quoted 79 lines
Quoted 30 lines
arch/arm/mach-socfpga/include/mach/iomap.h new file +23 -0
new file mode 100644
index 0000000..d5f8493
@@ -0,0 +1,33 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __MACH_SOCFPGA_IOMAP_H
+#define __MACH_SOCFPGA_IOMAP_H
+
+#include <asm/sizes.h>
+
+/* macro to get at IO space when running virtually */
+/*

arch/arm/mach-socfpga/include/mach/iomap.h line 33

Quoted 10 lines
arch/arm/mach-socfpga/include/mach/iomap.h new file +10 -0
+ * Statically mapped addresses:
+ *
+ * 10xx xxxx -> fbxx xxxx
+ * 1exx xxxx -> fdxx xxxx
+ * 1fxx xxxx -> fexx xxxx
+ */
+#define IO_ADDRESS(x)		(((x) & 0x03ffffff) + 0xfb000000)
+#define __io_address(n)		IOMEM(IO_ADDRESS(n))
+
+#endif

This is unused, right? Just remove it.

Quoted 20 lines
arch/arm/mach-socfpga/include/mach/irqs.h new file +14 -0
new file mode 100644
index 0000000..5e344db
@@ -0,0 +1,24 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.

arch/arm/mach-socfpga/include/mach/irqs.h line 24

Quoted 10 lines
arch/arm/mach-socfpga/include/mach/irqs.h new file +10 -0
+*/
+
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+#define IRQ_SOCFPGA_GIC_START	32
+#define IRQ_LOCALWDOG		30
+#define MAX_GIC_NR		1
+
+#endif	/* __MACH_IRQS_H */

Same with this. Since you're using sparse IRQ, this file is not even included anywhere.

Arnd

#5 lore raw

RFC PATCH v2 1/2 ARM: socfpga: initial support for Altera's SOCFPGA platform.

Quoted 8 lines · Dinh.Nguyen
Quoted 7 lines

arch/arm/mach-socfpga/clock.c line 30

Quoted 5 lines
arch/arm/mach-socfpga/clock.c new file +5 -0
+static struct clk apb_pclk = { .rate = 200000000};
+static struct clk i2c_clk = { .rate = 100000000};
+static struct clk spim_clk = { .rate = 100000000};
+static struct clk mpu_pclk = { .rate = SOCFPGA_MPU_PERIHCLK_FREQ_HZ};
+static struct clk l4_main_clk = { .rate = SOCFPGA_L4_MAIN_CLK};

Then move this file into drivers/clk/ using that code.

Quoted 4 lines

This doesn't quite make sense to me. You want me to move platform specific information to drivers folder? I only see mxs and spear under drivers/clk. Surely, you don't want me to create another socfpga folder under there, or do you?

Yes, that was the idea. We're in the process of moving most or all of the clock drivers there, and the two that you see there are just the start.

The distinction between "platform specific code" and "device driver" is quite artificial anyway, and we're constantly moving it so that we have less platform code.

Arnd

#6 lore raw

RFC PATCH v2 2/2 ARM: socfpga: Add board support for Altera's SOCFPGA Cyclone 5 HW

In reply to dinguyen at altera.com

From: Dinh Nguyen <[email protected]>

- Mininum support for Altera's SOCFPGA Cyclone 5 hardware.

---
 arch/arm/boot/dts/socfpga.dtsi           |   73 ++++++++++++++++++
 arch/arm/boot/dts/socfpga_cyclone5.dts   |  118 ++++++++++++++++++++++++++++++
 arch/arm/configs/socfpga_defconfig       |   83 +++++++++++++++++++++
 arch/arm/mach-socfpga/Kconfig            |    7 ++
 arch/arm/mach-socfpga/Makefile           |    6 ++
 arch/arm/mach-socfpga/Makefile.boot      |    1 +
 arch/arm/mach-socfpga/common.h           |    2 +-
 arch/arm/mach-socfpga/socfpga_cyclone5.c |   60 +++++++++++++++
 8 files changed, 349 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/socfpga.dtsi
 create mode 100644 arch/arm/boot/dts/socfpga_cyclone5.dts
 create mode 100644 arch/arm/configs/socfpga_defconfig
 create mode 100644 arch/arm/mach-socfpga/Kconfig
 create mode 100644 arch/arm/mach-socfpga/Makefile
 create mode 100644 arch/arm/mach-socfpga/Makefile.boot
 create mode 100644 arch/arm/mach-socfpga/socfpga_cyclone5.c
arch/arm/boot/dts/socfpga.dtsi new file +73 -0
new file mode 100644
index 0000000..54489b5
@@ -0,0 +1,73 @@
+/*
+ *  Copyright (C) 2012 Altera <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			compatible = "arm,cortex-a9";
+			device_type = "cpu";
+			reg = <0>;
+			next-level-cache = <&L2>;
+		};
+		cpu at 1 {
+			compatible = "arm,cortex-a9";
+			device_type = "cpu";
+			reg = <1>;
+			next-level-cache = <&L2>;
+		};
+	};
+
+	intc: intc at fffed000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0xfffed000 0x1000>,
+		      <0xfffec100 0x100>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		device_type = "soc";
+		interrupt-parent = <&intc>;
+		ranges;
+
+		/* Local timer */
+		timer at fffec600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0xfffec600 0x100>;
+			interrupts = <1 13 0xf04>;
+		};
+
+		L2: l2-cache at fffef000 {
+			compatible = "arm,pl310-cache";
+			reg = <0xfffef000 0x1000>;
+			interrupts = <0 38 0x04>;
+			cache-unified;
+			cache-level = <2>;
+		};
+	};
+};
arch/arm/boot/dts/socfpga_cyclone5.dts new file +118 -0

118 lines not on this page · raw message

arch/arm/configs/socfpga_defconfig new file +83 -0

83 lines not on this page · raw message

arch/arm/mach-socfpga/Kconfig new file +7 -0
new file mode 100644
index 0000000..133fc89
@@ -0,0 +1,7 @@
+config MACH_SOCFPGA_CYCLONE5
+       bool "SOCFPGA Cyclone5 platform"
+       select COMMON_CLK
+       select HAVE_SMP
+       select PLAT_SOCFPGA_ETH
+       help
+         Include support for the Altera(R) Cyclone5 development platform.
arch/arm/mach-socfpga/Makefile new file +6 -0
new file mode 100644
index 0000000..c994b40
@@ -0,0 +1,6 @@
+#
+# Makefile for the linux kernel.
+#
+
+obj-y					:= clock.o
+obj-$(CONFIG_MACH_SOCFPGA_CYCLONE5)	+= socfpga_cyclone5.o
arch/arm/mach-socfpga/Makefile.boot new file +1 -0
new file mode 100644
index 0000000..dae9661
@@ -0,0 +1 @@
+zreladdr-y	:= 0x00008000
arch/arm/mach-socfpga/common.h +1 -1
index e66587f..ba90e7a 100644
@@ -18,6 +18,6 @@
 #ifndef __MACH_SOCFPGA_COMMON_H
 #define __MACH_SOCFPGA_COMMON_H
 
-extern struct sys_timer socfpga_timer;
+extern struct sys_timer dw_apb_timer;
 
 #endif
arch/arm/mach-socfpga/socfpga_cyclone5.c new file +60 -0

60 lines not on this page · raw message

Signature · 1 line
1.7.9.5
#7 lore raw

RFC PATCH v2 2/2 ARM: socfpga: Add board support for Altera's SOCFPGA Cyclone 5 HW

Quoted 6 lines · dinguyen at altera.com

From: Dinh Nguyen <[email protected]>

- Mininum support for Altera's SOCFPGA Cyclone 5 hardware.

Two comments below, but otherwise:

Quoted 9 lines
---
 arch/arm/boot/dts/socfpga.dtsi           |   73 ++++++++++++++++++
 arch/arm/boot/dts/socfpga_cyclone5.dts   |  118 ++++++++++++++++++++++++++++++
 arch/arm/configs/socfpga_defconfig       |   83 +++++++++++++++++++++
 arch/arm/mach-socfpga/Kconfig            |    7 ++
 arch/arm/mach-socfpga/Makefile           |    6 ++
 arch/arm/mach-socfpga/Makefile.boot      |    1 +
 arch/arm/mach-socfpga/common.h           |    2 +-
 arch/arm/mach-socfpga/socfpga_cyclone5.c |   60 +++++++++++++++

I don't think this patch split makes too much sense. I would put all but the dts files and defconfig in the first patch.

arch/arm/mach-socfpga/Kconfig line 7

Quoted 13 lines
arch/arm/mach-socfpga/Kconfig new file +7 -0
new file mode 100644
index 0000000..133fc89
@@ -0,0 +1,7 @@
+config MACH_SOCFPGA_CYCLONE5
+       bool "SOCFPGA Cyclone5 platform"
+       select COMMON_CLK
+       select HAVE_SMP
+       select PLAT_SOCFPGA_ETH
+       help
+         Include support for the Altera(R) Cyclone5 development platform.

You don't need a config option for a machine with DT.

Rob

#8 lore raw

RFC PATCH v2 2/2 ARM: socfpga: Add board support for Altera's SOCFPGA Cyclone 5 HW

Le Mon, 16 Jul 2012 17:43:34 -0500,
Rob Herring <[email protected]> a ?crit :

Quoted 7 lines
Quoted 7 lines
arch/arm/mach-socfpga/Kconfig new file +1 -0
new file mode 100644
index 0000000..133fc89
@@ -0,0 +1,7 @@
+config MACH_SOCFPGA_CYCLONE5
Quoted 8 lines

arch/arm/mach-socfpga/Kconfig line 7

Quoted 6 lines
arch/arm/mach-socfpga/Kconfig new file +6 -0
+       bool "SOCFPGA Cyclone5 platform"
+       select COMMON_CLK
+       select HAVE_SMP
+       select PLAT_SOCFPGA_ETH
+       help
+         Include support for the Altera(R) Cyclone5 development platform.

You don't need a config option for a machine with DT.

Ah, interesting, I was precisely going to send an e-mail today about this, because we currently have different cases in tree:

* In mach-tegra/Kconfig, there is one Kconfig option per-board, and then mach-tegra/Makefile.boot contains lines like dtb-$(CONFIG_MACH_<board>) += <board>.dtb. So there is one Kconfig option per-board, and a .dtb generation per-board.

* In mach-at91/Kconfig, there is only one Kconfig option to support all DT-based platforms (CONFIG_MACH_AT91SAM_DT), and mach-at91/Makefile.boot generates the .dtb files for all boards as soon as CONFIG_MACH_AT91SAM_DT is enabled. So very different strategy from mach-tegra.

* In mach-mxs/Kconfig, there is only one Kconfig option to support all DT-based platforms (MACH_MXS_DT), but the mach-mxs/Makefile.boot does not have any dtb-... += line.

Which approach is the correct one? My feeling would be that the mach-at91 approach is the right one, because it doesn't make sense to have one Kconfig option per board when we use the device tree. Is this correct?

Best regards,

Thomas

Signature · 4 lines
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
#9 lore raw

RFC PATCH v2 2/2 ARM: socfpga: Add board support for Altera's SOCFPGA Cyclone 5 HW

In reply to dinguyen at altera.com

Hello,

Le Thu, 12 Jul 2012 12:26:16 -0500,
<[email protected]> a ?crit :

Quoted 71 lines
arch/arm/boot/dts/socfpga_cyclone5.dts new file +65 -0
new file mode 100644
index 0000000..710c773
@@ -0,0 +1,118 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+/include/ "socfpga.dtsi"
+
+/ {
+	model = "Altera SOCFPGA Cyclone V";
+	compatible = "altr,socfpga-cyclone5";
+
+	aliases {
+		ethernet0 = &gmac0;
+		serial0 = &uart0;
+		serial1 = &uart1;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,57600";
+	};
+
+	memory {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x10000000>; /* 256MB */
+	};
+
+	soc {
+		amba {
+			compatible = "arm,amba-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			pdma: pdma at ffe01000 {
+				compatible = "arm,pl330", "arm,primecell";
+				reg = <0xffe01000 0x1000>;
+				interrupts = <0 180 4>;
+			};
+		};
+
+		apb_periphs {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			uart0: uart at ffc02000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0xffc02000 0x1000>;
+				clock-frequency = <7372800>;
+				interrupts = <0 162 4>;

arch/arm/boot/dts/socfpga_cyclone5.dts line 75

Quoted 10 lines
arch/arm/boot/dts/socfpga_cyclone5.dts new file +10 -0
+				reg-shift = <2>;
+				reg-io-width = <4>;
+			};
+
+		timer0: timer at ffc08000 {
+				compatible = "snps,dw-apb-timer-sp";
+				interrupts = <0 167 4>;
+				clock-frequency = <200000000>;
+				reg = <0xffc08000 0x1000>;
+			};

There is an indentation problem here, the timer0 (and the following) should be at the same level as uart0.

Also, are all those peripherals (uarts, timers) really board-specific? I.e, are they synthesized on the FPGA part, or are they part of the ARM SoC, in which case they should be listed in the .dtsi and not in the .dts.

Best regards,

Thomas

Signature · 4 lines
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
#10 lore raw

RFC PATCH v2 2/2 ARM: socfpga: Add board support for Altera's SOCFPGA Cyclone 5 HW

Quoted 81 lines · Thomas Petazzoni

Hello,

Le Thu, 12 Jul 2012 12:26:16 -0500,
<[email protected]> a ?crit :

Quoted 76 lines
arch/arm/boot/dts/socfpga_cyclone5.dts new file +70 -0
new file mode 100644
index 0000000..710c773
@@ -0,0 +1,118 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+/include/ "socfpga.dtsi"
+
+/ {
+	model = "Altera SOCFPGA Cyclone V";
+	compatible = "altr,socfpga-cyclone5";
+
+	aliases {
+		ethernet0 = &gmac0;
+		serial0 = &uart0;
+		serial1 = &uart1;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,57600";
+	};
+
+	memory {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x10000000>; /* 256MB */
+	};
+
+	soc {
+		amba {
+			compatible = "arm,amba-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			pdma: pdma at ffe01000 {
+				compatible = "arm,pl330", "arm,primecell";
+				reg = <0xffe01000 0x1000>;
+				interrupts = <0 180 4>;
+			};
+		};
+
+		apb_periphs {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			uart0: uart at ffc02000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0xffc02000 0x1000>;
+				clock-frequency = <7372800>;
+				interrupts = <0 162 4>;
+				reg-shift = <2>;
+				reg-io-width = <4>;
+			};
+
+		timer0: timer at ffc08000 {
Quoted 8 lines

arch/arm/boot/dts/socfpga_cyclone5.dts line 75

Quoted 5 lines
arch/arm/boot/dts/socfpga_cyclone5.dts new file +5 -0
+				compatible = "snps,dw-apb-timer-sp";
+				interrupts = <0 167 4>;
+				clock-frequency = <200000000>;
+				reg = <0xffc08000 0x1000>;
+			};

There is an indentation problem here, the timer0 (and the following) should be at the same level as uart0.

Will fix..

Quoted 5 lines

Also, are all those peripherals (uarts, timers) really board-specific? I.e, are they synthesized on the FPGA part, or are they part of the ARM SoC, in which case they should be listed in the .dtsi and not in the .dts.

Agreed. The peripherals are just part of the ARM SoC.

Quoted 4 lines

Best regards,

Thomas

#11 lore raw

RFC PATCH v2 2/2 ARM: socfpga: Add board support for Altera's SOCFPGA Cyclone 5 HW

In reply to dinguyen at altera.com

arch/arm/mach-socfpga/Kconfig line 7

Quoted 13 lines · dinguyen at altera.com
arch/arm/mach-socfpga/Kconfig new file +7 -0
new file mode 100644
index 0000000..133fc89
@@ -0,0 +1,7 @@
+config MACH_SOCFPGA_CYCLONE5
+       bool "SOCFPGA Cyclone5 platform"
+       select COMMON_CLK
+       select HAVE_SMP
+       select PLAT_SOCFPGA_ETH
+       help
+         Include support for the Altera(R) Cyclone5 development platform.

Ah, so you actually select COMMON_CLK already. I wonder why that works, since you are also defining your own "struct clk" that gets passed into the clk_lookup table. I guess there is a bug somewhere.

arch/arm/mach-socfpga/common.h line 23

Quoted 12 lines
arch/arm/mach-socfpga/common.h +1 -1
index e66587f..ba90e7a 100644
@@ -18,6 +18,6 @@
 #ifndef __MACH_SOCFPGA_COMMON_H
 #define __MACH_SOCFPGA_COMMON_H
 
-extern struct sys_timer socfpga_timer;
+extern struct sys_timer dw_apb_timer;
 
 #endif

This should get folded into the first patch.

arch/arm/mach-socfpga/common.h

Quoted 13 lines
arch/arm/mach-socfpga/common.h +13 -0
+static const char *altera_dt_match[] = {
+	"altr,socfpga-cyclone5",
+	NULL
+};
+
+DT_MACHINE_START(SOCFPGA_CYCLONE5, "Altera SOCFPGA Cyclone V")
+	.init_irq	= gic_init_irq,
+	.handle_irq     = gic_handle_irq,
+	.timer		= &dw_apb_timer,
+	.init_machine	= socfpga_cyclone5_init,
+	.restart	= socfpga_cyclone5_restart,
+	.dt_compat	= altera_dt_match,
+MACHINE_END

I think you should not require more than one such file per platform, so I would either name the entire platform cyclone5 instead of socfpga, or if you expect this to all stay compatible with future products, remove the cyclone5 name here and just call it all socfpga. The dt_match array can still list multiple compatible strings, one for each family or so.

Arnd

#12 lore raw

v2 cover arm: socfpga: Add initial support for Altera's SOCFPGA HW

In reply to dinguyen at altera.com

Hi!

Arnd, do you think this is good enough to go to the next tree? It is new architecture, it should not break anything, I believe we addressed all the issues raised in the review, and noone is reporting new ones.

Plus, if we could make initial support into 3.6, that would be very nice :-).

Thanks,
Pavel

Quoted 14 lines · dinguyen at altera.com

From: Dinh Nguyen <[email protected]>

This patch series add minimal support for Altera's SOCFPGA hardward.

Changes since v1:
- Incorporate changes suggested by Pavel Machek, Thommas Petazzoni, Arnd Bergmann, and Rob Herring
- Reduce the patch to a make as much use of DTS as possible

Dinh Nguyen (2):
ARM: socfpga: initial support for Altera's SOCFPGA platform.
ARM: socfpga: Add board support for Altera's SOCFPGA Cyclone 5 HW

Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
#13 lore raw

v2 cover arm: socfpga: Add initial support for Altera's SOCFPGA HW

Quoted 7 lines · Pavel Machek

Arnd, do you think this is good enough to go to the next tree? It is new architecture, it should not break anything, I believe we addressed all the issues raised in the review, and noone is reporting new ones.

Plus, if we could make initial support into 3.6, that would be very nice :-).

I think we can make it for v3.6, but it's very late for that and I haven't looked at it enough in the past. I have a few small comments, so if you can address them quickly we can take it.

Arnd

#14 lore raw

v2 cover arm: socfpga: Add initial support for Altera's SOCFPGA HW

Quoted 6 lines · Arnd Bergmann
Quoted 5 lines · Pavel Machek

Arnd, do you think this is good enough to go to the next tree? It is new architecture, it should not break anything, I believe we addressed all the issues raised in the review, and noone is reporting new ones.

Quoted 6 lines
Quoted 2 lines

Plus, if we could make initial support into 3.6, that would be very nice :-).

I think we can make it for v3.6, but it's very late for that and I haven't looked at it enough in the past. I have a few small comments, so if you can address them quickly we can take it.

Hi Arnd. Thanks, please fire away your comments.
Dinh

Quoted 3 lines

Arnd

#15 lore raw

v2 cover arm: socfpga: Add initial support for Altera's SOCFPGA HW

Hi!

Quoted 5 lines
Quoted 5 lines
Quoted 5 lines

Arnd, do you think this is good enough to go to the next tree? It is new architecture, it should not break anything, I believe we addressed all the issues raised in the review, and noone is reporting new ones.

Quoted 8 lines
Quoted 6 lines
Quoted 2 lines

Plus, if we could make initial support into 3.6, that would be very nice :-).

I think we can make it for v3.6, but it's very late for that and I haven't looked at it enough in the past. I have a few small comments, so if you can address them quickly we can take it.

Hi Arnd. Thanks, please fire away your comments.

Arnd wanted quick reactions, so I took liberty of creating PATCHv4. (You are marked in From: so you'll still get the credit :-). I hope that is not a big problem.

I'm now pushing for-altera-0718 with the PATCHv4 (+ .config file).

Now, I guess at this point it would be useful to make our repository public?

(Oh, and cross the fingers for us so that it finally gets merged :-).

Pavel

Signature · 2 lines
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(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
#16 lore raw

v2 cover arm: socfpga: Add initial support for Altera's SOCFPGA HW

Quoted 20 lines · Pavel Machek

Hi!

Quoted 5 lines
Quoted 5 lines
Quoted 5 lines

Arnd, do you think this is good enough to go to the next tree? It is new architecture, it should not break anything, I believe we addressed all the issues raised in the review, and noone is reporting new ones.

Quoted 8 lines
Quoted 6 lines
Quoted 2 lines

Plus, if we could make initial support into 3.6, that would be very nice :-).

I think we can make it for v3.6, but it's very late for that and I haven't looked at it enough in the past. I have a few small comments, so if you can address them quickly we can take it.

Hi Arnd. Thanks, please fire away your comments.

Arnd wanted quick reactions, so I took liberty of creating PATCHv4. (You are marked in From: so you'll still get the credit :-). I hope that is not a big problem.

Quoted 6 lines

I'm now pushing for-altera-0718 with the PATCHv4 (+ .config file).

Now, I guess at this point it would be useful to make our repository public?

(Oh, and cross the fingers for us so that it finally gets merged :-).

Ooops, this was not supposed to go to the lists. Sorry for the spam :-(.
Pavel

Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html