Cleanup PRM and CM regbit headers
Subsystems (4)
cover Cleanup PRM and CM regbit headers
Hi,
Over the years the PRM and CM headers for OMAP have been growing largely due to autogeneration which creates headers for complete PRM and CM register space, regardless of the actual usage of these registers in software.
The latest master on linux-omap (which also happens to have the OMAP5 data) show these stats for the prm-regbits-*.h and cm-regbits-*.h alone. Not to mention there are other PRM/CM related headers which I am yet to look at.
a0131687 at ula0131687:~/oldhome/repos/github/linux$ cat arch/arm/mach-omap2/prm-regbits-*.h | wc -l 6285a0131687 at ula0131687:~/oldhome/repos/github/linux$ cat arch/arm/mach-omap2/cm-regbits-*.h | wc -l 5556
Using some simple awk/grep scripting I cleaned these headers to retain only the defines that are currently used and that changes the stats to this below.
a0131687 at ula0131687:~/oldhome/repos/github/linux$ cat arch/arm/mach-omap2/prm-regbits-*.h | wc -l 352a0131687 at ula0131687:~/oldhome/repos/github/linux$ cat arch/arm/mach-omap2/cm-regbits-*.h | wc -l 661
I am sharing this RFC just to take the discussion forward on how to handle these files, and many others which are also autogenerated, given we have newer SoCs coming up for which the autogen output ends up creating even larger files.
Rajendra Nayak (4):
ARM: OMAP2: PRM/CM: Cleanup unused header contents
ARM: OMAP3: PRM/CM: Cleanup unused header contents
ARM: OMAP4: PRM/CM: Cleanup unused header contents
ARM: OMAP5: PRM/CM: Cleanup unused header contents
arch/arm/mach-omap2/cm-regbits-24xx.h | 317 ---- arch/arm/mach-omap2/cm-regbits-33xx.h | 758 --------- arch/arm/mach-omap2/cm-regbits-34xx.h | 631 -------- arch/arm/mach-omap2/cm-regbits-44xx.h | 1557 ------------------- arch/arm/mach-omap2/cm-regbits-54xx.h | 1632 ------------------- arch/arm/mach-omap2/prm-regbits-24xx.h | 246 --- arch/arm/mach-omap2/prm-regbits-33xx.h | 305 ---- arch/arm/mach-omap2/prm-regbits-34xx.h | 480 ------ arch/arm/mach-omap2/prm-regbits-44xx.h | 2225 -------------------------- arch/arm/mach-omap2/prm-regbits-54xx.h | 2677 -------------------------------- 10 files changed, 10828 deletions(-)
Signature · 1 line
1.7.9.5
RFC 1/4 ARM: OMAP2: PRM/CM: Cleanup unused header contents
Cleanup unused bits of headers for PRM and CM leaving only whats used.
Signed-off-by Rajendra Nayak <[email protected]>
--- arch/arm/mach-omap2/cm-regbits-24xx.h | 317 -------------------------------- arch/arm/mach-omap2/prm-regbits-24xx.h | 246 ------------------------- 2 files changed, 563 deletions(-)
arch/arm/mach-omap2/cm-regbits-24xx.h +0 -317
@@ -14,439 +14,122 @@* published by the Free Software Foundation. */ -/* Bits shared between registers */ - -/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ #define OMAP24XX_EN_CAM_SHIFT 31 -#define OMAP24XX_EN_CAM_MASK (1 << 31)#define OMAP24XX_EN_WDT4_SHIFT 29 -#define OMAP24XX_EN_WDT4_MASK (1 << 29)#define OMAP2420_EN_WDT3_SHIFT 28 -#define OMAP2420_EN_WDT3_MASK (1 << 28)#define OMAP24XX_EN_MSPRO_SHIFT 27 -#define OMAP24XX_EN_MSPRO_MASK (1 << 27)#define OMAP24XX_EN_FAC_SHIFT 25 -#define OMAP24XX_EN_FAC_MASK (1 << 25)#define OMAP2420_EN_EAC_SHIFT 24 -#define OMAP2420_EN_EAC_MASK (1 << 24)#define OMAP24XX_EN_HDQ_SHIFT 23 -#define OMAP24XX_EN_HDQ_MASK (1 << 23)#define OMAP2420_EN_I2C2_SHIFT 20 -#define OMAP2420_EN_I2C2_MASK (1 << 20)#define OMAP2420_EN_I2C1_SHIFT 19 -#define OMAP2420_EN_I2C1_MASK (1 << 19) - -/* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */ #define OMAP2430_EN_MCBSP5_SHIFT 5 -#define OMAP2430_EN_MCBSP5_MASK (1 << 5)#define OMAP2430_EN_MCBSP4_SHIFT 4 -#define OMAP2430_EN_MCBSP4_MASK (1 << 4)#define OMAP2430_EN_MCBSP3_SHIFT 3 -#define OMAP2430_EN_MCBSP3_MASK (1 << 3)#define OMAP24XX_EN_SSI_SHIFT 1 -#define OMAP24XX_EN_SSI_MASK (1 << 1) - -/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ #define OMAP24XX_EN_MPU_WDT_SHIFT 3 -#define OMAP24XX_EN_MPU_WDT_MASK (1 << 3) - -/* Bits specific to each register */ - -/* CM_IDLEST_MPU */ -/* 2430 only */ -#define OMAP2430_ST_MPU_MASK (1 << 0) - -/* CM_CLKSEL_MPU */ #define OMAP24XX_CLKSEL_MPU_SHIFT 0 -#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0)#define OMAP24XX_CLKSEL_MPU_WIDTH 5 - -/* CM_CLKSTCTRL_MPU */ -#define OMAP24XX_AUTOSTATE_MPU_SHIFT 0#define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0) - -/* CM_FCLKEN1_CORE specific bits*/ #define OMAP24XX_EN_TV_SHIFT 2 -#define OMAP24XX_EN_TV_MASK (1 << 2)#define OMAP24XX_EN_DSS2_SHIFT 1 -#define OMAP24XX_EN_DSS2_MASK (1 << 1)#define OMAP24XX_EN_DSS1_SHIFT 0#define OMAP24XX_EN_DSS1_MASK (1 << 0) - -/* CM_FCLKEN2_CORE specific bits */ #define OMAP2430_EN_I2CHS2_SHIFT 20 -#define OMAP2430_EN_I2CHS2_MASK (1 << 20)#define OMAP2430_EN_I2CHS1_SHIFT 19 -#define OMAP2430_EN_I2CHS1_MASK (1 << 19)#define OMAP2430_EN_MMCHSDB2_SHIFT 17 -#define OMAP2430_EN_MMCHSDB2_MASK (1 << 17)#define OMAP2430_EN_MMCHSDB1_SHIFT 16 -#define OMAP2430_EN_MMCHSDB1_MASK (1 << 16) - -/* CM_ICLKEN1_CORE specific bits */ #define OMAP24XX_EN_MAILBOXES_SHIFT 30 -#define OMAP24XX_EN_MAILBOXES_MASK (1 << 30) -#define OMAP24XX_EN_DSS_SHIFT 0 -#define OMAP24XX_EN_DSS_MASK (1 << 0) - -/* CM_ICLKEN2_CORE specific bits */ - -/* CM_ICLKEN3_CORE */ -/* 2430 only */ #define OMAP2430_EN_SDRC_SHIFT 2 -#define OMAP2430_EN_SDRC_MASK (1 << 2) - -/* CM_ICLKEN4_CORE */ #define OMAP24XX_EN_PKA_SHIFT 4 -#define OMAP24XX_EN_PKA_MASK (1 << 4)#define OMAP24XX_EN_AES_SHIFT 3 -#define OMAP24XX_EN_AES_MASK (1 << 3)#define OMAP24XX_EN_RNG_SHIFT 2 -#define OMAP24XX_EN_RNG_MASK (1 << 2)#define OMAP24XX_EN_SHA_SHIFT 1 -#define OMAP24XX_EN_SHA_MASK (1 << 1)#define OMAP24XX_EN_DES_SHIFT 0 -#define OMAP24XX_EN_DES_MASK (1 << 0) - -/* CM_IDLEST1_CORE specific bits */ #define OMAP24XX_ST_MAILBOXES_SHIFT 30 -#define OMAP24XX_ST_MAILBOXES_MASK (1 << 30) -#define OMAP24XX_ST_WDT4_SHIFT 29 -#define OMAP24XX_ST_WDT4_MASK (1 << 29) -#define OMAP2420_ST_WDT3_SHIFT 28 -#define OMAP2420_ST_WDT3_MASK (1 << 28) -#define OMAP24XX_ST_MSPRO_SHIFT 27 -#define OMAP24XX_ST_MSPRO_MASK (1 << 27) -#define OMAP24XX_ST_FAC_SHIFT 25 -#define OMAP24XX_ST_FAC_MASK (1 << 25) -#define OMAP2420_ST_EAC_SHIFT 24 -#define OMAP2420_ST_EAC_MASK (1 << 24)#define OMAP24XX_ST_HDQ_SHIFT 23 -#define OMAP24XX_ST_HDQ_MASK (1 << 23)#define OMAP2420_ST_I2C2_SHIFT 20 -#define OMAP2420_ST_I2C2_MASK (1 << 20)#define OMAP2430_ST_I2CHS1_SHIFT 19 -#define OMAP2430_ST_I2CHS1_MASK (1 << 19)#define OMAP2420_ST_I2C1_SHIFT 19 -#define OMAP2420_ST_I2C1_MASK (1 << 19)#define OMAP2430_ST_I2CHS2_SHIFT 20 -#define OMAP2430_ST_I2CHS2_MASK (1 << 20)#define OMAP24XX_ST_MCBSP2_SHIFT 16 -#define OMAP24XX_ST_MCBSP2_MASK (1 << 16)#define OMAP24XX_ST_MCBSP1_SHIFT 15 -#define OMAP24XX_ST_MCBSP1_MASK (1 << 15)#define OMAP24XX_ST_DSS_SHIFT 0 -#define OMAP24XX_ST_DSS_MASK (1 << 0) - -/* CM_IDLEST2_CORE */ #define OMAP2430_ST_MCBSP5_SHIFT 5 -#define OMAP2430_ST_MCBSP5_MASK (1 << 5)#define OMAP2430_ST_MCBSP4_SHIFT 4 -#define OMAP2430_ST_MCBSP4_MASK (1 << 4)#define OMAP2430_ST_MCBSP3_SHIFT 3 -#define OMAP2430_ST_MCBSP3_MASK (1 << 3) -#define OMAP24XX_ST_SSI_SHIFT 1 -#define OMAP24XX_ST_SSI_MASK (1 << 1) - -/* CM_IDLEST3_CORE */ -/* 2430 only */ -#define OMAP2430_ST_SDRC_MASK (1 << 2) - -/* CM_IDLEST4_CORE */ -#define OMAP24XX_ST_PKA_SHIFT 4 -#define OMAP24XX_ST_PKA_MASK (1 << 4)#define OMAP24XX_ST_AES_SHIFT 3 -#define OMAP24XX_ST_AES_MASK (1 << 3)#define OMAP24XX_ST_RNG_SHIFT 2 -#define OMAP24XX_ST_RNG_MASK (1 << 2)#define OMAP24XX_ST_SHA_SHIFT 1 -#define OMAP24XX_ST_SHA_MASK (1 << 1) -#define OMAP24XX_ST_DES_SHIFT 0 -#define OMAP24XX_ST_DES_MASK (1 << 0) - -/* CM_AUTOIDLE1_CORE */ -#define OMAP24XX_AUTO_CAM_MASK (1 << 31) -#define OMAP24XX_AUTO_MAILBOXES_MASK (1 << 30) -#define OMAP24XX_AUTO_WDT4_MASK (1 << 29) -#define OMAP2420_AUTO_WDT3_MASK (1 << 28) -#define OMAP24XX_AUTO_MSPRO_MASK (1 << 27) -#define OMAP2420_AUTO_MMC_MASK (1 << 26) -#define OMAP24XX_AUTO_FAC_MASK (1 << 25) -#define OMAP2420_AUTO_EAC_MASK (1 << 24) -#define OMAP24XX_AUTO_HDQ_MASK (1 << 23) -#define OMAP24XX_AUTO_UART2_MASK (1 << 22) -#define OMAP24XX_AUTO_UART1_MASK (1 << 21) -#define OMAP24XX_AUTO_I2C2_MASK (1 << 20) -#define OMAP24XX_AUTO_I2C1_MASK (1 << 19) -#define OMAP24XX_AUTO_MCSPI2_MASK (1 << 18) -#define OMAP24XX_AUTO_MCSPI1_MASK (1 << 17) -#define OMAP24XX_AUTO_MCBSP2_MASK (1 << 16) -#define OMAP24XX_AUTO_MCBSP1_MASK (1 << 15) -#define OMAP24XX_AUTO_GPT12_MASK (1 << 14) -#define OMAP24XX_AUTO_GPT11_MASK (1 << 13) -#define OMAP24XX_AUTO_GPT10_MASK (1 << 12) -#define OMAP24XX_AUTO_GPT9_MASK (1 << 11) -#define OMAP24XX_AUTO_GPT8_MASK (1 << 10) -#define OMAP24XX_AUTO_GPT7_MASK (1 << 9) -#define OMAP24XX_AUTO_GPT6_MASK (1 << 8) -#define OMAP24XX_AUTO_GPT5_MASK (1 << 7) -#define OMAP24XX_AUTO_GPT4_MASK (1 << 6) -#define OMAP24XX_AUTO_GPT3_MASK (1 << 5) -#define OMAP24XX_AUTO_GPT2_MASK (1 << 4) -#define OMAP2420_AUTO_VLYNQ_MASK (1 << 3) -#define OMAP24XX_AUTO_DSS_MASK (1 << 0) - -/* CM_AUTOIDLE2_CORE */ -#define OMAP2430_AUTO_MDM_INTC_MASK (1 << 11) -#define OMAP2430_AUTO_GPIO5_MASK (1 << 10) -#define OMAP2430_AUTO_MCSPI3_MASK (1 << 9) -#define OMAP2430_AUTO_MMCHS2_MASK (1 << 8) -#define OMAP2430_AUTO_MMCHS1_MASK (1 << 7) -#define OMAP2430_AUTO_USBHS_MASK (1 << 6) -#define OMAP2430_AUTO_MCBSP5_MASK (1 << 5) -#define OMAP2430_AUTO_MCBSP4_MASK (1 << 4) -#define OMAP2430_AUTO_MCBSP3_MASK (1 << 3) -#define OMAP24XX_AUTO_UART3_MASK (1 << 2) -#define OMAP24XX_AUTO_SSI_MASK (1 << 1) -#define OMAP24XX_AUTO_USB_MASK (1 << 0) - -/* CM_AUTOIDLE3_CORE */ #define OMAP24XX_AUTO_SDRC_SHIFT 2 -#define OMAP24XX_AUTO_SDRC_MASK (1 << 2)#define OMAP24XX_AUTO_GPMC_SHIFT 1 -#define OMAP24XX_AUTO_GPMC_MASK (1 << 1)#define OMAP24XX_AUTO_SDMA_SHIFT 0 -#define OMAP24XX_AUTO_SDMA_MASK (1 << 0) - -/* CM_AUTOIDLE4_CORE */ -#define OMAP24XX_AUTO_PKA_MASK (1 << 4) -#define OMAP24XX_AUTO_AES_MASK (1 << 3) -#define OMAP24XX_AUTO_RNG_MASK (1 << 2) -#define OMAP24XX_AUTO_SHA_MASK (1 << 1) -#define OMAP24XX_AUTO_DES_MASK (1 << 0) - -/* CM_CLKSEL1_CORE */ -#define OMAP24XX_CLKSEL_USB_SHIFT 25#define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25) -#define OMAP24XX_CLKSEL_SSI_SHIFT 20#define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20) -#define OMAP2420_CLKSEL_VLYNQ_SHIFT 15#define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15) -#define OMAP24XX_CLKSEL_DSS2_SHIFT 13#define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13) -#define OMAP24XX_CLKSEL_DSS1_SHIFT 8#define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8)#define OMAP24XX_CLKSEL_L4_SHIFT 5 -#define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5)#define OMAP24XX_CLKSEL_L4_WIDTH 2#define OMAP24XX_CLKSEL_L3_SHIFT 0 -#define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0)#define OMAP24XX_CLKSEL_L3_WIDTH 5 - -/* CM_CLKSEL2_CORE */ -#define OMAP24XX_CLKSEL_GPT12_SHIFT 22#define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22) -#define OMAP24XX_CLKSEL_GPT11_SHIFT 20#define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20) -#define OMAP24XX_CLKSEL_GPT10_SHIFT 18#define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18) -#define OMAP24XX_CLKSEL_GPT9_SHIFT 16#define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16) -#define OMAP24XX_CLKSEL_GPT8_SHIFT 14#define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14) -#define OMAP24XX_CLKSEL_GPT7_SHIFT 12#define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12) -#define OMAP24XX_CLKSEL_GPT6_SHIFT 10#define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10) -#define OMAP24XX_CLKSEL_GPT5_SHIFT 8#define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8) -#define OMAP24XX_CLKSEL_GPT4_SHIFT 6#define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6) -#define OMAP24XX_CLKSEL_GPT3_SHIFT 4#define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4) -#define OMAP24XX_CLKSEL_GPT2_SHIFT 2#define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2) - -/* CM_CLKSTCTRL_CORE */ -#define OMAP24XX_AUTOSTATE_DSS_SHIFT 2#define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2) -#define OMAP24XX_AUTOSTATE_L4_SHIFT 1#define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1) -#define OMAP24XX_AUTOSTATE_L3_SHIFT 0#define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0) - -/* CM_FCLKEN_GFX */ #define OMAP24XX_EN_3D_SHIFT 2 -#define OMAP24XX_EN_3D_MASK (1 << 2)#define OMAP24XX_EN_2D_SHIFT 1 -#define OMAP24XX_EN_2D_MASK (1 << 1) - -/* CM_ICLKEN_GFX specific bits */ - -/* CM_IDLEST_GFX specific bits */ - -/* CM_CLKSEL_GFX specific bits */ - -/* CM_CLKSTCTRL_GFX */ -#define OMAP24XX_AUTOSTATE_GFX_SHIFT 0#define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0) - -/* CM_FCLKEN_WKUP specific bits */ - -/* CM_ICLKEN_WKUP specific bits */ #define OMAP2430_EN_ICR_SHIFT 6 -#define OMAP2430_EN_ICR_MASK (1 << 6)#define OMAP24XX_EN_OMAPCTRL_SHIFT 5 -#define OMAP24XX_EN_OMAPCTRL_MASK (1 << 5)#define OMAP24XX_EN_WDT1_SHIFT 4 -#define OMAP24XX_EN_WDT1_MASK (1 << 4)#define OMAP24XX_EN_32KSYNC_SHIFT 1 -#define OMAP24XX_EN_32KSYNC_MASK (1 << 1) - -/* CM_IDLEST_WKUP specific bits */ -#define OMAP2430_ST_ICR_SHIFT 6 -#define OMAP2430_ST_ICR_MASK (1 << 6) -#define OMAP24XX_ST_OMAPCTRL_SHIFT 5 -#define OMAP24XX_ST_OMAPCTRL_MASK (1 << 5) -#define OMAP24XX_ST_WDT1_SHIFT 4 -#define OMAP24XX_ST_WDT1_MASK (1 << 4)#define OMAP24XX_ST_MPU_WDT_SHIFT 3 -#define OMAP24XX_ST_MPU_WDT_MASK (1 << 3)#define OMAP24XX_ST_32KSYNC_SHIFT 1 -#define OMAP24XX_ST_32KSYNC_MASK (1 << 1) - -/* CM_AUTOIDLE_WKUP */ -#define OMAP24XX_AUTO_OMAPCTRL_MASK (1 << 5) -#define OMAP24XX_AUTO_WDT1_MASK (1 << 4) -#define OMAP24XX_AUTO_MPU_WDT_MASK (1 << 3) -#define OMAP24XX_AUTO_GPIOS_MASK (1 << 2) -#define OMAP24XX_AUTO_32KSYNC_MASK (1 << 1) -#define OMAP24XX_AUTO_GPT1_MASK (1 << 0) - -/* CM_CLKSEL_WKUP */ -#define OMAP24XX_CLKSEL_GPT1_SHIFT 0#define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0) - -/* CM_CLKEN_PLL */ #define OMAP24XX_EN_54M_PLL_SHIFT 6 -#define OMAP24XX_EN_54M_PLL_MASK (0x3 << 6)#define OMAP24XX_EN_96M_PLL_SHIFT 2 -#define OMAP24XX_EN_96M_PLL_MASK (0x3 << 2) -#define OMAP24XX_EN_DPLL_SHIFT 0#define OMAP24XX_EN_DPLL_MASK (0x3 << 0) - -/* CM_IDLEST_CKGEN */ #define OMAP24XX_ST_54M_APLL_SHIFT 9 -#define OMAP24XX_ST_54M_APLL_MASK (1 << 9)#define OMAP24XX_ST_96M_APLL_SHIFT 8 -#define OMAP24XX_ST_96M_APLL_MASK (1 << 8) -#define OMAP24XX_ST_54M_CLK_MASK (1 << 6) -#define OMAP24XX_ST_12M_CLK_MASK (1 << 5) -#define OMAP24XX_ST_48M_CLK_MASK (1 << 4) -#define OMAP24XX_ST_96M_CLK_MASK (1 << 2) -#define OMAP24XX_ST_CORE_CLK_SHIFT 0 -#define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0) - -/* CM_AUTOIDLE_PLL */ -#define OMAP24XX_AUTO_54M_SHIFT 6#define OMAP24XX_AUTO_54M_MASK (0x3 << 6) -#define OMAP24XX_AUTO_96M_SHIFT 2#define OMAP24XX_AUTO_96M_MASK (0x3 << 2)#define OMAP24XX_AUTO_DPLL_SHIFT 0#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0) - -/* CM_CLKSEL1_PLL */ -#define OMAP2430_MAXDPLLFASTLOCK_SHIFT 28 -#define OMAP2430_MAXDPLLFASTLOCK_MASK (0x7 << 28)#define OMAP24XX_APLLS_CLKIN_SHIFT 23#define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23) -#define OMAP24XX_DPLL_MULT_SHIFT 12#define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12) -#define OMAP24XX_DPLL_DIV_SHIFT 8#define OMAP24XX_DPLL_DIV_MASK (0xf << 8)#define OMAP24XX_54M_SOURCE_SHIFT 5 -#define OMAP24XX_54M_SOURCE_MASK (1 << 5)#define OMAP24XX_54M_SOURCE_WIDTH 1#define OMAP2430_96M_SOURCE_SHIFT 4 -#define OMAP2430_96M_SOURCE_MASK (1 << 4)#define OMAP2430_96M_SOURCE_WIDTH 1 -#define OMAP24XX_48M_SOURCE_SHIFT 3#define OMAP24XX_48M_SOURCE_MASK (1 << 3) -#define OMAP2430_ALTCLK_SOURCE_SHIFT 0 -#define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0) - -/* CM_CLKSEL2_PLL */ -#define OMAP24XX_CORE_CLK_SRC_SHIFT 0#define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0) - -/* CM_FCLKEN_DSP */ #define OMAP2420_EN_IVA_COP_SHIFT 10 -#define OMAP2420_EN_IVA_COP_MASK (1 << 10)#define OMAP2420_EN_IVA_MPU_SHIFT 8 -#define OMAP2420_EN_IVA_MPU_MASK (1 << 8)#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0 -#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_MASK (1 << 0) - -/* CM_ICLKEN_DSP */ #define OMAP2420_EN_DSP_IPI_SHIFT 1 -#define OMAP2420_EN_DSP_IPI_MASK (1 << 1) - -/* CM_IDLEST_DSP */ -#define OMAP2420_ST_IVA_MASK (1 << 8) -#define OMAP2420_ST_IPI_MASK (1 << 1) -#define OMAP24XX_ST_DSP_MASK (1 << 0) - -/* CM_AUTOIDLE_DSP */ -#define OMAP2420_AUTO_DSP_IPI_MASK (1 << 1) - -/* CM_CLKSEL_DSP */ -#define OMAP2420_SYNC_IVA_MASK (1 << 13) -#define OMAP2420_CLKSEL_IVA_SHIFT 8#define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8) -#define OMAP24XX_SYNC_DSP_MASK (1 << 7) -#define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5#define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5) -#define OMAP24XX_CLKSEL_DSP_SHIFT 0#define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0) - -/* CM_CLKSTCTRL_DSP */ -#define OMAP2420_AUTOSTATE_IVA_SHIFT 8#define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8) -#define OMAP24XX_AUTOSTATE_DSP_SHIFT 0#define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0) - -/* CM_FCLKEN_MDM */ -/* 2430 only */ #define OMAP2430_EN_OSC_SHIFT 1 -#define OMAP2430_EN_OSC_MASK (1 << 1) - -/* CM_ICLKEN_MDM */ -/* 2430 only */ #define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0 -#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_MASK (1 << 0) - -/* CM_IDLEST_MDM specific bits */ -/* 2430 only */ - -/* CM_AUTOIDLE_MDM */ -/* 2430 only */ -#define OMAP2430_AUTO_OSC_MASK (1 << 1) -#define OMAP2430_AUTO_MDM_MASK (1 << 0) - -/* CM_CLKSEL_MDM */ -/* 2430 only */ -#define OMAP2430_SYNC_MDM_MASK (1 << 4) -#define OMAP2430_CLKSEL_MDM_SHIFT 0#define OMAP2430_CLKSEL_MDM_MASK (0xf << 0) - -/* CM_CLKSTCTRL_MDM */ -/* 2430 only */ -#define OMAP2430_AUTOSTATE_MDM_SHIFT 0#define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0) - -/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */ #define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1 -#endif
arch/arm/mach-omap2/prm-regbits-24xx.h +0 -246
274 lines not on this page · raw message
Signature · 1 line
1.7.9.5
RFC 2/4 ARM: OMAP3: PRM/CM: Cleanup unused header contents
In reply to Rajendra NayakCleanup unused bits of headers for PRM and CM leaving only whats used.
Signed-off-by Rajendra Nayak <[email protected]>
--- arch/arm/mach-omap2/cm-regbits-33xx.h | 758 -------------------------------- arch/arm/mach-omap2/cm-regbits-34xx.h | 631 -------------------------- arch/arm/mach-omap2/prm-regbits-33xx.h | 305 ------------- arch/arm/mach-omap2/prm-regbits-34xx.h | 480 -------------------- 4 files changed, 2174 deletions(-)
arch/arm/mach-omap2/cm-regbits-33xx.h +0 -758
@@ -20,798 +20,40 @@#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H -/* -* Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP, -* CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER -*/ -#define AM33XX_AUTO_DPLL_MODE_SHIFT 0 -#define AM33XX_AUTO_DPLL_MODE_WIDTH 3 -#define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14 -#define AM33XX_CLKACTIVITY_ADC_FCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11 -#define AM33XX_CLKACTIVITY_CAN_CLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11) - -/* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4) - -/* Used by CM_PER_CPSW_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4) - -/* Used by CM_PER_L4HS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4) - -/* Used by CM_PER_L4HS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5 -#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5) - -/* Used by CM_PER_L4HS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6 -#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6) - -/* Used by CM_PER_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6 -#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6) - -/* Used by CM_CEFUSE_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 -#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) - -/* Used by CM_L3_AON_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2 -#define AM33XX_CLKACTIVITY_DBGSYSCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2) - -/* Used by CM_L3_AON_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4 -#define AM33XX_CLKACTIVITY_DEBUG_CLKA_WIDTH 1 -#define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4) - -/* Used by CM_PER_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2 -#define AM33XX_CLKACTIVITY_EMIF_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2) - -/* Used by CM_GFX_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9 -#define AM33XX_CLKACTIVITY_GFX_FCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9) - -/* Used by CM_GFX_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19 -#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20 -#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21 -#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22 -#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26 -#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18 -#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11 -#define AM33XX_CLKACTIVITY_I2C0_GFCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24 -#define AM33XX_CLKACTIVITY_I2C_FCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24) - -/* Used by CM_PER_PRUSS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5 -#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5) - -/* Used by CM_PER_PRUSS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4) - -/* Used by CM_PER_PRUSS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6 -#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6) - -/* Used by CM_PER_L3S_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3 -#define AM33XX_CLKACTIVITY_L3S_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3) - -/* Used by CM_L3_AON_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3 -#define AM33XX_CLKACTIVITY_L3_AON_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3) - -/* Used by CM_PER_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_L3_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4) - -/* Used by CM_PER_L4FW_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_L4FW_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8) - -/* Used by CM_PER_L4HS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3 -#define AM33XX_CLKACTIVITY_L4HS_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_L4LS_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8) - -/* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */ -#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8) - -/* Used by CM_CEFUSE_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) - -/* Used by CM_RTC_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8) - -/* Used by CM_L4_WKUP_AON_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2 -#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2 -#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17 -#define AM33XX_CLKACTIVITY_LCDC_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17) - -/* Used by CM_PER_LCDC_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4) - -/* Used by CM_PER_LCDC_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5 -#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5) - -/* Used by CM_PER_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7 -#define AM33XX_CLKACTIVITY_MCASP_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7) - -/* Used by CM_PER_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3 -#define AM33XX_CLKACTIVITY_MMC_FCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3) - -/* Used by CM_MPU_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2 -#define AM33XX_CLKACTIVITY_MPU_CLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2) - -/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4) - -/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5 -#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5) - -/* Used by CM_RTC_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9 -#define AM33XX_CLKACTIVITY_RTC_32KCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25 -#define AM33XX_CLKACTIVITY_SPI_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3 -#define AM33XX_CLKACTIVITY_SR_SYSCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10 -#define AM33XX_CLKACTIVITY_TIMER0_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13 -#define AM33XX_CLKACTIVITY_TIMER1_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14 -#define AM33XX_CLKACTIVITY_TIMER2_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15 -#define AM33XX_CLKACTIVITY_TIMER3_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16 -#define AM33XX_CLKACTIVITY_TIMER4_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27 -#define AM33XX_CLKACTIVITY_TIMER5_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28 -#define AM33XX_CLKACTIVITY_TIMER6_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13 -#define AM33XX_CLKACTIVITY_TIMER7_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12 -#define AM33XX_CLKACTIVITY_UART0_GFCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10 -#define AM33XX_CLKACTIVITY_UART_GFCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9 -#define AM33XX_CLKACTIVITY_WDT0_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_WDT1_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4) - -/* Used by CLKSEL_GFX_FCLK */ -#define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0 -#define AM33XX_CLKDIV_SEL_GFX_FCLK_WIDTH 1 -#define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0) - -/* Used by CM_CLKOUT_CTRL */ #define AM33XX_CLKOUT2DIV_SHIFT 3#define AM33XX_CLKOUT2DIV_WIDTH 3 -#define AM33XX_CLKOUT2DIV_MASK (0x7 << 3) - -/* Used by CM_CLKOUT_CTRL */ #define AM33XX_CLKOUT2EN_SHIFT 7 -#define AM33XX_CLKOUT2EN_WIDTH 1 -#define AM33XX_CLKOUT2EN_MASK (1 << 7) - -/* Used by CM_CLKOUT_CTRL */ -#define AM33XX_CLKOUT2SOURCE_SHIFT 0 -#define AM33XX_CLKOUT2SOURCE_WIDTH 3#define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0) - -/* -* Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK, -* CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK, -* CLKSEL_TIMER7_CLK -*/ -#define AM33XX_CLKSEL_SHIFT 0 -#define AM33XX_CLKSEL_WIDTH 1 -#define AM33XX_CLKSEL_MASK (0x01 << 0) - -/* -* Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK, -* CM_CPTS_RFT_CLKSEL -*/ #define AM33XX_CLKSEL_0_0_SHIFT 0#define AM33XX_CLKSEL_0_0_WIDTH 1#define AM33XX_CLKSEL_0_0_MASK (1 << 0) - -#define AM33XX_CLKSEL_0_1_SHIFT 0 -#define AM33XX_CLKSEL_0_1_WIDTH 2#define AM33XX_CLKSEL_0_1_MASK (3 << 0) - -/* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */ -#define AM33XX_CLKSEL_0_2_SHIFT 0 -#define AM33XX_CLKSEL_0_2_WIDTH 3#define AM33XX_CLKSEL_0_2_MASK (7 << 0) - -/* Used by CLKSEL_GFX_FCLK */ -#define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1 -#define AM33XX_CLKSEL_GFX_FCLK_WIDTH 1#define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1) - -/* -* Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL, -* CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL, -* CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL, -* CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL, -* CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL, -* CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL -*/ #define AM33XX_CLKTRCTRL_SHIFT 0 -#define AM33XX_CLKTRCTRL_WIDTH 2#define AM33XX_CLKTRCTRL_MASK (0x3 << 0) - -/* -* Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR, -* CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU, -* CM_SSC_DELTAMSTEP_DPLL_PER -*/ -#define AM33XX_DELTAMSTEP_SHIFT 0 -#define AM33XX_DELTAMSTEP_WIDTH 20 -#define AM33XX_DELTAMSTEP_MASK (0xfffff << 0) - -/* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */ -#define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23 -#define AM33XX_DPLL_BYP_CLKSEL_WIDTH 1 -#define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23) - -/* Used by CM_CLKDCOLDO_DPLL_PER */ -#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 -#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 1 -#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_CLKDCOLDO_DPLL_PER */ -#define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12 -#define AM33XX_DPLL_CLKDCOLDO_PWDN_WIDTH 1 -#define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12) - -/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ #define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0#define AM33XX_DPLL_CLKOUT_DIV_WIDTH 5 -#define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0) - -/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */ -#define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0 -#define AM33XX_DPLL_CLKOUT_DIV_0_6_WIDTH 7 -#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) - -/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ -#define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5 -#define AM33XX_DPLL_CLKOUT_DIVCHACK_WIDTH 1 -#define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) - -/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */ -#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7 -#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_WIDTH 1 -#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7) - -/* -* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU, -* CM_DIV_M2_DPLL_PER -*/ -#define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 -#define AM33XX_DPLL_CLKOUT_GATE_CTRL_WIDTH 1 -#define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) - -/* -* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, -* CM_CLKSEL_DPLL_MPU -*/ -#define AM33XX_DPLL_DIV_SHIFT 0 -#define AM33XX_DPLL_DIV_WIDTH 7#define AM33XX_DPLL_DIV_MASK (0x7f << 0) -#define AM33XX_DPLL_PER_DIV_MASK (0xff << 0) - -/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */ -#define AM33XX_DPLL_DIV_0_7_SHIFT 0 -#define AM33XX_DPLL_DIV_0_7_WIDTH 8 -#define AM33XX_DPLL_DIV_0_7_MASK (0xff << 0) - -/* -* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, -* CM_CLKMODE_DPLL_MPU -*/ -#define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8 -#define AM33XX_DPLL_DRIFTGUARD_EN_WIDTH 1 -#define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8) - -/* -* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, -* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER -*/ -#define AM33XX_DPLL_EN_SHIFT 0 -#define AM33XX_DPLL_EN_WIDTH 3#define AM33XX_DPLL_EN_MASK (0x7 << 0) - -/* -* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, -* CM_CLKMODE_DPLL_MPU -*/ -#define AM33XX_DPLL_LPMODE_EN_SHIFT 10 -#define AM33XX_DPLL_LPMODE_EN_WIDTH 1 -#define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10) - -/* -* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, -* CM_CLKSEL_DPLL_MPU -*/ -#define AM33XX_DPLL_MULT_SHIFT 8 -#define AM33XX_DPLL_MULT_WIDTH 11#define AM33XX_DPLL_MULT_MASK (0x7ff << 8) - -/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */ -#define AM33XX_DPLL_MULT_PERIPH_SHIFT 8 -#define AM33XX_DPLL_MULT_PERIPH_WIDTH 12#define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8) - -/* -* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, -* CM_CLKMODE_DPLL_MPU -*/ -#define AM33XX_DPLL_REGM4XEN_SHIFT 11 -#define AM33XX_DPLL_REGM4XEN_WIDTH 1 -#define AM33XX_DPLL_REGM4XEN_MASK (1 << 11) - -/* Used by CM_CLKSEL_DPLL_PERIPH */ -#define AM33XX_DPLL_SD_DIV_SHIFT 24 -#define AM33XX_DPLL_SD_DIV_WIDTH 8 -#define AM33XX_DPLL_SD_DIV_MASK (0xff << 24) - -/* -* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, -* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER -*/ -#define AM33XX_DPLL_SSC_ACK_SHIFT 13 -#define AM33XX_DPLL_SSC_ACK_WIDTH 1 -#define AM33XX_DPLL_SSC_ACK_MASK (1 << 13) - -/* -* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, -* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER -*/ -#define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14 -#define AM33XX_DPLL_SSC_DOWNSPREAD_WIDTH 1 -#define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) - -/* -* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, -* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER -*/ -#define AM33XX_DPLL_SSC_EN_SHIFT 12 -#define AM33XX_DPLL_SSC_EN_WIDTH 1 -#define AM33XX_DPLL_SSC_EN_MASK (1 << 12) - -/* Used by CM_DIV_M4_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0#define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5 -#define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) - -/* Used by CM_DIV_M4_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 -#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) - -/* Used by CM_DIV_M4_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 -#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_DIV_M4_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 -#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) - -/* Used by CM_DIV_M5_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0#define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5 -#define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) - -/* Used by CM_DIV_M5_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 -#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) - -/* Used by CM_DIV_M5_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 -#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_DIV_M5_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 -#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) - -/* Used by CM_DIV_M6_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0#define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5 -#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) - -/* Used by CM_DIV_M6_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 -#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) - -/* Used by CM_DIV_M6_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 -#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_DIV_M6_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 -#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) - -/* -* Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL, -* CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, -* CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL, -* CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL, -* CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL, -* CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL, -* CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL, -* CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL, -* CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL, -* CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL, -* CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL, -* CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL, -* CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL, -* CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL, -* CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, -* CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL, -* CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL, -* CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL, -* CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL, -* CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL, -* CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL, -* CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, -* CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL, -* CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL, -* CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL, -* CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL, -* CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL, -* CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL, -* CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL, -* CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL, -* CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL -*/ #define AM33XX_IDLEST_SHIFT 16 -#define AM33XX_IDLEST_WIDTH 2#define AM33XX_IDLEST_MASK (0x3 << 16) - -/* Used by CM_MAC_CLKSEL */ -#define AM33XX_MII_CLK_SEL_SHIFT 2 -#define AM33XX_MII_CLK_SEL_WIDTH 1 -#define AM33XX_MII_CLK_SEL_MASK (1 << 2) - -/* -* Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR, -* CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU, -* CM_SSC_MODFREQDIV_DPLL_PER -*/ -#define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8 -#define AM33XX_MODFREQDIV_EXPONENT_WIDTH 3 -#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8) - -/* -* Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR, -* CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU, -* CM_SSC_MODFREQDIV_DPLL_PER -*/ -#define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0 -#define AM33XX_MODFREQDIV_MANTISSA_WIDTH 7 -#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0) - -/* -* Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL, -* CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, -* CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL, -* CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL, -* CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL, -* CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL, -* CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL, -* CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL, -* CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL, -* CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL, -* CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL, -* CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL, -* CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL, -* CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL, -* CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, -* CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL, -* CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL, -* CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL, -* CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL, -* CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL, -* CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL, -* CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, -* CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL, -* CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL, -* CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL, -* CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL, -* CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL, -* CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL, -* CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL, -* CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, -* CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, -* CM_CEFUSE_CEFUSE_CLKCTRL -*/ #define AM33XX_MODULEMODE_SHIFT 0 -#define AM33XX_MODULEMODE_WIDTH 2#define AM33XX_MODULEMODE_MASK (0x3 << 0) - -/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ -#define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30 -#define AM33XX_OPTCLK_DEBUG_CLKA_WIDTH 1 -#define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30) - -/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ -#define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19 -#define AM33XX_OPTFCLKEN_DBGSYSCLK_WIDTH 1 -#define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19) - -/* Used by CM_WKUP_GPIO0_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_WIDTH 1 -#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18) - -/* Used by CM_PER_GPIO1_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_WIDTH 1 -#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18) - -/* Used by CM_PER_GPIO2_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_WIDTH 1 -#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18) - -/* Used by CM_PER_GPIO3_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_WIDTH 1 -#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18) - -/* Used by CM_PER_GPIO4_CLKCTRL */ -#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_WIDTH 1 -#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18) - -/* Used by CM_PER_GPIO5_CLKCTRL */ -#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_WIDTH 1 -#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18) - -/* Used by CM_PER_GPIO6_CLKCTRL */ -#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_WIDTH 1 -#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18) - -/* -* Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL, -* CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL, -* CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, -* CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, -* CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL, -* CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL -*/ -#define AM33XX_STBYST_SHIFT 18 -#define AM33XX_STBYST_WIDTH 1 -#define AM33XX_STBYST_MASK (1 << 18) - -/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ -#define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27 -#define AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3 -#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x7 << 27) - -/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ -#define AM33XX_STM_PMD_CLKSEL_SHIFT 22 -#define AM33XX_STM_PMD_CLKSEL_WIDTH 2 -#define AM33XX_STM_PMD_CLKSEL_MASK (0x3 << 22) - -/* -* Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP, -* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER -*/ -#define AM33XX_ST_DPLL_CLK_SHIFT 0 -#define AM33XX_ST_DPLL_CLK_WIDTH 1#define AM33XX_ST_DPLL_CLK_MASK (1 << 0) - -/* Used by CM_CLKDCOLDO_DPLL_PER */ #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8 -#define AM33XX_ST_DPLL_CLKDCOLDO_WIDTH 1 -#define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8) - -/* -* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU, -* CM_DIV_M2_DPLL_PER -*/ -#define AM33XX_ST_DPLL_CLKOUT_SHIFT 9 -#define AM33XX_ST_DPLL_CLKOUT_WIDTH 1 -#define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9) - -/* Used by CM_DIV_M4_DPLL_CORE */ -#define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9 -#define AM33XX_ST_HSDIVIDER_CLKOUT1_WIDTH 1 -#define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) - -/* Used by CM_DIV_M5_DPLL_CORE */ -#define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9 -#define AM33XX_ST_HSDIVIDER_CLKOUT2_WIDTH 1 -#define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) - -/* Used by CM_DIV_M6_DPLL_CORE */ -#define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9 -#define AM33XX_ST_HSDIVIDER_CLKOUT3_WIDTH 1 -#define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) - -/* -* Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP, -* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER -*/ -#define AM33XX_ST_MN_BYPASS_SHIFT 8 -#define AM33XX_ST_MN_BYPASS_WIDTH 1 -#define AM33XX_ST_MN_BYPASS_MASK (1 << 8) - -/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ -#define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24 -#define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3 -#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x7 << 24) - -/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ -#define AM33XX_TRC_PMD_CLKSEL_SHIFT 20 -#define AM33XX_TRC_PMD_CLKSEL_WIDTH 2 -#define AM33XX_TRC_PMD_CLKSEL_MASK (0x3 << 20) -/* Used by CONTROL_SEC_CLK_CTRL */ -#define AM33XX_TIMER0_CLKSEL_WIDTH 2 -#define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4)#endif
arch/arm/mach-omap2/cm-regbits-34xx.h +0 -631
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arch/arm/mach-omap2/prm-regbits-33xx.h +0 -305
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arch/arm/mach-omap2/prm-regbits-34xx.h +0 -480
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Signature · 1 line
1.7.9.5
Tony Lindgren
maintainercover Cleanup PRM and CM regbit headers
In reply to Rajendra NayakQuoted 6 lines · Rajendra Nayak
Hi,
Over the years the PRM and CM headers for OMAP have been growing largely due to autogeneration which creates headers for complete PRM and CM register space, regardless of the actual usage of these registers in software.
Thanks for working on this. Yes most of this should no longer be needed.
Quoted 12 lines
The latest master on linux-omap (which also happens to have the OMAP5 data) show these stats for the prm-regbits-*.h and cm-regbits-*.h alone. Not to mention there are other PRM/CM related headers which I am yet to look at.
a0131687at ula0131687:~/oldhome/repos/github/linux$ catarch/arm/mach-omap2/prm-regbits-*.h| wc -l 6285a0131687at ula0131687:~/oldhome/repos/github/linux$ catarch/arm/mach-omap2/cm-regbits-*.h| wc -l 5556Using some simple awk/grep scripting I cleaned these headers to retain only the defines that are currently used and that changes the stats to this below.
Quoted 8 lines
a0131687at ula0131687:~/oldhome/repos/github/linux$ catarch/arm/mach-omap2/prm-regbits-*.h| wc -l 352a0131687at ula0131687:~/oldhome/repos/github/linux$ catarch/arm/mach-omap2/cm-regbits-*.h| wc -l 661I am sharing this RFC just to take the discussion forward on how to handle these files, and many others which are also autogenerated, given we have newer SoCs coming up for which the autogen output ends up creating even larger files.
Yes we should get to the point where adding new SoCs is just few hundred lines of code plus the new device drivers.
Quoted 6 lines
Rajendra Nayak (4):
ARM: OMAP2: PRM/CM: Cleanup unused header contents
ARM: OMAP3: PRM/CM: Cleanup unused header contents
ARM: OMAP4: PRM/CM: Cleanup unused header contents
ARM: OMAP5: PRM/CM: Cleanup unused header contents
Quoted 11 lines
arch/arm/mach-omap2/cm-regbits-24xx.h | 317 ---- arch/arm/mach-omap2/cm-regbits-33xx.h | 758 --------- arch/arm/mach-omap2/cm-regbits-34xx.h | 631 -------- arch/arm/mach-omap2/cm-regbits-44xx.h | 1557 ------------------- arch/arm/mach-omap2/cm-regbits-54xx.h | 1632 ------------------- arch/arm/mach-omap2/prm-regbits-24xx.h | 246 --- arch/arm/mach-omap2/prm-regbits-33xx.h | 305 ---- arch/arm/mach-omap2/prm-regbits-34xx.h | 480 ------ arch/arm/mach-omap2/prm-regbits-44xx.h | 2225 -------------------------- arch/arm/mach-omap2/prm-regbits-54xx.h | 2677 -------------------------------- 10 files changed, 10828 deletions(-)
If things build and work after applying this, I suggest we send them as a clean-up branch right after -rc1.
It seems that build testing and then randconfig testing should be enough for these if they are unused and only removal.
Regards,
Tony
cover Cleanup PRM and CM regbit headers
Quoted 17 lines · Tony Lindgren
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Rajendra Nayak (4):
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ARM: OMAP2: PRM/CM: Cleanup unused header contents
ARM: OMAP3: PRM/CM: Cleanup unused header contents
ARM: OMAP4: PRM/CM: Cleanup unused header contents
ARM: OMAP5: PRM/CM: Cleanup unused header contentsarch/arm/mach-omap2/cm-regbits-24xx.h | 317 ---- arch/arm/mach-omap2/cm-regbits-33xx.h | 758 --------- arch/arm/mach-omap2/cm-regbits-34xx.h | 631 -------- arch/arm/mach-omap2/cm-regbits-44xx.h | 1557 ------------------- arch/arm/mach-omap2/cm-regbits-54xx.h | 1632 ------------------- arch/arm/mach-omap2/prm-regbits-24xx.h | 246 --- arch/arm/mach-omap2/prm-regbits-33xx.h | 305 ---- arch/arm/mach-omap2/prm-regbits-34xx.h | 480 ------ arch/arm/mach-omap2/prm-regbits-44xx.h | 2225 -------------------------- arch/arm/mach-omap2/prm-regbits-54xx.h | 2677 -------------------------------- 10 files changed, 10828 deletions(-)
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If things build and work after applying this, I suggest we send them as a clean-up branch right after -rc1.
They build fine, and I boot tested on the omap4/5 boards that I have too. (I had the out of tree clock data pulled in for omap5 before I did this cleanup).
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It seems that build testing and then randconfig testing should be enough for these if they are unused and only removal.
Right, I'll do more testing and even though they should just boot fine on the omap2/3 boards too since all thats removed is anyway unused, I will still do more sanity test before posting them on -rc1.
regards,
Rajendra
Tony Lindgren
maintainercover Cleanup PRM and CM regbit headers
Quoted 26 lines · Rajendra Nayak
Quoted 17 lines · Tony Lindgren
Quoted 17 lines
Rajendra Nayak (4):
Quoted 16 lines
ARM: OMAP2: PRM/CM: Cleanup unused header contents
ARM: OMAP3: PRM/CM: Cleanup unused header contents
ARM: OMAP4: PRM/CM: Cleanup unused header contents
ARM: OMAP5: PRM/CM: Cleanup unused header contentsarch/arm/mach-omap2/cm-regbits-24xx.h | 317 ---- arch/arm/mach-omap2/cm-regbits-33xx.h | 758 --------- arch/arm/mach-omap2/cm-regbits-34xx.h | 631 -------- arch/arm/mach-omap2/cm-regbits-44xx.h | 1557 ------------------- arch/arm/mach-omap2/cm-regbits-54xx.h | 1632 ------------------- arch/arm/mach-omap2/prm-regbits-24xx.h | 246 --- arch/arm/mach-omap2/prm-regbits-33xx.h | 305 ---- arch/arm/mach-omap2/prm-regbits-34xx.h | 480 ------ arch/arm/mach-omap2/prm-regbits-44xx.h | 2225 -------------------------- arch/arm/mach-omap2/prm-regbits-54xx.h | 2677 -------------------------------- 10 files changed, 10828 deletions(-)Quoted 2 lines
If things build and work after applying this, I suggest we send them as a clean-up branch right after -rc1.
They build fine, and I boot tested on the omap4/5 boards that I have too. (I had the out of tree clock data pulled in for omap5 before I did this cleanup).
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It seems that build testing and then randconfig testing should be enough for these if they are unused and only removal.
Right, I'll do more testing and even though they should just boot fine on the omap2/3 boards too since all thats removed is anyway unused, I will still do more sanity test before posting them on -rc1.
Looks like we have all the pending stuff merged already, this would probably be a good time to post a pull request for these.
Tony
cover Cleanup PRM and CM regbit headers
Quoted 31 lines · Tony Lindgren
Quoted 30 lines · Rajendra Nayak
Quoted 17 lines · Tony Lindgren
Quoted 17 lines
Rajendra Nayak (4):
Quoted 16 lines
ARM: OMAP2: PRM/CM: Cleanup unused header contents
ARM: OMAP3: PRM/CM: Cleanup unused header contents
ARM: OMAP4: PRM/CM: Cleanup unused header contents
ARM: OMAP5: PRM/CM: Cleanup unused header contentsarch/arm/mach-omap2/cm-regbits-24xx.h | 317 ---- arch/arm/mach-omap2/cm-regbits-33xx.h | 758 --------- arch/arm/mach-omap2/cm-regbits-34xx.h | 631 -------- arch/arm/mach-omap2/cm-regbits-44xx.h | 1557 ------------------- arch/arm/mach-omap2/cm-regbits-54xx.h | 1632 ------------------- arch/arm/mach-omap2/prm-regbits-24xx.h | 246 --- arch/arm/mach-omap2/prm-regbits-33xx.h | 305 ---- arch/arm/mach-omap2/prm-regbits-34xx.h | 480 ------ arch/arm/mach-omap2/prm-regbits-44xx.h | 2225 -------------------------- arch/arm/mach-omap2/prm-regbits-54xx.h | 2677 -------------------------------- 10 files changed, 10828 deletions(-)Quoted 2 lines
If things build and work after applying this, I suggest we send them as a clean-up branch right after -rc1.
They build fine, and I boot tested on the omap4/5 boards that I have too. (I had the out of tree clock data pulled in for omap5 before I did this cleanup).
Quoted 4 lines
It seems that build testing and then randconfig testing should be enough for these if they are unused and only removal.
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Right, I'll do more testing and even though they should just boot fine on the omap2/3 boards too since all thats removed is anyway unused, I will still do more sanity test before posting them on -rc1.
Looks like we have all the pending stuff merged already, this would probably be a good time to post a pull request for these.
Ok, will do, thanks.
Paul/Benoit,
Should I also drop these lines from the file headers since they are no longer same as the outputs from autogen files?
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap at vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
regards,
Rajendra
Quoted 3 lines
Tony
Paul Walmsley
maintainercover Cleanup PRM and CM regbit headers
Quoted 10 lines · Rajendra Nayak
Paul/Benoit,
Should I also drop these lines from the file headers since they are no longer same as the outputs from autogen files?
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap at vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
Heh...
Here's my view:
You mentioned that these patches were generated with some kind of awk/grep scripting. Can you integrate that in an automated way into the autogeneration flow? If the answer is yes, then keep the header. If the answer is no, then the header should be dropped. Beno?t, maybe you have an opinion too?
As far as whether this should go in -rcX or not, my view is that, as a matter of policy, large changes like this should wait until v3.12. Now, having written that, I also was under the impression that the OMAP5 changes weren't going to be sent upstream unless the total diffstat would be balanced to roughly zero or negative lines. As far as I know, that didn't happen. So I guess, v3.11-rc it is... kernel development by diffstat :-(
Finally, please repost the whole series once you're done with your changes, as a non-RFC, along with your pull request (if you plan to send one). I guess I should be the one to take these, since I wound up taking the OMAP5 addition...
regards
- Paul
cover Cleanup PRM and CM regbit headers
Quoted 5 lines · Paul Walmsley
You mentioned that these patches were generated with some kind of awk/grep scripting. Can you integrate that in an automated way into the autogeneration flow? If the answer is yes, then keep the header. If the answer is no, then the header should be dropped. Beno?t, maybe you have an opinion too?
Ok, I'll try and integrate those scripts so all this can be done in an automated way even for newer SoCs.
Quoted 8 lines
As far as whether this should go in -rcX or not, my view is that, as a matter of policy, large changes like this should wait until v3.12. Now, having written that, I also was under the impression that the OMAP5 changes weren't going to be sent upstream unless the total diffstat would be balanced to roughly zero or negative lines. As far as I know, that didn't happen. So I guess, v3.11-rc it is... kernel development by diffstat :-(
I don't mind these going in -rcX or 3.12, either way is fine.
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Finally, please repost the whole series once you're done with your changes, as a non-RFC, along with your pull request (if you plan to send one). I guess I should be the one to take these, since I wound up taking the OMAP5 addition...
:) I thought so too that you should be the one sending the pull. I will post these out as non-RFC after I do a clean integration into the autogen scripts, and then you can take a call on sending the pull for either -rcX or 3.12
Tony Lindgren
maintainercover Cleanup PRM and CM regbit headers
Quoted 19 lines · Rajendra Nayak
Quoted 5 lines · Paul Walmsley
You mentioned that these patches were generated with some kind of awk/grep scripting. Can you integrate that in an automated way into the autogeneration flow? If the answer is yes, then keep the header. If the answer is no, then the header should be dropped. Beno?t, maybe you have an opinion too?
Ok, I'll try and integrate those scripts so all this can be done in an automated way even for newer SoCs.
Quoted 8 lines
As far as whether this should go in -rcX or not, my view is that, as a matter of policy, large changes like this should wait until v3.12. Now, having written that, I also was under the impression that the OMAP5 changes weren't going to be sent upstream unless the total diffstat would be balanced to roughly zero or negative lines. As far as I know, that didn't happen. So I guess, v3.11-rc it is... kernel development by diffstat :-(
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I don't mind these going in -rcX or 3.12, either way is fine.
Removal of unused code should be OK for the early -rc. I doubt that anybody would object it especially considering that's it's a huge pile of unused defines that most likely won't ever be needed for DT based booting.
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Finally, please repost the whole series once you're done with your changes, as a non-RFC, along with your pull request (if you plan to send one). I guess I should be the one to take these, since I wound up taking the OMAP5 addition...
:) I thought so too that you should be the one sending the pull. I will post these out as non-RFC after I do a clean integration into the autogen scripts, and then you can take a call on sending the pull for either -rcX or 3.12
I'd prefer to have it done now for the early -rc series. But if it drags on, we should not merge it during the -rc series.
Regards,
Tony