ARM: rockchip: add smp functionality

This series enables the use of the additional cores on Rockchip Cortex-A9 SoCs.

To achieve this, add the scu, the needed sram and power-management-unit.

Tested on both a BQ Curie2 (rk3066a / dual core) and on a Radxa Rock (rk3188 / quad core).

changes since v4:
- rebase on top of the recent rk3188 board support
- implement suggestion from Matt Sealey in moving the sram-limit from marking reserved regions to marking available regions - hopefully I got the usage right :-)
- remove __CPUINIT as suggested by Fabio Estevam

changes since v3:
- address comments from Rob Herring:
- split the gathering of the reserve-data into a separate loop
- spelling and style fixes
- first patch only included for reference, already part of the char-misc git tree

changes since v2:
- rework the sram allocation following the suggestion from Philipp Zabel

changes since v1:
- add reserved block feature for mmio-sram, to not use two logical sram nodes
- the sram content is kept intact while the device is running, so copying the trampoline is only needed once

Heiko Stuebner (5):
misc: sram: add ability to limit used sram areas
ARM: rockchip: add snoop-control-unit
ARM: rockchip: add sram dt nodes and documentation
ARM: rockchip: add power-management-unit dt node
ARM: rockchip: add smp bringup code

 .../devicetree/bindings/arm/rockchip/pmu.txt       |   16 ++
 .../devicetree/bindings/arm/rockchip/smp-sram.txt  |   24 +++
 Documentation/devicetree/bindings/misc/sram.txt    |    8 +
 arch/arm/boot/dts/rk3066a.dtsi                     |    6 +
 arch/arm/boot/dts/rk3188.dtsi                      |    6 +
 arch/arm/boot/dts/rk3xxx.dtsi                      |   10 +
 arch/arm/mach-rockchip/Kconfig                     |    1 +
 arch/arm/mach-rockchip/Makefile                    |    1 +
 arch/arm/mach-rockchip/core.h                      |   22 +++
 arch/arm/mach-rockchip/headsmp.S                   |   30 ++++
 arch/arm/mach-rockchip/platsmp.c                   |  195 ++++++++++++++++++++
 arch/arm/mach-rockchip/rockchip.c                  |    2 +
 drivers/misc/sram.c                                |   51 ++++-
 13 files changed, 368 insertions(+), 6 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/rockchip/pmu.txt
 create mode 100644 Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt
 create mode 100644 arch/arm/mach-rockchip/core.h
 create mode 100644 arch/arm/mach-rockchip/headsmp.S
 create mode 100644 arch/arm/mach-rockchip/platsmp.c

1.7.10.4

Some SoCs need parts of their sram for special purposes. So while being part of the peripheral, it should not be part of the genpool controlling the sram.

Therefore add an option available to keep arbitrary portions of the sram from being part of the pool. If available is not present, all sram is used.

move from marking reserved space to available space

---
 Documentation/devicetree/bindings/misc/sram.txt |    8 ++++
 drivers/misc/sram.c                             |   51 ++++++++++++++++++++---
 2 files changed, 53 insertions(+), 6 deletions(-)

index 4d0a00e..8be552f 100644
@@ -8,9 +8,17 @@ Required properties:
 
 - reg : SRAM iomem address range
 
+Optional properties:
+
+- available: optional list of available chunks inside the sram that the
+  OS can use. Without available, the whole range is usable for the OS.
+  Format is <base size>, <base size>, ...; with base being relative to the
+  reg property base.
+
 Example:
 
 sram: sram at 5c000000 {
 	compatible = "mmio-sram";
 	reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
+	available = <0x100 0x3ff00>;
 };

1.7.10.4

This adds the device-node and config select to enable the scu in all Rockchip Cortex-A9 SoCs.

---
 arch/arm/boot/dts/rk3xxx.dtsi  |    5 +++++
 arch/arm/mach-rockchip/Kconfig |    1 +
 2 files changed, 6 insertions(+)

index 0fcbcfd..0a3d5b1 100644
@@ -26,6 +26,11 @@
 		compatible = "simple-bus";
 		ranges;
 
+		scu at 1013c000 {
+			compatible = "arm,cortex-a9-scu";
+			reg = <0x1013c000 0x100>;
+		};
+
 		gic: interrupt-controller at 1013d000 {
 			compatible = "arm,cortex-a9-gic";
 			interrupt-controller;

index 6fef464..8700395 100644
@@ -5,6 +5,7 @@ config ARCH_ROCKCHIP
 	select ARCH_REQUIRE_GPIOLIB
 	select ARM_GIC
 	select CACHE_L2X0
+	select HAVE_ARM_SCU
 	select HAVE_ARM_TWD if LOCAL_TIMERS
 	select HAVE_SMP
 	select LOCAL_TIMERS if SMP

1.7.10.4

gaah, there I just learned about the arm at kernel.org address and still didn't remember when digging up this old recipient list - which of course resulted in Kevin not being included.

Additionally I also had the old devicetree list included.

So I'll do it again shortly :-)

Sorry for the noise
Heiko

Am Dienstag, 22. Oktober 2013, 16:00:13 schrieb Heiko St?bner: