PCI:Add SPEAr13xx PCie support

From: Pratyush Anand <[email protected]>

ST miphy40lp can be used with PCIe, SATA and Super Speed USB controllers. SPEAr13XX SoCs use this phy for PCIe and SATA.

Signed-off-by Pratyush Anand <[email protected]>

Cc Mohit Kumar <[email protected]>

Cc Arnd Bergmann <[email protected]>

Cc Viresh Kumar <[email protected]>

Cc Kishon Vijay Abraham I <[email protected]>

Cc [email protected]

Cc [email protected]

---
 .../devicetree/bindings/phy/st-miphy40lp.txt       |   18 ++++++++++++++++++
 1 files changed, 18 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt

Documentation/devicetree/bindings/phy/st-miphy40lp.txt new file +3 -0

new file mode 100644
index 0000000..1c8d04c
@@ -0,0 +1,18 @@
+ST miphy40lp DT detail
+===================================
+

-----Original Message-----
From: Mark Rutland [mailto:[email protected]]
Sent: Wednesday, February 12, 2014 11:50 PM
To: Mohit KUMAR DCG
Cc: [email protected]; Pratyush ANAND; Viresh Kumar; Kishon Vijay Abraham I; spear-devel; [email protected]
Subject: Re: [PATCH V6 03/12] phy: st-miphy40lp: Add binding information

Quoted 12 lines · Mohit Kumar

From: Pratyush Anand <[email protected]>

ST miphy40lp can be used with PCIe, SATA and Super Speed USB controllers. SPEAr13XX SoCs use this phy for PCIe and SATA.

Signed-off-by Pratyush Anand <[email protected]>

Cc Mohit Kumar <[email protected]>

Cc Arnd Bergmann <[email protected]>

Cc Viresh Kumar <[email protected]>

Cc Kishon Vijay Abraham I <[email protected]>

Cc [email protected]

Cc [email protected]

Quoted 2 lines

---
 .../devicetree/bindings/phy/st-miphy40lp.txt       |   18

++++++++++++++++++

Quoted 10 lines

 1 files changed, 18 insertions(+), 0 deletions(-)  create mode 100644

Documentation/devicetree/bindings/phy/st-miphy40lp.txt

Documentation/devicetree/bindings/phy/st-miphy40lp.txt new file +0 -0

new file mode 100644
index 0000000..1c8d04c

Documentation/devicetree/bindings/phy/st-miphy40lp.txt line 5

Quoted 5 lines

Documentation/devicetree/bindings/phy/st-miphy40lp.txt new file +5 -0

@@ -0,0 +1,18 @@
+ST miphy40lp DT detail
+===================================
+
+miphy40lp is a phy controller from ST Microelectronics which supports
+PCIe, SATA and Super Speed USB host and devices. It has been used in

SPEAr13xx SOCs.

Documentation/devicetree/bindings/phy/st-miphy40lp.txt line 13

Quoted 8 lines

Documentation/devicetree/bindings/phy/st-miphy40lp.txt new file +8 -0

+
+Required properties:
+- compatible : should be "st,miphy40lp-phy"
+	Other supported soc specific compatible:
+		"st,spear1310-miphy"
+		"st,spear1340-miphy"
+- reg : offset and length of the PHY register set.
+- misc: phandle for the syscon node to access misc registers

This is very vague. What is this used for?

Documentation/devicetree/bindings/phy/st-miphy40lp.txt line 18

Quoted 6 lines

Documentation/devicetree/bindings/phy/st-miphy40lp.txt new file +5 -0

+- phy-id: Instance id of the phy.
+- #phy-cells : from the generic PHY bindings, must be 1.
+	- 1st cell: phandle to the phy node.
+	- 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
+	  and 2 for Super Speed USB.

One cell or two?

Hello Mark,

Quoted 40 lines

-----Original Message-----
From: Mark Rutland [mailto:[email protected]]
Sent: Wednesday, February 12, 2014 11:50 PM
To: Mohit KUMAR DCG
Cc: [email protected]; Pratyush ANAND; Viresh Kumar; Kishon Vijay Abraham I; spear-devel; [email protected]
Subject: Re: [PATCH V6 03/12] phy: st-miphy40lp: Add binding information

Quoted 12 lines · Mohit Kumar

From: Pratyush Anand <[email protected]>

ST miphy40lp can be used with PCIe, SATA and Super Speed USB controllers. SPEAr13XX SoCs use this phy for PCIe and SATA.

Signed-off-by Pratyush Anand <[email protected]>

Cc Mohit Kumar <[email protected]>

Cc Arnd Bergmann <[email protected]>

Cc Viresh Kumar <[email protected]>

Cc Kishon Vijay Abraham I <[email protected]>

Cc [email protected]

Cc [email protected]

Quoted 2 lines

---
 .../devicetree/bindings/phy/st-miphy40lp.txt       |   18

++++++++++++++++++

Quoted 10 lines

 1 files changed, 18 insertions(+), 0 deletions(-)  create mode 100644

Documentation/devicetree/bindings/phy/st-miphy40lp.txt

Documentation/devicetree/bindings/phy/st-miphy40lp.txt new file +0 -0

new file mode 100644
index 0000000..1c8d04c

Documentation/devicetree/bindings/phy/st-miphy40lp.txt line 5

Quoted 5 lines

Documentation/devicetree/bindings/phy/st-miphy40lp.txt new file +5 -0

@@ -0,0 +1,18 @@
+ST miphy40lp DT detail
+===================================
+
+miphy40lp is a phy controller from ST Microelectronics which supports
+PCIe, SATA and Super Speed USB host and devices. It has been used in

SPEAr13xx SOCs.

Quoted 10 lines

Documentation/devicetree/bindings/phy/st-miphy40lp.txt line 13

Quoted 8 lines

Documentation/devicetree/bindings/phy/st-miphy40lp.txt new file +8 -0

+
+Required properties:
+- compatible : should be "st,miphy40lp-phy"
+	Other supported soc specific compatible:
+		"st,spear1310-miphy"
+		"st,spear1340-miphy"
+- reg : offset and length of the PHY register set.
+- misc: phandle for the syscon node to access misc registers

This is very vague. What is this used for?

- These are Spear SoC specific miscellaneous registers. Here these are used for to configure sata/pcie aux clock.

Quoted 8 lines

Documentation/devicetree/bindings/phy/st-miphy40lp.txt line 18

Quoted 6 lines

Documentation/devicetree/bindings/phy/st-miphy40lp.txt new file +5 -0

+- phy-id: Instance id of the phy.
+- #phy-cells : from the generic PHY bindings, must be 1.
+	- 1st cell: phandle to the phy node.
+	- 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
+	  and 2 for Super Speed USB.

One cell or two?

- No of cells are two, is this the question?

Quoted 10 lines

- These are Spear SoC specific miscellaneous registers. Here these are used for to configure sata/pcie aux clock.

Quoted 7 lines

Quoted 6 lines

+- phy-id: Instance id of the phy.
+- #phy-cells : from the generic PHY bindings, must be 1.

+ - 1st cell: phandle to the phy node.
+ - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
+ and 2 for Super Speed USB.

Quoted 3 lines

Quoted 1 line

One cell or two?

- No of cells are two, is this the question?

The description of #phy-cells says it must be 1. Presumably it must be 2.

Quoted 12 lines · Mark Rutland

Quoted 12 lines

- These are Spear SoC specific miscellaneous registers. Here these are used for to configure sata/pcie aux clock.

Quoted 8 lines

Quoted 6 lines

+- phy-id: Instance id of the phy.
+- #phy-cells : from the generic PHY bindings, must be 1.

+ - 1st cell: phandle to the phy node.
+ - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
+ and 2 for Super Speed USB.

One cell or two?

Quoted 3 lines

Quoted 1 line

- No of cells are two, is this the question?

The description of #phy-cells says it must be 1. Presumably it must be 2.

The description here is counting the phandle, while we normally only count the arguments following the phandle. #phy-cells=<1> is correct here, but the description should be written a bit clearer.

From: Pratyush Anand <[email protected]>

SPEAr SOCs have some miscellaneous registers which are used to configure few properties of different peripheral controllers.

Signed-off-by Pratyush Anand <[email protected]>

Cc Mohit Kumar <[email protected]>

Cc Arnd Bergmann <[email protected]>

Cc Viresh Kumar <[email protected]>

Cc [email protected]

Cc [email protected]

---
 .../devicetree/bindings/arm/spear-misc.txt         |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt

Documentation/devicetree/bindings/arm/spear-misc.txt new file +0 -0

new file mode 100644
index 0000000..ab324e1

-----Original Message-----
From: Mark Rutland [mailto:[email protected]]
Sent: Wednesday, February 12, 2014 11:51 PM
To: Mohit KUMAR DCG
Cc: [email protected]; Pratyush ANAND; Viresh Kumar; spear-devel; [email protected]
Subject: Re: [PATCH V6 05/12] SPEAr: misc: Add binding information

Quoted 26 lines · Mohit Kumar

From: Pratyush Anand <[email protected]>

SPEAr SOCs have some miscellaneous registers which are used to configure few properties of different peripheral controllers.

Signed-off-by Pratyush Anand <[email protected]>

Cc Mohit Kumar <[email protected]>

Cc Arnd Bergmann <[email protected]>

Cc Viresh Kumar <[email protected]>

Cc [email protected]

Cc [email protected]

---
 .../devicetree/bindings/arm/spear-misc.txt         |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)  create mode 100644

Documentation/devicetree/bindings/arm/spear-misc.txt

Documentation/devicetree/bindings/arm/spear-misc.txt new file +3 -0

new file mode 100644
index 0000000..ab324e1
@@ -0,0 +1,9 @@
+SPEAr Misc configuration
+===========================
+SPEAr SOCs have some miscellaneous registers which are used to

Documentation/devicetree/bindings/arm/spear-misc.txt line 9

Quoted 6 lines

Documentation/devicetree/bindings/arm/spear-misc.txt new file +6 -0

+configure few properties of different peripheral controllers.
+
+misc node required properties:
+
+- compatible Should be	"st,spear1340-misc", "syscon".
+- reg: Address range of misc space

Is there no better name than misc?

How big is this expected to be?

From: Pratyush Anand <[email protected]>

ST miphy40lp supports PCIe, SATA and Super Speed USB. This driver adds skeleton support for the same.

This skeleton defines function corresponding to phy ops as well as sleep pm ops. Any platform using this phy can add its own platform specific ops(if needed) corresponding to each phy ops.

Phy specific modifications will require phy register space, which is passed from DT as a resource. Currently only SPEAr1310 and SPEAr1340 are known user of this phy, which do not need to modify phy registers normally. Therefore we have not retrieved phy base address from DT and hence not io-remapped it. However, same can be added in future if required.

SoC specific modifications should be done in plat specific ops and phy specific modifications should be done in phy ops itself. As a general rule, follow the convention of modifying misc reg space in plat ops and phy reg space in phy ops.

Signed-off-by Pratyush Anand <[email protected]>

Tested-by Mohit Kumar <[email protected]>

Cc Arnd Bergmann <[email protected]>

Cc Viresh Kumar <[email protected]>

Cc Kishon Vijay Abraham I <[email protected]>

Cc [email protected]

Cc [email protected]

---
 drivers/phy/Kconfig         |    7 ++
 drivers/phy/Makefile        |    1 +
 drivers/phy/phy-miphy40lp.c |  234 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 242 insertions(+), 0 deletions(-)
 create mode 100644 drivers/phy/phy-miphy40lp.c

drivers/phy/Kconfig +7 -0

index afa2354..ed5b4f3 100644
@@ -64,4 +64,11 @@ config BCM_KONA_USB2_PHY
 	help
 	  Enable this to support the Broadcom Kona USB 2.0 PHY.
 
+config PHY_ST_MIPHY40LP
+	tristate "ST MIPHY 40LP driver"
+	select GENERIC_PHY
+	help
+	  Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB.
+	  SPEAr13xx SoCs have used this PHY internally for PCIe and SATA implementation.
+
 endmenu

drivers/phy/Makefile +1 -0

index b57c253..c061091 100644
@@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
 obj-$(CONFIG_PHY_MVEBU_SATA)		+= phy-mvebu-sata.o
 obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
 obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
+obj-$(CONFIG_PHY_ST_MIPHY40LP)		+= phy-miphy40lp.o

drivers/phy/phy-miphy40lp.c new file +12 -0

new file mode 100644
index 0000000..98859ff
@@ -0,0 +1,234 @@
+/*
+ * ST MiPHY-40LP PHY driver
+ *
+ * Copyright (C) 2014 ST Microelectronics
+ * Pratyush Anand <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+

drivers/phy/phy-miphy40lp.c new file +52 -0

+	SATA,
+	PCIE,
+	SS_USB,
+};
+
+struct miphy40lp_priv;
+
+/* platform specific function struct */
+struct miphy40lp_plat_ops {
+	int	(*plat_init)(struct miphy40lp_priv *priv);
+	int	(*plat_exit)(struct miphy40lp_priv *priv);
+	int	(*plat_power_off)(struct miphy40lp_priv *priv);
+	int	(*plat_power_on)(struct miphy40lp_priv *priv);
+	int	(*plat_suspend)(struct miphy40lp_priv *priv);
+	int	(*plat_resume)(struct miphy40lp_priv *priv);
+};
+
+struct miphy40lp_priv {
+	/* regmap for any soc specific misc registers */
+	struct regmap			*misc;
+	/* phy struct pointer */
+	struct phy			*phy;
+	/* phy mode: 0 for SATA 1 for PCIe and 2 for SS-USB */
+	enum phy_mode			mode;
+	/* instance id of this phy */
+	u32				id;
+	/* platform specific callbacks */
+	const struct miphy40lp_plat_ops	*plat_ops;
+};
+
+static int miphy40lp_init(struct phy *phy)
+{
+	struct miphy40lp_priv *priv = phy_get_drvdata(phy);
+	const struct miphy40lp_plat_ops *ops = priv->plat_ops;
+	int ret = 0;
+
+	if (ops && ops->plat_init)
+		ret = ops->plat_init(priv);
+
+	return ret;
+}
+
+static int miphy40lp_exit(struct phy *phy)
+{
+	struct miphy40lp_priv *priv = phy_get_drvdata(phy);
+	const struct miphy40lp_plat_ops *ops = priv->plat_ops;
+	int ret = 0;
+
+	if (ops && ops->plat_exit)
+		ret = ops->plat_exit(priv);
+
+	return ret;

drivers/phy/phy-miphy40lp.c new file +60 -0

+
+	return ret;
+}
+
+static int miphy40lp_power_on(struct phy *phy)
+{
+	struct miphy40lp_priv *priv = phy_get_drvdata(phy);
+	const struct miphy40lp_plat_ops *ops = priv->plat_ops;
+	int ret = 0;
+
+	if (ops && ops->plat_power_on)
+		ret = ops->plat_power_on(priv);
+
+	return ret;
+}
+
+static const struct of_device_id miphy40lp_of_match[] = {
+	{ .compatible = "st,miphy40lp-phy", .data = NULL },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, miphy40lp_of_match);
+
+static struct phy_ops miphy40lp_ops = {
+	.init = miphy40lp_init,
+	.exit = miphy40lp_exit,
+	.power_off = miphy40lp_power_off,
+	.power_on = miphy40lp_power_on,
+	.owner = THIS_MODULE,
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int miphy40lp_suspend(struct device *dev)
+{
+	struct miphy40lp_priv *priv = dev_get_drvdata(dev);
+	const struct miphy40lp_plat_ops *ops = priv->plat_ops;
+	int ret = 0;
+
+	if (ops && ops->plat_suspend)
+		ret = ops->plat_suspend(priv);
+
+	return ret;
+}
+
+static int miphy40lp_resume(struct device *dev)
+{
+	struct miphy40lp_priv *priv = dev_get_drvdata(dev);
+	const struct miphy40lp_plat_ops *ops = priv->plat_ops;
+	int ret = 0;
+
+	if (ops && ops->plat_resume)
+		ret = ops->plat_resume(priv);
+
+	return ret;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(miphy40lp_pm_ops, miphy40lp_suspend,
+		miphy40lp_resume);
+
+static struct phy *miphy40lp_xlate(struct device *dev,

-----Original Message-----
From: Kishon Vijay Abraham I [mailto:[email protected]]
Sent: Tuesday, February 11, 2014 5:05 PM
To: Mohit KUMAR DCG; [email protected]
Cc: Pratyush ANAND; Viresh Kumar; spear-devel; linux- [email protected]
Subject: Re: [PATCH V6 04/12] phy: st-miphy40lp: Add skeleton driver

Hi,

Quoted 41 lines · Mohit Kumar

From: Pratyush Anand <[email protected]>

ST miphy40lp supports PCIe, SATA and Super Speed USB. This driver adds skeleton support for the same.

This skeleton defines function corresponding to phy ops as well as sleep pm ops. Any platform using this phy can add its own platform specific ops(if needed) corresponding to each phy ops.

Phy specific modifications will require phy register space, which is passed from DT as a resource. Currently only SPEAr1310 and SPEAr1340 are known user of this phy, which do not need to modify phy registers normally. Therefore we have not retrieved phy base address from DT and hence not io-remapped it. However, same can be added in future if required.

SoC specific modifications should be done in plat specific ops and phy specific modifications should be done in phy ops itself. As a general rule, follow the convention of modifying misc reg space in plat ops and phy reg space in phy ops.

Signed-off-by Pratyush Anand <[email protected]>

Tested-by Mohit Kumar <[email protected]>

Cc Arnd Bergmann <[email protected]>

Cc Viresh Kumar <[email protected]>

Cc Kishon Vijay Abraham I <[email protected]>

Cc [email protected]

Cc [email protected]

---
 drivers/phy/Kconfig         |    7 ++
 drivers/phy/Makefile        |    1 +
 drivers/phy/phy-miphy40lp.c |  234
+++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 242 insertions(+), 0 deletions(-)  create mode

100644 drivers/phy/phy-miphy40lp.c

drivers/phy/Kconfig index renamed from drivers/phy/Kconfig +0 -0

afa2354..ed5b4f3 100644

drivers/phy/Kconfig config BCM_KONA_USB2_PHY · line 71

Quoted 8 lines

drivers/phy/Kconfig +5 -0

@@ -64,4 +64,11 @@ config BCM_KONA_USB2_PHY
 	help
 	  Enable this to support the Broadcom Kona USB 2.0 PHY.
 
+config PHY_ST_MIPHY40LP
+	tristate "ST MIPHY 40LP driver"
+	select GENERIC_PHY
+	help
+	  Support for ST MIPHY 40LP which can be used for PCIe, SATA and

Super Speed USB.

drivers/phy/Kconfig config BCM_KONA_USB2_PHY · line 72

Quoted 1 line

drivers/phy/Kconfig +1 -0

+	  SPEAr13xx SoCs have used this PHY internally for PCIe and SATA

implementation.

drivers/phy/Makefile obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) +=

Quoted 7 lines

drivers/phy/Kconfig +1 -0

+
 endmenu

drivers/phy/Makefile index renamed from drivers/phy/Makefile +0 -0

b57c253..c061091 100644

drivers/phy/Makefile +0 -0

@@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+=

phy-exynos-mipi-video.o

Quoted 25 lines

drivers/phy/Makefile +1 -0

 obj-$(CONFIG_PHY_MVEBU_SATA)		+= phy-mvebu-sata.o
 obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
 obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
+obj-$(CONFIG_PHY_ST_MIPHY40LP)		+= phy-miphy40lp.o

drivers/phy/phy-miphy40lp.c new file +16 -0

new file mode 100644 index 0000000..98859ff
@@ -0,0 +1,234 @@
+/*
+ * ST MiPHY-40LP PHY driver
+ *
+ * Copyright (C) 2014 ST Microelectronics
+ * Pratyush Anand <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/kernel.h>

drivers/phy/phy-miphy40lp.c line 22

Quoted 7 lines

drivers/phy/phy-miphy40lp.c new file +7 -0

+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+
+enum phy_mode {

miphy40lp_phy_mode?

Quoted 52 lines

drivers/phy/phy-miphy40lp.c new file +52 -0

+	SATA,
+	PCIE,
+	SS_USB,
+};
+
+struct miphy40lp_priv;
+
+/* platform specific function struct */ struct miphy40lp_plat_ops {
+	int	(*plat_init)(struct miphy40lp_priv *priv);
+	int	(*plat_exit)(struct miphy40lp_priv *priv);
+	int	(*plat_power_off)(struct miphy40lp_priv *priv);
+	int	(*plat_power_on)(struct miphy40lp_priv *priv);
+	int	(*plat_suspend)(struct miphy40lp_priv *priv);
+	int	(*plat_resume)(struct miphy40lp_priv *priv);
+};
+
+struct miphy40lp_priv {
+	/* regmap for any soc specific misc registers */
+	struct regmap			*misc;
+	/* phy struct pointer */
+	struct phy			*phy;
+	/* phy mode: 0 for SATA 1 for PCIe and 2 for SS-USB */
+	enum phy_mode			mode;
+	/* instance id of this phy */
+	u32				id;
+	/* platform specific callbacks */
+	const struct miphy40lp_plat_ops	*plat_ops;
+};
+
+static int miphy40lp_init(struct phy *phy) {
+	struct miphy40lp_priv *priv = phy_get_drvdata(phy);
+	const struct miphy40lp_plat_ops *ops = priv->plat_ops;
+	int ret = 0;
+
+	if (ops && ops->plat_init)
+		ret = ops->plat_init(priv);
+
+	return ret;
+}
+
+static int miphy40lp_exit(struct phy *phy) {
+	struct miphy40lp_priv *priv = phy_get_drvdata(phy);
+	const struct miphy40lp_plat_ops *ops = priv->plat_ops;
+	int ret = 0;
+
+	if (ops && ops->plat_exit)
+		ret = ops->plat_exit(priv);
+
+	return ret;
+}
+
+static int miphy40lp_power_off(struct phy *phy) {

drivers/phy/phy-miphy40lp.c line 60

Quoted 6 lines

drivers/phy/phy-miphy40lp.c new file +6 -0

+	struct miphy40lp_priv *priv = phy_get_drvdata(phy);
+	const struct miphy40lp_plat_ops *ops = priv->plat_ops;
+	int ret = 0;
+
+	if (ops && ops->plat_init)
+		ret = ops->plat_init(priv);

plat_power_off here..

Quoted 61 lines

drivers/phy/phy-miphy40lp.c new file +61 -0

+
+	return ret;
+}
+
+static int miphy40lp_power_on(struct phy *phy) {
+	struct miphy40lp_priv *priv = phy_get_drvdata(phy);
+	const struct miphy40lp_plat_ops *ops = priv->plat_ops;
+	int ret = 0;
+
+	if (ops && ops->plat_power_on)
+		ret = ops->plat_power_on(priv);
+
+	return ret;
+}
+
+static const struct of_device_id miphy40lp_of_match[] = {
+	{ .compatible = "st,miphy40lp-phy", .data = NULL },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, miphy40lp_of_match);
+
+static struct phy_ops miphy40lp_ops = {
+	.init = miphy40lp_init,
+	.exit = miphy40lp_exit,
+	.power_off = miphy40lp_power_off,
+	.power_on = miphy40lp_power_on,
+	.owner = THIS_MODULE,
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int miphy40lp_suspend(struct device *dev) {
+	struct miphy40lp_priv *priv = dev_get_drvdata(dev);
+	const struct miphy40lp_plat_ops *ops = priv->plat_ops;
+	int ret = 0;
+
+	if (ops && ops->plat_suspend)
+		ret = ops->plat_suspend(priv);
+
+	return ret;
+}
+
+static int miphy40lp_resume(struct device *dev) {
+	struct miphy40lp_priv *priv = dev_get_drvdata(dev);
+	const struct miphy40lp_plat_ops *ops = priv->plat_ops;
+	int ret = 0;
+
+	if (ops && ops->plat_resume)
+		ret = ops->plat_resume(priv);
+
+	return ret;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(miphy40lp_pm_ops, miphy40lp_suspend,
+		miphy40lp_resume);
+
+static struct phy *miphy40lp_xlate(struct device *dev,
+					struct of_phandle_args *args)
+{
+	struct miphy40lp_priv *priv = dev_get_drvdata(dev);
+

drivers/phy/phy-miphy40lp.c line 154

Quoted 6 lines

drivers/phy/phy-miphy40lp.c new file +6 -0

+	if (args->args_count < 1) {
+		dev_err(dev, "DT did not pass correct no of args\n");
+		return NULL;
+	}
+
+	priv->mode = args->args[0];

Lets add error checking here if the mode is incorrect.

Thanks
Kishon

From: Pratyush Anand <[email protected]>

ahci driver needs some platform specific functions which are called at init, exit, suspend and resume conditions. Till now these functions were present in a platform driver with a fixme notes.

Similar functions modifying same set of registers will also be needed in case of PCIe phy init/exit.

So move all these SATA platform code to phy-miphy40lp driver.

Signed-off-by Pratyush Anand <[email protected]>

Tested-by Mohit Kumar <[email protected]>

Cc Arnd Bergmann <[email protected]>

Cc Viresh Kumar <[email protected]>

Cc Tejun Heo <[email protected]>

Cc Kishon Vijay Abraham I <[email protected]>

Cc spear-devel at list.st.com

Cc linux-arm-kernel at lists.infradead.org

Cc linux-kernel at vger.kernel.org

---
 arch/arm/boot/dts/spear1310-evb.dts |    4 +
 arch/arm/boot/dts/spear1310.dtsi    |   39 +++++++++-
 arch/arm/boot/dts/spear1340-evb.dts |    4 +
 arch/arm/boot/dts/spear1340.dtsi    |   13 +++-
 arch/arm/boot/dts/spear13xx.dtsi    |    5 +
 arch/arm/mach-spear/Kconfig         |    2 +
 arch/arm/mach-spear/spear1340.c     |  127 +------------------------------
 drivers/phy/phy-miphy40lp.c         |  144 +++++++++++++++++++++++++++++++++++
 8 files changed, 208 insertions(+), 130 deletions(-)

arch/arm/boot/dts/spear1310-evb.dts +4 -0

index b56a801..d42c84b 100644
@@ -106,6 +106,10 @@
 			status = "okay";
 		};
 
+		miphy at eb800000 {
+			status = "okay";
+		};
+
 		cf at b2800000 {
 			status = "okay";
 		};

arch/arm/boot/dts/spear1310.dtsi +36 -3

index 122ae94..64e7dd5 100644
@@ -29,24 +29,57 @@
 			#gpio-cells = <2>;
 		};
 
-		ahci at b1000000 {
+		miphy0: miphy at eb800000 {
+			compatible = "st,miphy", "st,spear1310-miphy";
+			reg = <0xeb800000 0x4000>;
+			misc = <&misc>;
+			phy-id = <0>;
+			#phy-cells = <1>;
+			status = "disabled";
+		};
+
+		miphy1: miphy at eb804000 {
+			compatible = "st,miphy", "st,spear1310-miphy";
+			reg = <0xeb804000 0x4000>;
+			misc = <&misc>;
+			phy-id = <1>;
+			#phy-cells = <1>;
+			status = "disabled";
+		};
+
+		miphy2: miphy at eb808000 {
+			compatible = "st,miphy", "st,spear1310-miphy";
+			reg = <0xeb808000 0x4000>;
+			misc = <&misc>;
+			phy-id = <2>;
+			#phy-cells = <1>;
+			status = "disabled";
+		};
+
+		ahci0: ahci at b1000000 {
 			compatible = "snps,spear-ahci";
 			reg = <0xb1000000 0x10000>;
 			interrupts = <0 68 0x4>;
+			phys = <&miphy0 0>;
+			phy-names = "sata-phy";
 			status = "disabled";
 		};
 
-		ahci at b1800000 {
+		ahci1: ahci at b1800000 {
 			compatible = "snps,spear-ahci";
 			reg = <0xb1800000 0x10000>;
 			interrupts = <0 69 0x4>;
+			phys = <&miphy1 0>;
+			phy-names = "sata-phy";
 			status = "disabled";
 		};
 
-		ahci at b4000000 {
+		ahci2: ahci at b4000000 {
 			compatible = "snps,spear-ahci";
 			reg = <0xb4000000 0x10000>;
 			interrupts = <0 70 0x4>;
+			phys = <&miphy2 0>;
+			phy-names = "sata-phy";
 			status = "disabled";
 		};
 

arch/arm/boot/dts/spear1340-evb.dts +4 -0

index d6c30ae..b23e05e 100644
@@ -122,6 +122,10 @@
 			status = "okay";
 		};
 
+		miphy at eb800000 {
+			status = "okay";
+		};
+
 		dma at ea800000 {
 			status = "okay";
 		};

arch/arm/boot/dts/spear1340.dtsi +12 -1

index 54d128d..7e3a04b 100644
@@ -31,10 +31,21 @@
 			status = "disabled";
 		};
 
-		ahci at b1000000 {
+		miphy0: miphy at eb800000 {
+			compatible = "st,miphy", "st,spear1340-miphy";
+			reg = <0xeb800000 0x4000>;
+			misc = <&misc>;
+			phy-id = <0>;
+			#phy-cells = <1>;
+			status = "disabled";
+		};
+
+		ahci0: ahci at b1000000 {
 			compatible = "snps,spear-ahci";
 			reg = <0xb1000000 0x10000>;
 			interrupts = <0 72 0x4>;
+			phys = <&miphy0 0>;
+			phy-names = "sata-phy";
 			status = "disabled";
 		};
 

arch/arm/boot/dts/spear13xx.dtsi +5 -0

index 4382547..3a72508 100644
@@ -220,6 +220,11 @@
 				  0xd8000000 0xd8000000 0x01000000
 				  0xe0000000 0xe0000000 0x10000000>;
 
+			misc: syscon at e0700000 {
+				compatible = "st,spear1340-misc", "syscon";
+				reg = <0xe0700000 0x1000>;
+			};
+
 			gpio0: gpio at e0600000 {
 				compatible = "arm,pl061", "arm,primecell";
 				reg = <0xe0600000 0x1000>;

arch/arm/mach-spear/Kconfig +2 -0

index ac1710e..7e7f1b0 100644
@@ -26,6 +26,8 @@ config ARCH_SPEAR13XX
 	select MIGHT_HAVE_CACHE_L2X0
 	select PINCTRL
 	select USE_OF
+	select MFD_SYSCON
+	select PHY_ST_MIPHY40LP
 	help
 	  Supports for ARM's SPEAR13XX family
 

arch/arm/mach-spear/spear1340.c +1 -126

index 3fb6834..8e27093 100644
@@ -11,138 +11,13 @@
  * warranty of any kind, whether express or implied.
  */
 
-#define pr_fmt(fmt) "SPEAr1340: " fmt
-
-#include <linux/ahci_platform.h>
-#include <linux/amba/serial.h>
-#include <linux/delay.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include "generic.h"
-#include <mach/spear.h>
-
-/* FIXME: Move SATA PHY code into a standalone driver */
-
-/* Base addresses */
-#define SPEAR1340_SATA_BASE			UL(0xB1000000)
-
-/* Power Management Registers */
-#define SPEAR1340_PCM_CFG			(VA_MISC_BASE + 0x100)
-#define SPEAR1340_PCM_WKUP_CFG			(VA_MISC_BASE + 0x104)
-#define SPEAR1340_SWITCH_CTR			(VA_MISC_BASE + 0x108)
-
-#define SPEAR1340_PERIP1_SW_RST			(VA_MISC_BASE + 0x318)
-#define SPEAR1340_PERIP2_SW_RST			(VA_MISC_BASE + 0x31C)
-#define SPEAR1340_PERIP3_SW_RST			(VA_MISC_BASE + 0x320)
-
-/* PCIE - SATA configuration registers */
-#define SPEAR1340_PCIE_SATA_CFG			(VA_MISC_BASE + 0x424)
-	/* PCIE CFG MASks */
-	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)
-	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
-	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
-	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
-	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
-	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
-	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)
-	#define SPEAR1340_SATA_CFG_PM_CLK_EN		(1 << 1)
-	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
-	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
-	#define SPEAR1340_SATA_PCIE_CFG_MASK		0xF1F
-	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
-			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
-			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
-			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
-			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
-	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \
-			SPEAR1340_SATA_CFG_PM_CLK_EN | \
-			SPEAR1340_SATA_CFG_POWERUP_RESET | \
-			SPEAR1340_SATA_CFG_RX_CLK_EN | \
-			SPEAR1340_SATA_CFG_TX_CLK_EN)
-
-#define SPEAR1340_PCIE_MIPHY_CFG		(VA_MISC_BASE + 0x428)
-	#define SPEAR1340_MIPHY_OSC_BYPASS_EXT		(1 << 31)
-	#define SPEAR1340_MIPHY_CLK_REF_DIV2		(1 << 27)
-	#define SPEAR1340_MIPHY_CLK_REF_DIV4		(2 << 27)
-	#define SPEAR1340_MIPHY_CLK_REF_DIV8		(3 << 27)
-	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
-	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
-			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
-			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
-			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
-	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
-			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
-	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
-			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
-			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
-
-/* SATA device registration */
-static int sata_miphy_init(struct device *dev, void __iomem *addr)
-{
-	writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG);
-	writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK,
-			SPEAR1340_PCIE_MIPHY_CFG);
-	/* Switch on sata power domain */
-	writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG);
-	msleep(20);
-	/* Disable PCIE SATA Controller reset */
-	writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)),
-			SPEAR1340_PERIP1_SW_RST);
-	msleep(20);
-
-	return 0;
-}
-
-void sata_miphy_exit(struct device *dev)
-{
-	writel(0, SPEAR1340_PCIE_SATA_CFG);
-	writel(0, SPEAR1340_PCIE_MIPHY_CFG);
-
-	/* Enable PCIE SATA Controller reset */
-	writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)),
-			SPEAR1340_PERIP1_SW_RST);
-	msleep(20);
-	/* Switch off sata power domain */
-	writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG);
-	msleep(20);
-}
-
-int sata_suspend(struct device *dev)
-{
-	if (dev->power.power_state.event == PM_EVENT_FREEZE)
-		return 0;
-
-	sata_miphy_exit(dev);
-
-	return 0;
-}
-
-int sata_resume(struct device *dev)
-{
-	if (dev->power.power_state.event == PM_EVENT_THAW)
-		return 0;
-
-	return sata_miphy_init(dev, NULL);
-}
-
-static struct ahci_platform_data sata_pdata = {
-	.init = sata_miphy_init,
-	.exit = sata_miphy_exit,
-	.suspend = sata_suspend,
-	.resume = sata_resume,
-};
-
-/* Add SPEAr1340 auxdata to pass platform data */
-static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
-	OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
-			&sata_pdata),
-	{}
-};
 
 static void __init spear1340_dt_init(void)
 {
-	of_platform_populate(NULL, of_default_bus_match_table,
-			spear1340_auxdata_lookup, NULL);
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static const char * const spear1340_dt_board_compat[] = {

drivers/phy/phy-miphy40lp.c +2 -0

index 98859ff..16da55b 100644
@@ -8,8 +8,10 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
+ * 04/02/2014: Adding support of SATA mode for SPEAr1340.
  */
 
+#include <linux/bitops.h>
 #include <linux/delay.h>
 #include <linux/dma-mapping.h>
 #include <linux/kernel.h>

drivers/phy/phy-miphy40lp.c +28 -0

+#define SPEAR1340_PCM_WKUP_CFG			0x104
+#define SPEAR1340_SWITCH_CTR			0x108
+
+#define SPEAR1340_PERIP1_SW_RST			0x318
+	#define SPEAR1340_PERIP1_SW_RSATA		BIT(12)
+#define SPEAR1340_PERIP2_SW_RST			0x31C
+#define SPEAR1340_PERIP3_SW_RST			0x320
+
+/* PCIE - SATA configuration registers */
+#define SPEAR1340_PCIE_SATA_CFG			0x424
+	/* PCIE CFG MASks */
+	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	BIT(11)
+	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	BIT(10)
+	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		BIT(9)
+	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		BIT(8)
+	#define SPEAR1340_SATA_CFG_TX_CLK_EN		BIT(4)
+	#define SPEAR1340_SATA_CFG_RX_CLK_EN		BIT(3)
+	#define SPEAR1340_SATA_CFG_POWERUP_RESET	BIT(2)
+	#define SPEAR1340_SATA_CFG_PM_CLK_EN		BIT(1)
+	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
+	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
+	#define SPEAR1340_PCIE_SATA_CFG_MASK		0xF1F
+	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
+			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
+			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
+			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
+			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
+	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \

drivers/phy/phy-miphy40lp.c +99 -0

+	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
+	#define SPEAR1340_PCIE_MIPHY_CFG_MASK		0xF80000FF
+	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
+			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
+			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
+	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
+	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
+			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
+
 enum phy_mode {
 	SATA,
 	PCIE,

@@ -50,6 +106,93 @@ struct miphy40lp_priv {
 	const struct miphy40lp_plat_ops	*plat_ops;
 };
 
+static int miphy40lp_spear1340_sata_init(struct miphy40lp_priv *priv)
+{
+	regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+			SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
+	regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+			SPEAR1340_PCIE_MIPHY_CFG_MASK,
+			SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
+	/* Switch on sata power domain */
+	regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
+			SPEAR1340_PCM_CFG_SATA_POWER_EN,
+			SPEAR1340_PCM_CFG_SATA_POWER_EN);
+	msleep(20);
+	/* Disable PCIE SATA Controller reset */
+	regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
+			SPEAR1340_PERIP1_SW_RSATA, 0);
+	msleep(20);
+
+	return 0;
+}
+
+static int miphy40lp_spear1340_sata_exit(struct miphy40lp_priv *priv)
+{
+	regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+			SPEAR1340_PCIE_SATA_CFG_MASK, 0);
+	regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+			SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
+
+	/* Enable PCIE SATA Controller reset */
+	regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
+			SPEAR1340_PERIP1_SW_RSATA,
+			SPEAR1340_PERIP1_SW_RSATA);
+	msleep(20);
+	/* Switch off sata power domain */
+	regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
+			SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
+	msleep(20);
+
+	return 0;
+}
+
+static int miphy40lp_spear1340_init(struct miphy40lp_priv *priv)
+{
+	int ret = 0;
+
+	if (priv->mode == SATA)
+		ret = miphy40lp_spear1340_sata_init(priv);
+
+	return ret;
+}
+
+static int miphy40lp_spear1340_exit(struct miphy40lp_priv *priv)
+{
+	int ret = 0;
+
+	if (priv->mode == SATA)
+		ret = miphy40lp_spear1340_sata_exit(priv);
+
+	return ret;
+}
+
+static int miphy40lp_spear1340_suspend(struct miphy40lp_priv *priv)
+{
+	int ret = 0;
+
+	if (priv->mode == SATA)
+		ret = miphy40lp_spear1340_sata_exit(priv);
+
+	return ret;
+}
+
+static int miphy40lp_spear1340_resume(struct miphy40lp_priv *priv)
+{
+	int ret = 0;
+
+	if (priv->mode == SATA)
+		ret = miphy40lp_spear1340_sata_init(priv);
+
+	return ret;
+}
+
+static struct miphy40lp_plat_ops spear1340_phy_ops = {
+	.plat_init = miphy40lp_spear1340_init,
+	.plat_exit = miphy40lp_spear1340_exit,
+	.plat_suspend = miphy40lp_spear1340_suspend,
+	.plat_resume = miphy40lp_spear1340_resume,
+};
+
 static int miphy40lp_init(struct phy *phy)
 {
 	struct miphy40lp_priv *priv = phy_get_drvdata(phy);

-----Original Message-----
From: Kishon Vijay Abraham I [mailto:[email protected]]
Sent: Tuesday, February 11, 2014 5:06 PM
To: Mohit KUMAR DCG; [email protected]
Cc: Pratyush ANAND; Viresh Kumar; Tejun Heo; spear-devel; linux-arm- [email protected]; [email protected]
Subject: Re: [PATCH V6 06/12] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver

Hi,

Quoted 20 lines · Mohit Kumar

From: Pratyush Anand <[email protected]>

ahci driver needs some platform specific functions which are called at init, exit, suspend and resume conditions. Till now these functions were present in a platform driver with a fixme notes.

Similar functions modifying same set of registers will also be needed in case of PCIe phy init/exit.

So move all these SATA platform code to phy-miphy40lp driver.

Signed-off-by Pratyush Anand <[email protected]>

Tested-by Mohit Kumar <[email protected]>

Cc Arnd Bergmann <[email protected]>

Cc Viresh Kumar <[email protected]>

Cc Tejun Heo <[email protected]>

Cc Kishon Vijay Abraham I <[email protected]>

Cc [email protected]

Cc [email protected]

Cc [email protected]

Quoted 9 lines

---
 arch/arm/boot/dts/spear1310-evb.dts |    4 +
 arch/arm/boot/dts/spear1310.dtsi    |   39 +++++++++-
 arch/arm/boot/dts/spear1340-evb.dts |    4 +
 arch/arm/boot/dts/spear1340.dtsi    |   13 +++-
 arch/arm/boot/dts/spear13xx.dtsi    |    5 +
 arch/arm/mach-spear/Kconfig         |    2 +
 arch/arm/mach-spear/spear1340.c     |  127 +------------------------------
 drivers/phy/phy-miphy40lp.c         |  144

+++++++++++++++++++++++++++++++++++

Quoted 173 lines

 8 files changed, 208 insertions(+), 130 deletions(-)

arch/arm/boot/dts/spear1310-evb.dts +4 -0

index b56a801..d42c84b 100644
@@ -106,6 +106,10 @@
                    status = "okay";
            };
 
+           miphy@eb800000 {
+                   status = "okay";
+           };
+
            cf@b2800000 {
                    status = "okay";
            };

arch/arm/boot/dts/spear1310.dtsi +36 -3

index 122ae94..64e7dd5 100644
@@ -29,24 +29,57 @@
                    #gpio-cells = <2>;
            };
 
-           ahci@b1000000 {
+           miphy0: miphy@eb800000 {
+                   compatible = "st,miphy", "st,spear1310-miphy";
+                   reg = <0xeb800000 0x4000>;
+                   misc = <&misc>;
+                   phy-id = <0>;
+                   #phy-cells = <1>;
+                   status = "disabled";
+           };
+
+           miphy1: miphy@eb804000 {
+                   compatible = "st,miphy", "st,spear1310-miphy";
+                   reg = <0xeb804000 0x4000>;
+                   misc = <&misc>;
+                   phy-id = <1>;
+                   #phy-cells = <1>;
+                   status = "disabled";
+           };
+
+           miphy2: miphy@eb808000 {
+                   compatible = "st,miphy", "st,spear1310-miphy";
+                   reg = <0xeb808000 0x4000>;
+                   misc = <&misc>;
+                   phy-id = <2>;
+                   #phy-cells = <1>;
+                   status = "disabled";
+           };
+
+           ahci0: ahci@b1000000 {
                    compatible = "snps,spear-ahci";
                    reg = <0xb1000000 0x10000>;
                    interrupts = <0 68 0x4>;
+                   phys = <&miphy0 0>;
+                   phy-names = "sata-phy";
                    status = "disabled";
            };
 
-           ahci@b1800000 {
+           ahci1: ahci@b1800000 {
                    compatible = "snps,spear-ahci";
                    reg = <0xb1800000 0x10000>;
                    interrupts = <0 69 0x4>;
+                   phys = <&miphy1 0>;
+                   phy-names = "sata-phy";
                    status = "disabled";
            };
 
-           ahci@b4000000 {
+           ahci2: ahci@b4000000 {
                    compatible = "snps,spear-ahci";
                    reg = <0xb4000000 0x10000>;
                    interrupts = <0 70 0x4>;
+                   phys = <&miphy2 0>;
+                   phy-names = "sata-phy";
                    status = "disabled";
            };
 

arch/arm/boot/dts/spear1340-evb.dts +4 -0

index d6c30ae..b23e05e 100644
@@ -122,6 +122,10 @@
                    status = "okay";
            };
 
+           miphy@eb800000 {
+                   status = "okay";
+           };
+
            dma@ea800000 {
                    status = "okay";
            };

arch/arm/boot/dts/spear1340.dtsi +12 -1

index 54d128d..7e3a04b 100644
@@ -31,10 +31,21 @@
                    status = "disabled";
            };
 
-           ahci@b1000000 {
+           miphy0: miphy@eb800000 {
+                   compatible = "st,miphy", "st,spear1340-miphy";
+                   reg = <0xeb800000 0x4000>;
+                   misc = <&misc>;
+                   phy-id = <0>;
+                   #phy-cells = <1>;
+                   status = "disabled";
+           };
+
+           ahci0: ahci@b1000000 {
                    compatible = "snps,spear-ahci";
                    reg = <0xb1000000 0x10000>;
                    interrupts = <0 72 0x4>;
+                   phys = <&miphy0 0>;
+                   phy-names = "sata-phy";
                    status = "disabled";
            };
 

arch/arm/boot/dts/spear13xx.dtsi +5 -0

index 4382547..3a72508 100644
@@ -220,6 +220,11 @@
                              0xd8000000 0xd8000000 0x01000000
                              0xe0000000 0xe0000000 0x10000000>;
 
+                   misc: syscon@e0700000 {
+                           compatible = "st,spear1340-misc", "syscon";
+                           reg = <0xe0700000 0x1000>;
+                   };
+
                    gpio0: gpio@e0600000 {
                            compatible = "arm,pl061", "arm,primecell";
                            reg = <0xe0600000 0x1000>;

arch/arm/mach-spear/Kconfig +2 -0

index ac1710e..7e7f1b0 100644
@@ -26,6 +26,8 @@ config ARCH_SPEAR13XX
    select MIGHT_HAVE_CACHE_L2X0
    select PINCTRL
    select USE_OF
+   select MFD_SYSCON
+   select PHY_ST_MIPHY40LP
    help
      Supports for ARM's SPEAR13XX family
 

(quoted diff) +0 -0

b/arch/arm/mach-spear/spear1340.c index 3fb6834..8e27093 100644

arch/arm/mach-spear/spear1340.c +0 -5

@@ -11,138 +11,13 @@
  * warranty of any kind, whether express or implied.
  */
 
-#define pr_fmt(fmt) "SPEAr1340: " fmt
-
-#include <linux/ahci_platform.h>
-#include <linux/amba/serial.h>
-#include <linux/delay.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>

arch/arm/mach-spear/spear1340.c line 30

Quoted 10 lines

arch/arm/mach-spear/spear1340.c +0 -9

 #include "generic.h"
-#include <mach/spear.h>
-
-/* FIXME: Move SATA PHY code into a standalone driver */
-
-/* Base addresses */
-#define SPEAR1340_SATA_BASE                        UL(0xB1000000)
-
-/* Power Management Registers */
-#define SPEAR1340_PCM_CFG                  (VA_MISC_BASE +

0x100)

arch/arm/mach-spear/spear1340.c line 31

Quoted 1 line

arch/arm/mach-spear/spear1340.c +0 -1

-#define SPEAR1340_PCM_WKUP_CFG

      (VA_MISC_BASE + 0x104)

arch/arm/mach-spear/spear1340.c line 32

Quoted 1 line

arch/arm/mach-spear/spear1340.c +0 -1

-#define SPEAR1340_SWITCH_CTR                       (VA_MISC_BASE +

0x108)

arch/arm/mach-spear/spear1340.c line 34

Quoted 2 lines

arch/arm/mach-spear/spear1340.c +0 -2

-
-#define SPEAR1340_PERIP1_SW_RST

      (VA_MISC_BASE + 0x318)

arch/arm/mach-spear/spear1340.c line 35

Quoted 1 line

arch/arm/mach-spear/spear1340.c +0 -1

-#define SPEAR1340_PERIP2_SW_RST

      (VA_MISC_BASE + 0x31C)

arch/arm/mach-spear/spear1340.c line 36

Quoted 1 line

arch/arm/mach-spear/spear1340.c +0 -1

-#define SPEAR1340_PERIP3_SW_RST

      (VA_MISC_BASE + 0x320)

arch/arm/mach-spear/spear1340.c

Quoted 3 lines

arch/arm/mach-spear/spear1340.c +0 -3

-
-/* PCIE - SATA configuration registers */
-#define SPEAR1340_PCIE_SATA_CFG

      (VA_MISC_BASE + 0x424)

arch/arm/mach-spear/spear1340.c

Quoted 13 lines

arch/arm/mach-spear/spear1340.c +0 -13

-   /* PCIE CFG MASks */
-   #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT       (1 << 11)
-   #define SPEAR1340_PCIE_CFG_POWERUP_RESET        (1 << 10)
-   #define SPEAR1340_PCIE_CFG_CORE_CLK_EN          (1 << 9)
-   #define SPEAR1340_PCIE_CFG_AUX_CLK_EN           (1 << 8)
-   #define SPEAR1340_SATA_CFG_TX_CLK_EN            (1 << 4)
-   #define SPEAR1340_SATA_CFG_RX_CLK_EN            (1 << 3)
-   #define SPEAR1340_SATA_CFG_POWERUP_RESET        (1 << 2)
-   #define SPEAR1340_SATA_CFG_PM_CLK_EN            (1 << 1)
-   #define SPEAR1340_PCIE_SATA_SEL_PCIE            (0)
-   #define SPEAR1340_PCIE_SATA_SEL_SATA            (1)
-   #define SPEAR1340_SATA_PCIE_CFG_MASK            0xF1F
-   #define SPEAR1340_PCIE_CFG_VAL

      (SPEAR1340_PCIE_SATA_SEL_PCIE | \

arch/arm/mach-spear/spear1340.c

Quoted 5 lines

arch/arm/mach-spear/spear1340.c +0 -5

-                   SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
-                   SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
-                   SPEAR1340_PCIE_CFG_POWERUP_RESET | \
-                   SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
-   #define SPEAR1340_SATA_CFG_VAL

      (SPEAR1340_PCIE_SATA_SEL_SATA | \

arch/arm/mach-spear/spear1340.c

Quoted 6 lines

arch/arm/mach-spear/spear1340.c +0 -6

-                   SPEAR1340_SATA_CFG_PM_CLK_EN | \
-                   SPEAR1340_SATA_CFG_POWERUP_RESET | \
-                   SPEAR1340_SATA_CFG_RX_CLK_EN | \
-                   SPEAR1340_SATA_CFG_TX_CLK_EN)
-
-#define SPEAR1340_PCIE_MIPHY_CFG           (VA_MISC_BASE +

0x428)

arch/arm/mach-spear/spear1340.c

Quoted 10 lines

arch/arm/mach-spear/spear1340.c +0 -10

-   #define SPEAR1340_MIPHY_OSC_BYPASS_EXT          (1 << 31)
-   #define SPEAR1340_MIPHY_CLK_REF_DIV2            (1 << 27)
-   #define SPEAR1340_MIPHY_CLK_REF_DIV4            (2 << 27)
-   #define SPEAR1340_MIPHY_CLK_REF_DIV8            (3 << 27)
-   #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)        (x << 0)
-   #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
-                   (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
-                   SPEAR1340_MIPHY_CLK_REF_DIV2 | \
-                   SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
-   #define

SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \

arch/arm/mach-spear/spear1340.c line 92

Quoted 9 lines

arch/arm/mach-spear/spear1340.c +0 -9

-                   (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
-   #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
-                   (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
-                   SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
-
-/* SATA device registration */
-static int sata_miphy_init(struct device *dev, void __iomem *addr) -{
-   writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG);
-

      writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CL

K,

arch/arm/mach-spear/spear1340.c

Quoted 3 lines

arch/arm/mach-spear/spear1340.c +0 -3

-                   SPEAR1340_PCIE_MIPHY_CFG);
-   /* Switch on sata power domain */
-   writel((readl(SPEAR1340_PCM_CFG) | (0x800)),

SPEAR1340_PCM_CFG);

Quoted 9 lines

arch/arm/mach-spear/spear1340.c +0 -9

-   msleep(20);
-   /* Disable PCIE SATA Controller reset */
-   writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)),
-                   SPEAR1340_PERIP1_SW_RST);
-   msleep(20);
-
-   return 0;
-}
-

arch/arm/mach-spear/spear1340.c

Quoted 10 lines

arch/arm/mach-spear/spear1340.c +0 -10

-void sata_miphy_exit(struct device *dev) -{
-   writel(0, SPEAR1340_PCIE_SATA_CFG);
-   writel(0, SPEAR1340_PCIE_MIPHY_CFG);
-
-   /* Enable PCIE SATA Controller reset */
-   writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)),
-                   SPEAR1340_PERIP1_SW_RST);
-   msleep(20);
-   /* Switch off sata power domain */
-   writel((readl(SPEAR1340_PCM_CFG) & (~0x800)),

SPEAR1340_PCM_CFG);

Quoted 21 lines

arch/arm/mach-spear/spear1340.c +0 -21

-   msleep(20);
-}
-
-int sata_suspend(struct device *dev)
-{
-   if (dev->power.power_state.event == PM_EVENT_FREEZE)
-           return 0;
-
-   sata_miphy_exit(dev);
-
-   return 0;
-}
-
-int sata_resume(struct device *dev)
-{
-   if (dev->power.power_state.event == PM_EVENT_THAW)
-           return 0;
-
-   return sata_miphy_init(dev, NULL);
-}
-

arch/arm/mach-spear/spear1340.c

Quoted 10 lines

arch/arm/mach-spear/spear1340.c +0 -9

-static struct ahci_platform_data sata_pdata = {
-   .init = sata_miphy_init,
-   .exit = sata_miphy_exit,
-   .suspend = sata_suspend,
-   .resume = sata_resume,
-};
-
-/* Add SPEAr1340 auxdata to pass platform data */ -static struct
 of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
-   OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE,

NULL,

arch/arm/mach-spear/spear1340.c

Quoted 8 lines

arch/arm/mach-spear/spear1340.c +1 -5

-                   &sata_pdata),
-   {}
-};
 
 static void __init spear1340_dt_init(void)  {
-   of_platform_populate(NULL, of_default_bus_match_table,
-                   spear1340_auxdata_lookup, NULL);
+   of_platform_populate(NULL, of_default_bus_match_table, NULL,

NULL);

Quoted 19 lines

arch/arm/mach-spear/spear1340.c +0 -0

 }
 
 static const char * const spear1340_dt_board_compat[] = { diff --git

a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c index 98859ff..16da55b 100644

drivers/phy/phy-miphy40lp.c +2 -0

@@ -8,8 +8,10 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
+ * 04/02/2014: Adding support of SATA mode for SPEAr1340.
  */
 
+#include <linux/bitops.h>
 #include <linux/delay.h>
 #include <linux/dma-mapping.h>
 #include <linux/kernel.h>

drivers/phy/phy-miphy40lp.c line 27

Quoted 7 lines

drivers/phy/phy-miphy40lp.c +4 -0

@@ -19,6 +21,60 @@
 #include <linux/phy/phy.h>
 #include <linux/regmap.h>
 
+/* SPEAr1340 Registers */
+/* Power Management Registers */
+#define SPEAR1340_PCM_CFG                  0x100
+   #define SPEAR1340_PCM_CFG_SATA_POWER_EN

      BIT(11)

No tabs in the beginning. Just my personal preference though. No strong feelings.

Quoted 13 lines

drivers/phy/phy-miphy40lp.c +13 -0

+#define SPEAR1340_PCM_WKUP_CFG                     0x104
+#define SPEAR1340_SWITCH_CTR                       0x108
+
+#define SPEAR1340_PERIP1_SW_RST                    0x318
+   #define SPEAR1340_PERIP1_SW_RSATA               BIT(12)
+#define SPEAR1340_PERIP2_SW_RST                    0x31C
+#define SPEAR1340_PERIP3_SW_RST                    0x320
+
+/* PCIE - SATA configuration registers */
+#define SPEAR1340_PCIE_SATA_CFG                    0x424
+   /* PCIE CFG MASks */
+   #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT       BIT(11)
+   #define SPEAR1340_PCIE_CFG_POWERUP_RESET        BIT(10)

drivers/phy/phy-miphy40lp.c

Quoted 10 lines

drivers/phy/phy-miphy40lp.c +10 -0

+   #define SPEAR1340_PCIE_CFG_CORE_CLK_EN          BIT(9)
+   #define SPEAR1340_PCIE_CFG_AUX_CLK_EN           BIT(8)
+   #define SPEAR1340_SATA_CFG_TX_CLK_EN            BIT(4)
+   #define SPEAR1340_SATA_CFG_RX_CLK_EN            BIT(3)
+   #define SPEAR1340_SATA_CFG_POWERUP_RESET        BIT(2)
+   #define SPEAR1340_SATA_CFG_PM_CLK_EN            BIT(1)
+   #define SPEAR1340_PCIE_SATA_SEL_PCIE            (0)
+   #define SPEAR1340_PCIE_SATA_SEL_SATA            (1)
+   #define SPEAR1340_PCIE_SATA_CFG_MASK            0xF1F
+   #define SPEAR1340_PCIE_CFG_VAL

      (SPEAR1340_PCIE_SATA_SEL_PCIE | \

drivers/phy/phy-miphy40lp.c

Quoted 5 lines

drivers/phy/phy-miphy40lp.c +5 -0

+                   SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
+                   SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
+                   SPEAR1340_PCIE_CFG_POWERUP_RESET | \
+                   SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
+   #define SPEAR1340_SATA_CFG_VAL

      (SPEAR1340_PCIE_SATA_SEL_SATA | \

drivers/phy/phy-miphy40lp.c line 65

Quoted 10 lines

drivers/phy/phy-miphy40lp.c +10 -0

+                   SPEAR1340_SATA_CFG_PM_CLK_EN | \
+                   SPEAR1340_SATA_CFG_POWERUP_RESET | \
+                   SPEAR1340_SATA_CFG_RX_CLK_EN | \
+                   SPEAR1340_SATA_CFG_TX_CLK_EN)
+
+#define SPEAR1340_PCIE_MIPHY_CFG           0x428
+   #define SPEAR1340_MIPHY_OSC_BYPASS_EXT          BIT(31)
+   #define SPEAR1340_MIPHY_CLK_REF_DIV2            BIT(27)
+   #define SPEAR1340_MIPHY_CLK_REF_DIV4            (2 << 27)
+   #define SPEAR1340_MIPHY_CLK_REF_DIV8            (3 << 27)

This doesn't look very nice. But I'm not sure if there are similar macros to handle sequence of bits.

drivers/phy/phy-miphy40lp.c

Quoted 7 lines

drivers/phy/phy-miphy40lp.c +7 -0

+   #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)        (x << 0)
+   #define SPEAR1340_PCIE_MIPHY_CFG_MASK           0xF80000FF
+   #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
+                   (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+                   SPEAR1340_MIPHY_CLK_REF_DIV2 | \
+                   SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
+   #define

SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \

Quoted 9 lines

drivers/phy/phy-miphy40lp.c +5 -0

+                   (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
+   #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
+                   (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+                   SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
+
 enum phy_mode {
    SATA,
    PCIE,

drivers/phy/phy-miphy40lp.c struct miphy40lp_priv { · line 112

Quoted 7 lines

drivers/phy/phy-miphy40lp.c +4 -0

@@ -50,6 +106,93 @@ struct miphy40lp_priv {
    const struct miphy40lp_plat_ops *plat_ops;
 };
 
+static int miphy40lp_spear1340_sata_init(struct miphy40lp_priv *priv)
+{
+   regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+                   SPEAR1340_PCIE_SATA_CFG_MASK,

SPEAR1340_SATA_CFG_VAL);

drivers/phy/phy-miphy40lp.c struct miphy40lp_priv { · line 125

Quoted 3 lines

drivers/phy/phy-miphy40lp.c +3 -0

+   regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+                   SPEAR1340_PCIE_MIPHY_CFG_MASK,
+

      SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);

Quoted 67 lines

drivers/phy/phy-miphy40lp.c +67 -0

+   /* Switch on sata power domain */
+   regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
+                   SPEAR1340_PCM_CFG_SATA_POWER_EN,
+                   SPEAR1340_PCM_CFG_SATA_POWER_EN);
+   msleep(20);
+   /* Disable PCIE SATA Controller reset */
+   regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
+                   SPEAR1340_PERIP1_SW_RSATA, 0);
+   msleep(20);
+
+   return 0;
+}
+
+static int miphy40lp_spear1340_sata_exit(struct miphy40lp_priv *priv)
+{
+   regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+                   SPEAR1340_PCIE_SATA_CFG_MASK, 0);
+   regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+                   SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
+
+   /* Enable PCIE SATA Controller reset */
+   regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
+                   SPEAR1340_PERIP1_SW_RSATA,
+                   SPEAR1340_PERIP1_SW_RSATA);
+   msleep(20);
+   /* Switch off sata power domain */
+   regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
+                   SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
+   msleep(20);
+
+   return 0;
+}
+
+static int miphy40lp_spear1340_init(struct miphy40lp_priv *priv) {
+   int ret = 0;
+
+   if (priv->mode == SATA)
+           ret = miphy40lp_spear1340_sata_init(priv);
+
+   return ret;
+}
+
+static int miphy40lp_spear1340_exit(struct miphy40lp_priv *priv) {
+   int ret = 0;
+
+   if (priv->mode == SATA)
+           ret = miphy40lp_spear1340_sata_exit(priv);
+
+   return ret;
+}
+
+static int miphy40lp_spear1340_suspend(struct miphy40lp_priv *priv) {
+   int ret = 0;
+
+   if (priv->mode == SATA)
+           ret = miphy40lp_spear1340_sata_exit(priv);
+
+   return ret;
+}
+
+static int miphy40lp_spear1340_resume(struct miphy40lp_priv *priv) {
+   int ret = 0;
+
+   if (priv->mode == SATA)
+           ret = miphy40lp_spear1340_sata_init(priv);
+
+   return ret;

drivers/phy/phy-miphy40lp.c struct miphy40lp_priv {

Quoted 10 lines

drivers/phy/phy-miphy40lp.c +8 -0

+}
+
+static struct miphy40lp_plat_ops spear1340_phy_ops = {
+   .plat_init = miphy40lp_spear1340_init,
+   .plat_exit = miphy40lp_spear1340_exit,
+   .plat_suspend = miphy40lp_spear1340_suspend,
+   .plat_resume = miphy40lp_spear1340_resume, };
+
 static int miphy40lp_init(struct phy *phy)  {
    struct miphy40lp_priv *priv = phy_get_drvdata(phy); @@ -100,6

+243,7

drivers/phy/phy-miphy40lp.c static int miphy40lp_power_on(struct phy *phy) · line 245

Quoted 4 lines

drivers/phy/phy-miphy40lp.c +0 -0

 @@ static int miphy40lp_power_on(struct phy *phy)
 
 static const struct of_device_id miphy40lp_of_match[] = {
    { .compatible = "st,miphy40lp-phy", .data = NULL },

Do we still need this compatible? Because it doesn't do anything anyways?

Thanks
Kishon

From: Pratyush Anand <[email protected]>

SPEAr1310 and SPEAr1340 uses miphy40lp phy for PCIe. This driver adds support for the same.

Signed-off-by Pratyush Anand <[email protected]>

Tested-by Mohit Kumar <[email protected]>

Cc Arnd Bergmann <[email protected]>

Cc Viresh Kumar <[email protected]>

Cc Kishon Vijay Abraham I <[email protected]>

Cc spear-devel at list.st.com

Cc linux-arm-kernel at lists.infradead.org

Cc linux-kernel at vger.kernel.org

---
 drivers/phy/phy-miphy40lp.c |  165 +++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 165 insertions(+), 0 deletions(-)

drivers/phy/phy-miphy40lp.c +100 -0

index 16da55b..dec67ed 100644
@@ -9,6 +9,7 @@
  * published by the Free Software Foundation.
  *
  * 04/02/2014: Adding support of SATA mode for SPEAr1340.
+ * 04/02/2014: Adding support of PCIe mode for SPEAr1340 and SPEAr1310
  */
 
 #include <linux/bitops.h>

@@ -74,6 +75,80 @@
 	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
 			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
 			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
+/* SPEAr1310 Registers */
+#define SPEAR1310_PCIE_SATA_CFG			0x3A4
+	#define SPEAR1310_PCIE_SATA2_SEL_PCIE		(0 << 31)
+	#define SPEAR1310_PCIE_SATA1_SEL_PCIE		(0 << 30)
+	#define SPEAR1310_PCIE_SATA0_SEL_PCIE		(0 << 29)
+	#define SPEAR1310_PCIE_SATA2_SEL_SATA		BIT(31)
+	#define SPEAR1310_PCIE_SATA1_SEL_SATA		BIT(30)
+	#define SPEAR1310_PCIE_SATA0_SEL_SATA		BIT(29)
+	#define SPEAR1310_SATA2_CFG_TX_CLK_EN		BIT(27)
+	#define SPEAR1310_SATA2_CFG_RX_CLK_EN		BIT(26)
+	#define SPEAR1310_SATA2_CFG_POWERUP_RESET	BIT(25)
+	#define SPEAR1310_SATA2_CFG_PM_CLK_EN		BIT(24)
+	#define SPEAR1310_SATA1_CFG_TX_CLK_EN		BIT(23)
+	#define SPEAR1310_SATA1_CFG_RX_CLK_EN		BIT(22)
+	#define SPEAR1310_SATA1_CFG_POWERUP_RESET	BIT(21)
+	#define SPEAR1310_SATA1_CFG_PM_CLK_EN		BIT(20)
+	#define SPEAR1310_SATA0_CFG_TX_CLK_EN		BIT(19)
+	#define SPEAR1310_SATA0_CFG_RX_CLK_EN		BIT(18)
+	#define SPEAR1310_SATA0_CFG_POWERUP_RESET	BIT(17)
+	#define SPEAR1310_SATA0_CFG_PM_CLK_EN		BIT(16)
+	#define SPEAR1310_PCIE2_CFG_DEVICE_PRESENT	BIT(11)
+	#define SPEAR1310_PCIE2_CFG_POWERUP_RESET	BIT(10)
+	#define SPEAR1310_PCIE2_CFG_CORE_CLK_EN		BIT(9)
+	#define SPEAR1310_PCIE2_CFG_AUX_CLK_EN		BIT(8)
+	#define SPEAR1310_PCIE1_CFG_DEVICE_PRESENT	BIT(7)
+	#define SPEAR1310_PCIE1_CFG_POWERUP_RESET	BIT(6)
+	#define SPEAR1310_PCIE1_CFG_CORE_CLK_EN		BIT(5)
+	#define SPEAR1310_PCIE1_CFG_AUX_CLK_EN		BIT(4)
+	#define SPEAR1310_PCIE0_CFG_DEVICE_PRESENT	BIT(3)
+	#define SPEAR1310_PCIE0_CFG_POWERUP_RESET	BIT(2)
+	#define SPEAR1310_PCIE0_CFG_CORE_CLK_EN		BIT(1)
+	#define SPEAR1310_PCIE0_CFG_AUX_CLK_EN		BIT(0)
+
+	#define SPEAR1310_PCIE_CFG_MASK(x) ((0xF << (x * 4)) | BIT((x + 29)))
+	#define SPEAR1310_SATA_CFG_MASK(x) ((0xF << (x * 4 + 16)) | \
+			BIT((x + 29)))
+	#define SPEAR1310_PCIE_CFG_VAL(x) \
+			(SPEAR1310_PCIE_SATA##x##_SEL_PCIE | \
+			SPEAR1310_PCIE##x##_CFG_AUX_CLK_EN | \
+			SPEAR1310_PCIE##x##_CFG_CORE_CLK_EN | \
+			SPEAR1310_PCIE##x##_CFG_POWERUP_RESET | \
+			SPEAR1310_PCIE##x##_CFG_DEVICE_PRESENT)
+	#define SPEAR1310_SATA_CFG_VAL(x) \
+			(SPEAR1310_PCIE_SATA##x##_SEL_SATA | \
+			SPEAR1310_SATA##x##_CFG_PM_CLK_EN | \
+			SPEAR1310_SATA##x##_CFG_POWERUP_RESET | \
+			SPEAR1310_SATA##x##_CFG_RX_CLK_EN | \
+			SPEAR1310_SATA##x##_CFG_TX_CLK_EN)
+
+#define SPEAR1310_PCIE_MIPHY_CFG_1		0x3A8
+	#define SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT	BIT(31)
+	#define SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2	BIT(28)
+	#define SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(x)	(x << 16)
+	#define SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT	BIT(15)
+	#define SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2	BIT(12)
+	#define SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(x)	(x << 0)
+	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_MASK (0xFFFF)
+	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK (0xFFFF << 16)
+	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA \
+			(SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
+			SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 | \
+			SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(60) | \
+			SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
+			SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 | \
+			SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(60))
+	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+			(SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(120))
+	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE \
+			(SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
+			SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(25) | \
+			SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
+			SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(25))
+
+#define SPEAR1310_PCIE_MIPHY_CFG_2		0x3AC
 
 enum phy_mode {
 	SATA,

@@ -146,12 +221,35 @@ static int miphy40lp_spear1340_sata_exit(struct miphy40lp_priv *priv)
 	return 0;
 }
 
+static int miphy40lp_spear1340_pcie_init(struct miphy40lp_priv *priv)
+{
+	regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+			SPEAR1340_PCIE_MIPHY_CFG_MASK,
+			SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE);
+	regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+			SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_PCIE_CFG_VAL);
+
+	return 0;
+}
+
+static int miphy40lp_spear1340_pcie_exit(struct miphy40lp_priv *priv)
+{
+	regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+			SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
+	regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+			SPEAR1340_PCIE_SATA_CFG_MASK, 0);
+
+	return 0;
+}
+
 static int miphy40lp_spear1340_init(struct miphy40lp_priv *priv)
 {
 	int ret = 0;
 
 	if (priv->mode == SATA)
 		ret = miphy40lp_spear1340_sata_init(priv);
+	else if (priv->mode == PCIE)
+		ret = miphy40lp_spear1340_pcie_init(priv);
 
 	return ret;
 }

@@ -162,6 +260,8 @@ static int miphy40lp_spear1340_exit(struct miphy40lp_priv *priv)
 
 	if (priv->mode == SATA)
 		ret = miphy40lp_spear1340_sata_exit(priv);
+	else if (priv->mode == PCIE)
+		ret = miphy40lp_spear1340_pcie_exit(priv);
 
 	return ret;
 }

@@ -193,6 +293,70 @@ static struct miphy40lp_plat_ops spear1340_phy_ops = {
 	.plat_resume = miphy40lp_spear1340_resume,
 };

-----Original Message-----
From: Kishon Vijay Abraham I [mailto:kishon at ti.com]
Sent: Tuesday, February 11, 2014 5:36 PM
To: Mohit KUMAR DCG; arnd at arndb.de
Cc: Pratyush ANAND; Viresh Kumar; spear-devel; linux-arm- kernel at lists.infradead.org; linux-kernel at vger.kernel.org
Subject: Re: [PATCH V6 07/12] phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support

Quoted 4 lines · Mohit Kumar

From: Pratyush Anand <[email protected]>

SPEAr1310 and SPEAr1340 uses miphy40lp phy for PCIe. This driver adds support for the same.

What's up with SATA support for SPEAr1310? Do you have plans of adding it soon?

Quoted 1 line

drivers/phy/phy-miphy40lp.c static struct miphy40lp_plat_ops spear1340_phy_ops = { · line 304

Quoted 6 lines

drivers/phy/phy-miphy40lp.c +6 -0

+
+	regmap_update_bits(priv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
+			SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK,
+			SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE);
+
+	switch (priv->id) {

'id' should be made as optional dt property since it's not used for 1340 no?