nand/denali: Adding Denali NAND driver support

To add the Denali NAND driver support into U-Boot. It required information such as register base address from configuration header file within include/configs folder.

---
Changes for v7
- Adding Masahiro's code to support 64bit version controller
- Removed unused stub functions
- Enhanced the ECC calculation
Changes for v6
- Remove chip_delay as its unused
- Remove ECC bit assignment in nand_para functions Changes for v5
- Rename denali_nand to denali only
- Rename the macro for ctrl and data address Changes for v4
- Added cache flush to handle dcache enabled
- Used standard return where 0 for pass
- Removed unnecessary casting
- Used standard readl and writel
Changes for v3
- Fixed coding style
Changes for v2
- Enable this driver support for SOCFPGA

---
 drivers/mtd/nand/Makefile |    1 +
 drivers/mtd/nand/denali.c | 1122 +++++++++++++++++++++++++++++++++++++++++++++
 drivers/mtd/nand/denali.h |  490 ++++++++++++++++++++
 3 files changed, 1613 insertions(+)
 create mode 100644 drivers/mtd/nand/denali.c
 create mode 100644 drivers/mtd/nand/denali.h

index 02b149c..76ae105 100644
@@ -39,6 +39,7 @@ obj-$(CONFIG_NAND_ECC_BCH) += nand_bch.o
 obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
 obj-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
 obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
+obj-$(CONFIG_NAND_DENALI) += denali.o
 obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
 obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
 obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o

1.7.9.5

Hi Chin,

This version works on Panasonic SoCs and
looks good enough to be applied.
Thanks!

Best Regards
Masahiro Yamada

Hi Masahiro,

Great to hear that.
It was a fun experience to work with you to get this patch work for both 32bit and 64 bit controller.

Thanks
Chin Liang

Hi Chin, Scott,

I am evaluating the performance of this driver. Unfortunately it turned out this driver is very slow.

I have another driver for Denali NAND controller, which does not use DMA.

So I compared the read/write performance.

This is my benchmark

(1) Write 0x10000000 bytes from SDRAM to NAND.

This patch (with DMA): 68 sec
My implementation without DMA: 46sec

(2) Read 0x10000000 bytes from NAND to SDRAM

This patch(with DMA): 45sec
My implementaion without DMA: 22sec

This patch with DMA is slower than without DMA.

What is worse is scanning bad block marks is extremely slow. (Maybe abount 10x slower than without DMA)

So my question is, what should we do to improve the performance? Is it a bad idea to use DMA?

The sequence of page_read in this patch is like this:
(1) Cache flush of DMA buffer area
(2) DMA transfer from NAND device to DMA buffer
(3) memcpy() from DMA buffer to destination memory

In Linux Kernel, I guess there is DMA sync process between (2) and (3). But we don't have DMA API in U-Boot.

If we do not use DMA, the read sequence is like this
(1) Copy data directly from NAND register to destination memory

According to my benchmark, this is about twice faster.

Scott, do you have any advice?

Best Regards
Masahiro Yamada

flush_dcache_range() plays the same role as the Linux DMA sync.

Have you measured the performance in the Linux driver?

Do some profiling to see where the time is spent. I don't know how easy it is to do automated profiling of U-Boot, but you could add some manual instrumentation of the driver to measure min/avg/max/total time taken over various intervals.

-Scott

Hi Chin,

I found another fatal problem in v7. "nand markbad" command does not work at all. I think write_oob_data() is buggy.

And I made "nand bad" command much faster. And other misc feedbacks.

How about squashing
http://patchwork.ozlabs.org/patch/340277/
http://patchwork.ozlabs.org/patch/340278/
to v7 and posting v8.

Best Regards
Masahiro Yamada

Hi Masahiro,

I believe I already comment that on the previous mail. In short, its working for me as I am using the BBT within the flash.

Actually, its only happen when new chip is used. But this code improved the speed, its a nice enhancement to put into v8.

If you are ok with the comments, I can go ahead to create the v8 with below changes
1. Change denali.xx to denali->xx
2. Enhancement of nand bad bad block scanning function

Thanks
Chin Liang

Hi Chin,

As I commented in another reply,
I guess it is working for you on v2013.01 release. But I doubt it on the current u-boot/master.

I found another bug.
NAND_BBT_USE_FLASH and NAND_BBT_NO_OOB must be added to nand->bbt_options.

Please include this fix too in version 8.

@@ -1162,13 +1162,13 @@ static int denali_nand_init(struct nand_chip *nand)
/* check whether flash got BBT table (located at end of flash). As we
* use NAND_BBT_NO_OOB, the BBT page will start with
* bbt_pattern. We will have mirror pattern too */
- nand->options |= NAND_BBT_USE_FLASH;
+ nand->bbt_options |= NAND_BBT_USE_FLASH;
/*
* We are using main + spare with ECC support. As BBT need ECC support,
* we need to ensure BBT code don't write to OOB for the BBT pattern.
* All BBT info will be stored into data area with ECC support. */
- nand->options |= NAND_BBT_NO_OOB;
+ nand->bbt_options |= NAND_BBT_NO_OOB;
#endif

         nand->ecc.mode = NAND_ECC_HW;

Best Regards
Masahiro Yamada

Hi Chin,

Could you send v8?

Best Regards
Masahiro Yamada

Hi Chin,

Could you tell me the status of Denali NAND driver?

Please apply my feedback and post v8.
I really need this driver.

Thanks,

Best Regards
Masahiro Yamada

Hi Masahiro,

Sorry as I was busy on some issues recently.
Let me work out the v8 patch and send out within this few days. Thanks for reminding.

Chin Liang