PCI: Add SPEAr13xx PCie support
Subsystems (9)
v8 cover PCI: Add SPEAr13xx PCie support
Patch# 1 and 2: Improvement and fixes for SPEAr13xx support. Patch# 3,4 and 6: Add DT bindings for spear1310/40-miphy, misc and pcie node Patch# 5: Add spear1310/40-miphy driver and support for spear1310/40 miphy wrapper.
Patch# 7-9: Add SPEAr13xx PCIe driver and dt support.
These pathes are tested with linux-3.15 tag of arm-soc tree. Tested with SPEAr1310 evaluation board with:
- INTEL PRO 100/100 EP card
- USB xhci gen2 card
- Above cards connected through LeCROY PTC switch
Modifications for SATA are tested with SPEAr1340-evb board
Changes since v7:
- Rebase over for-linus-3.15 tag of arm-soc tree so that complete patch series can be applied cleanly.
- Incorporated few comments on comment style and superfluous comments Changes since v6:
- Split miphy driver for SPEAr1310 and SPEAr1340
- Some cleanup and incorporated other minor comments
Changes since v5:
- Split DT bindings for misc, miphy-40lp and pcie node into sepearte patches
- Merge config options PCIE_SPEAR13XX and PCI_MSI into defconfig patch
- Incorporated other minor comments
Changes since v4:
- Uses per device function pointers passed from .data field to the of_device_id instead of of_device_is_compatible.
- Incorporated other minor comments from v4
Changes since v3:
- Phy driver renamed to phy-miphy40lp
- ahci phy hook patch used as suggested by Arnd
- Incorporated other minor comments from v3
Changes since v2:
- Incorporated comments to move SPEAr13xx PCIe and SATA phy specific routines to the phy framework
- Modify ahci driver to include phy hooks
- phy-core driver modifications for subsys_initcall()
Changes since v1:
- Few patches of the series are already accepted and applied to mainline e.g. pcie designware driver improvements,fixes for IO translation bug, PCIe dw driver maintainer. So dropped these from v2.
- Incorporated comment to move the common/reset PCIe code to the seperate driver
- PCIe and SATA share common PHY configuration registers, so move SATA platform code to the system config driver
Fourth patch is improves pcie designware driver and fixes the IO translation bug. IO translation bug fix leads to the working of PCIe EP devices connected to RC through switch.
Mohit Kumar (1):
SPEAr13xx: defconfig: Update
Pratyush Anand (8):
clk: SPEAr13XX: Fix pcie clock name
SPEAr13XX: Fix static mapping table
phy: SPEAr1310/40-miphy: Add binding information
SPEAr: misc: Add binding information
phy: SPEAr1310/40-miphy: Add phy driver for PCIe and SATA
SPEAr13XX: Add binding information for PCIe controller
SPEAr13XX: dts: Add PCIe node information
pcie: SPEAr13xx: Add designware wrapper support
.../devicetree/bindings/arm/spear-misc.txt | 9 + .../devicetree/bindings/pci/spear13xx-pcie.txt | 14 + .../devicetree/bindings/phy/st-spear1310-miphy.txt | 12 + .../devicetree/bindings/phy/st-spear1340-miphy.txt | 11 + MAINTAINERS | 6 + arch/arm/boot/dts/spear1310-evb.dts | 4 + arch/arm/boot/dts/spear1310.dtsi | 93 +++++- arch/arm/boot/dts/spear1340-evb.dts | 4 + arch/arm/boot/dts/spear1340.dtsi | 30 ++- arch/arm/boot/dts/spear13xx.dtsi | 9 +- arch/arm/configs/spear13xx_defconfig | 16 + arch/arm/mach-spear/Kconfig | 4 + arch/arm/mach-spear/include/mach/spear.h | 4 +- arch/arm/mach-spear/spear1340.c | 127 +------ arch/arm/mach-spear/spear13xx.c | 2 +- drivers/clk/spear/spear1310_clock.c | 6 +- drivers/clk/spear/spear1340_clock.c | 2 +- drivers/pci/host/Kconfig | 8 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pcie-spear13xx.c | 407 ++++++++++++++++++++ drivers/phy/Kconfig | 12 + drivers/phy/Makefile | 2 + drivers/phy/phy-spear1310-miphy.c | 274 +++++++++++++ drivers/phy/phy-spear1340-miphy.c | 300 ++++++++++++++ 24 files changed, 1218 insertions(+), 139 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt create mode 100644 Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt create mode 100644 Documentation/devicetree/bindings/phy/st-spear1340-miphy.txt create mode 100644 drivers/pci/host/pcie-spear13xx.c create mode 100644 drivers/phy/phy-spear1310-miphy.c create mode 100644 drivers/phy/phy-spear1340-miphy.c
PATCH v8 1/9 clk: SPEAr13XX: Fix pcie clock name
From: Pratyush Anand <[email protected]>
Follow dt clock naming convention for PCIe clocks.
--- drivers/clk/spear/spear1310_clock.c | 6 +++--- drivers/clk/spear/spear1340_clock.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-)
drivers/clk/spear/spear1310_clock.c +3 -3
@@ -742,19 +742,19 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) clk =clk_register_gate (NULL ,"pcie_sata_0_clk" ,"ahb_clk" ,0 ,SPEAR1310_PERIP1_CLK_ENB ,SPEAR1310_PCIE_SATA_0_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie.0" ); +clk_register_clkdev (clk,NULL ,"b1000000.pcie" );clk_register_clkdev (clk,NULL ,"b1000000.ahci" ); clk =clk_register_gate (NULL ,"pcie_sata_1_clk" ,"ahb_clk" ,0 ,SPEAR1310_PERIP1_CLK_ENB ,SPEAR1310_PCIE_SATA_1_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie.1" ); +clk_register_clkdev (clk,NULL ,"b1800000.pcie" );clk_register_clkdev (clk,NULL ,"b1800000.ahci" ); clk =clk_register_gate (NULL ,"pcie_sata_2_clk" ,"ahb_clk" ,0 ,SPEAR1310_PERIP1_CLK_ENB ,SPEAR1310_PCIE_SATA_2_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie.2" ); +clk_register_clkdev (clk,NULL ,"b4000000.pcie" );clk_register_clkdev (clk,NULL ,"b4000000.ahci" ); clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
drivers/clk/spear/spear1340_clock.c +1 -1
@@ -839,7 +839,7 @@ void __init spear1340_clk_init(void __iomem *misc_base) clk =clk_register_gate (NULL ,"pcie_sata_clk" ,"ahb_clk" ,0 ,SPEAR1340_PERIP1_CLK_ENB ,SPEAR1340_PCIE_SATA_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie" ); +clk_register_clkdev (clk,NULL ,"b1000000.pcie" );clk_register_clkdev (clk,NULL ,"b1000000.ahci" ); clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
Signature · 1 line
1.7.0.1
PATCH v8 1/9 clk: SPEAr13XX: Fix pcie clock name
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
Follow dt clock naming convention for PCIe clocks.
--- drivers/clk/spear/spear1310_clock.c | 6 +++--- drivers/clk/spear/spear1340_clock.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-)
drivers/clk/spear/spear1310_clock.c +3 -3
@@ -742,19 +742,19 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) clk =clk_register_gate (NULL ,"pcie_sata_0_clk" ,"ahb_clk" ,0 ,SPEAR1310_PERIP1_CLK_ENB ,SPEAR1310_PCIE_SATA_0_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie.0" ); +clk_register_clkdev (clk,NULL ,"b1000000.pcie" );clk_register_clkdev (clk,NULL ,"b1000000.ahci" ); clk =clk_register_gate (NULL ,"pcie_sata_1_clk" ,"ahb_clk" ,0 ,SPEAR1310_PERIP1_CLK_ENB ,SPEAR1310_PCIE_SATA_1_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie.1" ); +clk_register_clkdev (clk,NULL ,"b1800000.pcie" );clk_register_clkdev (clk,NULL ,"b1800000.ahci" ); clk =clk_register_gate (NULL ,"pcie_sata_2_clk" ,"ahb_clk" ,0 ,SPEAR1310_PERIP1_CLK_ENB ,SPEAR1310_PCIE_SATA_2_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie.2" ); +clk_register_clkdev (clk,NULL ,"b4000000.pcie" );clk_register_clkdev (clk,NULL ,"b4000000.ahci" ); clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
drivers/clk/spear/spear1340_clock.c +1 -1
@@ -839,7 +839,7 @@ void __init spear1340_clk_init(void __iomem *misc_base) clk =clk_register_gate (NULL ,"pcie_sata_clk" ,"ahb_clk" ,0 ,SPEAR1340_PERIP1_CLK_ENB ,SPEAR1340_PCIE_SATA_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie" ); +clk_register_clkdev (clk,NULL ,"b1000000.pcie" );clk_register_clkdev (clk,NULL ,"b1000000.ahci" ); clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
Signature · 1 line
1.7.0.1
PATCH v8 1/9 clk: SPEAr13XX: Fix pcie clock name
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
Follow dt clock naming convention for PCIe clocks.
--- drivers/clk/spear/spear1310_clock.c | 6 +++--- drivers/clk/spear/spear1340_clock.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-)
drivers/clk/spear/spear1310_clock.c +3 -3
@@ -742,19 +742,19 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) clk =clk_register_gate (NULL ,"pcie_sata_0_clk" ,"ahb_clk" ,0 ,SPEAR1310_PERIP1_CLK_ENB ,SPEAR1310_PCIE_SATA_0_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie.0" ); +clk_register_clkdev (clk,NULL ,"b1000000.pcie" );clk_register_clkdev (clk,NULL ,"b1000000.ahci" ); clk =clk_register_gate (NULL ,"pcie_sata_1_clk" ,"ahb_clk" ,0 ,SPEAR1310_PERIP1_CLK_ENB ,SPEAR1310_PCIE_SATA_1_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie.1" ); +clk_register_clkdev (clk,NULL ,"b1800000.pcie" );clk_register_clkdev (clk,NULL ,"b1800000.ahci" ); clk =clk_register_gate (NULL ,"pcie_sata_2_clk" ,"ahb_clk" ,0 ,SPEAR1310_PERIP1_CLK_ENB ,SPEAR1310_PCIE_SATA_2_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie.2" ); +clk_register_clkdev (clk,NULL ,"b4000000.pcie" );clk_register_clkdev (clk,NULL ,"b4000000.ahci" ); clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
drivers/clk/spear/spear1340_clock.c +1 -1
@@ -839,7 +839,7 @@ void __init spear1340_clk_init(void __iomem *misc_base) clk =clk_register_gate (NULL ,"pcie_sata_clk" ,"ahb_clk" ,0 ,SPEAR1340_PERIP1_CLK_ENB ,SPEAR1340_PCIE_SATA_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie" ); +clk_register_clkdev (clk,NULL ,"b1000000.pcie" );clk_register_clkdev (clk,NULL ,"b1000000.ahci" ); clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
Signature · 1 line
1.7.0.1
PATCH v8 2/9 SPEAr13XX: Fix static mapping table
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
SPEAr13XX was using virtual address space 0xFE000000 to map physical address space 0xB3000000. pci_remap_io uses 0xFEE00000 as virtual address. So change 0xFE000000 to 0xF9000000.
--- arch/arm/mach-spear/include/mach/spear.h | 4 ++-- arch/arm/mach-spear/spear13xx.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-)
arch/arm/mach-spear/include/mach/spear.h +2 -2
@@ -52,10 +52,10 @@#ifdef CONFIG_ARCH_SPEAR13XX #define PERIP_GRP2_BASE UL(0xB3000000) -#define VA_PERIP_GRP2_BASE IOMEM(0xFE000000) +#define VA_PERIP_GRP2_BASE IOMEM(0xF9000000)#define MCIF_SDHCI_BASE UL(0xB3000000)#define SYSRAM0_BASE UL(0xB3800000) -#define VA_SYSRAM0_BASE IOMEM(0xFE800000) +#define VA_SYSRAM0_BASE IOMEM(0xF9800000)#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600)#define PERIP_GRP1_BASE UL(0xE0000000)
arch/arm/mach-spear/spear13xx.c +1 -1
@@ -52,7 +52,7 @@ void __init spear13xx_l2x0_init(void)/* * Following will create 16MB static virtual/physical mappings * PHYSICAL VIRTUAL -* 0xB3000000 0xFE000000 +* 0xB3000000 0xF9000000 * 0xE0000000 0xFD000000 * 0xEC000000 0xFC000000 * 0xED000000 0xFB000000
Signature · 1 line
1.7.0.1
PATCH v8 2/9 SPEAr13XX: Fix static mapping table
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
SPEAr13XX was using virtual address space 0xFE000000 to map physical address space 0xB3000000. pci_remap_io uses 0xFEE00000 as virtual address. So change 0xFE000000 to 0xF9000000.
--- arch/arm/mach-spear/include/mach/spear.h | 4 ++-- arch/arm/mach-spear/spear13xx.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-)
arch/arm/mach-spear/include/mach/spear.h +2 -2
@@ -52,10 +52,10 @@#ifdef CONFIG_ARCH_SPEAR13XX #define PERIP_GRP2_BASE UL(0xB3000000) -#define VA_PERIP_GRP2_BASE IOMEM(0xFE000000) +#define VA_PERIP_GRP2_BASE IOMEM(0xF9000000)#define MCIF_SDHCI_BASE UL(0xB3000000)#define SYSRAM0_BASE UL(0xB3800000) -#define VA_SYSRAM0_BASE IOMEM(0xFE800000) +#define VA_SYSRAM0_BASE IOMEM(0xF9800000)#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600)#define PERIP_GRP1_BASE UL(0xE0000000)
arch/arm/mach-spear/spear13xx.c +1 -1
@@ -52,7 +52,7 @@ void __init spear13xx_l2x0_init(void)/* * Following will create 16MB static virtual/physical mappings * PHYSICAL VIRTUAL -* 0xB3000000 0xFE000000 +* 0xB3000000 0xF9000000 * 0xE0000000 0xFD000000 * 0xEC000000 0xFC000000 * 0xED000000 0xFB000000
Signature · 1 line
1.7.0.1
PATCH v8 2/9 SPEAr13XX: Fix static mapping table
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
SPEAr13XX was using virtual address space 0xFE000000 to map physical address space 0xB3000000. pci_remap_io uses 0xFEE00000 as virtual address. So change 0xFE000000 to 0xF9000000.
--- arch/arm/mach-spear/include/mach/spear.h | 4 ++-- arch/arm/mach-spear/spear13xx.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-)
arch/arm/mach-spear/include/mach/spear.h +2 -2
@@ -52,10 +52,10 @@#ifdef CONFIG_ARCH_SPEAR13XX #define PERIP_GRP2_BASE UL(0xB3000000) -#define VA_PERIP_GRP2_BASE IOMEM(0xFE000000) +#define VA_PERIP_GRP2_BASE IOMEM(0xF9000000)#define MCIF_SDHCI_BASE UL(0xB3000000)#define SYSRAM0_BASE UL(0xB3800000) -#define VA_SYSRAM0_BASE IOMEM(0xFE800000) +#define VA_SYSRAM0_BASE IOMEM(0xF9800000)#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600)#define PERIP_GRP1_BASE UL(0xE0000000)
arch/arm/mach-spear/spear13xx.c +1 -1
@@ -52,7 +52,7 @@ void __init spear13xx_l2x0_init(void)/* * Following will create 16MB static virtual/physical mappings * PHYSICAL VIRTUAL -* 0xB3000000 0xFE000000 +* 0xB3000000 0xF9000000 * 0xE0000000 0xFD000000 * 0xEC000000 0xFC000000 * 0xED000000 0xFB000000
Signature · 1 line
1.7.0.1
PATCH v8 3/9 phy: SPEAr1310/40-miphy: Add binding information
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
SPEAr1310/40 uses miphy for PCIe, SATA. This patch adds documentation for the binding on the top of generic phy bindings.
--- .../devicetree/bindings/phy/st-spear1310-miphy.txt | 12 ++++++++++++ .../devicetree/bindings/phy/st-spear1340-miphy.txt | 11 +++++++++++ 2 files changed, 23 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt create mode 100644 Documentation/devicetree/bindings/phy/st-spear1340-miphy.txt
Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt new file +12 -0
@@ -0,0 +1,12 @@ +ST SPEAr1310-miphy DT detail +=================================== + +SPEAr1310-miphy is a phy controller supporting PCIe and SATA. + +Required properties: +- compatible : should be "st,spear1310-miphy" +- reg : offset and length of the PHY register set. +- misc: phandle for the syscon node to access misc registers +- phy-id: Instance id of the phy. +- #phy-cells : from the generic PHY bindings, must be 1. + - cell[1]: 0 if phy used for SATA, 1 for PCIe.
Documentation/devicetree/bindings/phy/st-spear1340-miphy.txt new file +11 -0
@@ -0,0 +1,11 @@ +ST SPEAr1340-miphy DT detail +=================================== + +SPEAr1340-miphy is a phy controller supporting PCIe and SATA. + +Required properties: +- compatible : should be "st,spear1340-miphy" +- reg : offset and length of the PHY register set. +- misc: phandle for the syscon node to access misc registers +- #phy-cells : from the generic PHY bindings, must be 1. + - cell[1]: 0 if phy used for SATA, 1 for PCIe.
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A message that is not in the archive (sent off-list or not yet received): 323b13ad6a87e6650c00f6e566818fa2ede7be95.1397555158.git.mohit.kumar-qxv4g6HH51o@public.gmane.org
Kishon Vijay Abraham I
Acked-byRe: [PATCH V8 3/9] phy: SPEAr1310/40-miphy: Add binding information
Quoted 5 lines · Mohit Kumar
From: Pratyush Anand <[email protected]>
SPEAr1310/40 uses miphy for PCIe, SATA. This patch adds documentation for the binding on the top of generic phy bindings.
Quoted 7 lines
Signed-off-by Pratyush Anand <[email protected]>Acked-by Arnd Bergmann <[email protected]>Cc Mohit Kumar <[email protected]>Cc Viresh Kumar <[email protected]>Cc Kishon Vijay Abraham I <[email protected]>
Quoted 33 lines
--- .../devicetree/bindings/phy/st-spear1310-miphy.txt | 12 ++++++++++++ .../devicetree/bindings/phy/st-spear1340-miphy.txt | 11 +++++++++++ 2 files changed, 23 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt create mode 100644 Documentation/devicetree/bindings/phy/st-spear1340-miphy.txtDocumentation/devicetree/bindings/phy/st-spear1310-miphy.txt new file +12
-0@@ -0,0 +1,12 @@ +ST SPEAr1310-miphy DT detail +=================================== + +SPEAr1310-miphy is a phy controller supporting PCIe and SATA. + +Required properties: +- compatible : should be "st,spear1310-miphy" +- reg : offset and length of the PHY register set. +- misc: phandle for the syscon node to access misc registers +- phy-id: Instance id of the phy. +- #phy-cells : from the generic PHY bindings, must be 1. + - cell[1]: 0 if phy used for SATA, 1 for PCIe.Documentation/devicetree/bindings/phy/st-spear1340-miphy.txt new file +1
-0@@ -0,0 +1,11 @@ +ST SPEAr1340-miphy DT detail
Documentation/devicetree/bindings/phy/st-spear1340-miphy.txt line 11
Quoted 10 lines
Documentation/devicetree/bindings/phy/st-spear1340-miphy.txt new file +10
-0+=================================== + +SPEAr1340-miphy is a phy controller supporting PCIe and SATA. + +Required properties: +- compatible : should be "st,spear1340-miphy" +- reg : offset and length of the PHY register set. +- misc: phandle for the syscon node to access misc registers +- #phy-cells : from the generic PHY bindings, must be 1. + - cell[1]: 0 if phy used for SATA, 1 for PCIe.
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PATCH v8 4/9 SPEAr: misc: Add binding information
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
SPEAr SOCs have some miscellaneous registers which are used to configure few properties of different peripheral controllers.
--- .../devicetree/bindings/arm/spear-misc.txt | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
Documentation/devicetree/bindings/arm/spear-misc.txt new file +9 -0
@@ -0,0 +1,9 @@ +SPEAr Misc configuration +=========================== +SPEAr SOCs have some miscellaneous registers which are used to configure +few properties of different peripheral controllers. + +misc node required properties: + +- compatible Should be "st,spear1340-misc", "syscon". +- reg: Address range of misc space upto 8K
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PATCH v8 5/9 phy: SPEAr1310/40-miphy: Add phy driver for PCIe and SATA
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
SPEAr1310/40 uses miphy for PCIe and SATA phy. This driver adds support for the same.
AHCI phy hookups from arch specific code has been cleaned up.
--- arch/arm/boot/dts/spear1310-evb.dts | 4 + arch/arm/boot/dts/spear1310.dtsi | 39 ++++- arch/arm/boot/dts/spear1340-evb.dts | 4 + arch/arm/boot/dts/spear1340.dtsi | 12 ++- arch/arm/boot/dts/spear13xx.dtsi | 5 + arch/arm/mach-spear/Kconfig | 3 + arch/arm/mach-spear/spear1340.c | 127 +--------------- drivers/phy/Kconfig | 12 ++ drivers/phy/Makefile | 2 + drivers/phy/phy-spear1310-miphy.c | 274 ++++++++++++++++++++++++++++++++ drivers/phy/phy-spear1340-miphy.c | 300 +++++++++++++++++++++++++++++++++++ 11 files changed, 652 insertions(+), 130 deletions(-) create mode 100644 drivers/phy/phy-spear1310-miphy.c create mode 100644 drivers/phy/phy-spear1340-miphy.c
arch/arm/boot/dts/spear1310-evb.dts +4 -0
@@ -106,6 +106,10 @@ status = "okay"; }; + miphy@eb800000 { + status = "okay"; + }; + cf@b2800000 { status = "okay"; };
arch/arm/boot/dts/spear1310.dtsi +36 -3
@@ -29,24 +29,57 @@ #gpio-cells = <2>; }; - ahci@b1000000 { + miphy0: miphy@eb800000 { + compatible = "st,miphy", "st,spear1310-miphy"; + reg = <0xeb800000 0x4000>; + misc = <&misc>; + phy-id = <0>; + #phy-cells = <1>; + status = "disabled"; + }; + + miphy1: miphy@eb804000 { + compatible = "st,miphy", "st,spear1310-miphy"; + reg = <0xeb804000 0x4000>; + misc = <&misc>; + phy-id = <1>; + #phy-cells = <1>; + status = "disabled"; + }; + + miphy2: miphy@eb808000 { + compatible = "st,miphy", "st,spear1310-miphy"; + reg = <0xeb808000 0x4000>; + misc = <&misc>; + phy-id = <2>; + #phy-cells = <1>; + status = "disabled"; + }; + + ahci0: ahci@b1000000 { compatible = "snps,spear-ahci"; reg = <0xb1000000 0x10000>; interrupts = <0 68 0x4>; + phys = <&miphy0 0>; + phy-names = "sata-phy"; status = "disabled"; }; - ahci@b1800000 { + ahci1: ahci@b1800000 { compatible = "snps,spear-ahci"; reg = <0xb1800000 0x10000>; interrupts = <0 69 0x4>; + phys = <&miphy1 0>; + phy-names = "sata-phy"; status = "disabled"; }; - ahci@b4000000 { + ahci2: ahci@b4000000 { compatible = "snps,spear-ahci"; reg = <0xb4000000 0x10000>; interrupts = <0 70 0x4>; + phys = <&miphy2 0>; + phy-names = "sata-phy"; status = "disabled"; };
arch/arm/boot/dts/spear1340-evb.dts +4 -0
@@ -122,6 +122,10 @@ status = "okay"; }; + miphy@eb800000 { + status = "okay"; + }; + dma@ea800000 { status = "okay"; };
arch/arm/boot/dts/spear1340.dtsi +11 -1
@@ -31,10 +31,20 @@ status = "disabled"; }; - ahci@b1000000 { + miphy0: miphy@eb800000 { + compatible = "st,miphy", "st,spear1340-miphy"; + reg = <0xeb800000 0x4000>; + misc = <&misc>; + #phy-cells = <1>; + status = "disabled"; + }; + + ahci0: ahci@b1000000 { compatible = "snps,spear-ahci"; reg = <0xb1000000 0x10000>; interrupts = <0 72 0x4>; + phys = <&miphy0 0>; + phy-names = "sata-phy"; status = "disabled"; };
arch/arm/boot/dts/spear13xx.dtsi +5 -0
@@ -220,6 +220,11 @@ 0xd8000000 0xd8000000 0x01000000 0xe0000000 0xe0000000 0x10000000>; + misc: syscon@e0700000 { + compatible = "st,spear1340-misc", "syscon"; + reg = <0xe0700000 0x1000>; + }; + gpio0: gpio@e0600000 { compatible = "arm,pl061", "arm,primecell"; reg = <0xe0600000 0x1000>;
arch/arm/mach-spear/Kconfig +3 -0
@@ -20,6 +20,7 @@ config ARCH_SPEAR13XX select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select PINCTRL + select MFD_SYSCON help Supports for ARM's SPEAR13XX family
@@ -28,12 +29,14 @@ if ARCH_SPEAR13XX config MACH_SPEAR1310 bool "SPEAr1310 Machine support with Device Tree" select PINCTRL_SPEAR1310 + select PHY_ST_SPEAR1310_MIPHY help Supports ST SPEAr1310 machine configured via the device-tree config MACH_SPEAR1340 bool "SPEAr1340 Machine support with Device Tree" select PINCTRL_SPEAR1340 + select PHY_ST_SPEAR1340_MIPHY help Supports ST SPEAr1340 machine configured via the device-tree
arch/arm/mach-spear/spear1340.c +1 -126
139 lines not on this page · raw message
drivers/phy/Kconfig +12 -0
@@ -166,4 +166,16 @@ config PHY_XGENE help This option enables support for APM X-Gene SoC multi-purpose PHY. +config PHY_ST_SPEAR1310_MIPHY + tristate "ST SPEAR1310-MIPHY driver" + select GENERIC_PHY + help + Support for ST SPEAr1310 MIPHY which can be used for PCIe and SATA. + +config PHY_ST_SPEAR1340_MIPHY + tristate "ST SPEAR1340-MIPHY driver" + select GENERIC_PHY + help + Support for ST SPEAr1340 MIPHY which can be used for PCIe and SATA. + endmenu
drivers/phy/Makefile +2 -0
@@ -18,3 +18,5 @@ obj-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o obj-$(CONFIG_PHY_EXYNOS4X12_USB2) += phy-exynos4x12-usb2.o obj-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o obj-$(CONFIG_PHY_XGENE) += phy-xgene.o +obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o +obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
drivers/phy/phy-spear1310-miphy.c new file +274 -0
274 lines not on this page · raw message
drivers/phy/phy-spear1340-miphy.c new file +300 -0
300 lines not on this page · raw message
Signature · 1 line
1.7.0.1
Re: [PATCH V8 5/9] phy: SPEAr1310/40-miphy: Add phy driver for PCIe and SATA
Quoted 7 lines · Mohit Kumar
From: Pratyush Anand <[email protected]>
SPEAr1310/40 uses miphy for PCIe and SATA phy. This driver adds support for the same.
AHCI phy hookups from arch specific code has been cleaned up.
Quoted 7 lines
Signed-off-by Pratyush Anand <[email protected]>Tested-by Mohit Kumar <[email protected]>Acked-by Arnd Bergmann <[email protected]>Cc Viresh Kumar <[email protected]>Cc Kishon Vijay Abraham I <[email protected]>
Quoted 942 lines
--- arch/arm/boot/dts/spear1310-evb.dts | 4 + arch/arm/boot/dts/spear1310.dtsi | 39 ++++- arch/arm/boot/dts/spear1340-evb.dts | 4 + arch/arm/boot/dts/spear1340.dtsi | 12 ++- arch/arm/boot/dts/spear13xx.dtsi | 5 + arch/arm/mach-spear/Kconfig | 3 + arch/arm/mach-spear/spear1340.c | 127 +--------------- drivers/phy/Kconfig | 12 ++ drivers/phy/Makefile | 2 + drivers/phy/phy-spear1310-miphy.c | 274 ++++++++++++++++++++++++++++++++ drivers/phy/phy-spear1340-miphy.c | 300 +++++++++++++++++++++++++++++++++++ 11 files changed, 652 insertions(+), 130 deletions(-) create mode 100644 drivers/phy/phy-spear1310-miphy.c create mode 100644 drivers/phy/phy-spear1340-miphy.carch/arm/boot/dts/spear1310-evb.dts +4
-0@@ -106,6 +106,10 @@ status = "okay"; }; + miphy@eb800000 { + status = "okay"; + }; + cf@b2800000 { status = "okay"; };arch/arm/boot/dts/spear1310.dtsi +36
-3@@ -29,24 +29,57 @@ #gpio-cells = <2>; }; - ahci@b1000000 { + miphy0: miphy@eb800000 { + compatible = "st,miphy", "st,spear1310-miphy"; + reg = <0xeb800000 0x4000>; + misc = <&misc>; + phy-id = <0>; + #phy-cells = <1>; + status = "disabled"; + }; + + miphy1: miphy@eb804000 { + compatible = "st,miphy", "st,spear1310-miphy"; + reg = <0xeb804000 0x4000>; + misc = <&misc>; + phy-id = <1>; + #phy-cells = <1>; + status = "disabled"; + }; + + miphy2: miphy@eb808000 { + compatible = "st,miphy", "st,spear1310-miphy"; + reg = <0xeb808000 0x4000>; + misc = <&misc>; + phy-id = <2>; + #phy-cells = <1>; + status = "disabled"; + }; + + ahci0: ahci@b1000000 { compatible = "snps,spear-ahci"; reg = <0xb1000000 0x10000>; interrupts = <0 68 0x4>; + phys = <&miphy0 0>; + phy-names = "sata-phy"; status = "disabled"; }; - ahci@b1800000 { + ahci1: ahci@b1800000 { compatible = "snps,spear-ahci"; reg = <0xb1800000 0x10000>; interrupts = <0 69 0x4>; + phys = <&miphy1 0>; + phy-names = "sata-phy"; status = "disabled"; }; - ahci@b4000000 { + ahci2: ahci@b4000000 { compatible = "snps,spear-ahci"; reg = <0xb4000000 0x10000>; interrupts = <0 70 0x4>; + phys = <&miphy2 0>; + phy-names = "sata-phy"; status = "disabled"; };arch/arm/boot/dts/spear1340-evb.dts +4
-0@@ -122,6 +122,10 @@ status = "okay"; }; + miphy@eb800000 { + status = "okay"; + }; + dma@ea800000 { status = "okay"; };arch/arm/boot/dts/spear1340.dtsi +11
-1@@ -31,10 +31,20 @@ status = "disabled"; }; - ahci@b1000000 { + miphy0: miphy@eb800000 { + compatible = "st,miphy", "st,spear1340-miphy"; + reg = <0xeb800000 0x4000>; + misc = <&misc>; + #phy-cells = <1>; + status = "disabled"; + }; + + ahci0: ahci@b1000000 { compatible = "snps,spear-ahci"; reg = <0xb1000000 0x10000>; interrupts = <0 72 0x4>; + phys = <&miphy0 0>; + phy-names = "sata-phy"; status = "disabled"; };arch/arm/boot/dts/spear13xx.dtsi +5
-0@@ -220,6 +220,11 @@ 0xd8000000 0xd8000000 0x01000000 0xe0000000 0xe0000000 0x10000000>; + misc: syscon@e0700000 { + compatible = "st,spear1340-misc", "syscon"; + reg = <0xe0700000 0x1000>; + }; + gpio0: gpio@e0600000 { compatible = "arm,pl061", "arm,primecell"; reg = <0xe0600000 0x1000>;arch/arm/mach-spear/Kconfig +3
-0@@ -20,6 +20,7 @@ config ARCH_SPEAR13XX select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select PINCTRL + select MFD_SYSCON help Supports for ARM's SPEAR13XX family@@ -28,12 +29,14 @@ if ARCH_SPEAR13XX config MACH_SPEAR1310 bool "SPEAr1310 Machine support with Device Tree" select PINCTRL_SPEAR1310 + select PHY_ST_SPEAR1310_MIPHY help Supports ST SPEAr1310 machine configured via the device-tree config MACH_SPEAR1340 bool "SPEAr1340 Machine support with Device Tree" select PINCTRL_SPEAR1340 + select PHY_ST_SPEAR1340_MIPHY help Supports ST SPEAr1340 machine configured via the device-treearch/arm/mach-spear/spear1340.c +1
-126@@ -11,138 +11,13 @@* warranty of any kind, whether express or implied. */ -#define pr_fmt (fmt) "SPEAr1340: " fmt - -#include <linux/ahci_platform.h> -#include <linux/amba/serial.h> -#include <linux/delay.h> #include <linux/of_platform.h> #include <asm/mach/arch.h> #include "generic.h" -#include <mach/spear.h> - -/* FIXME: Move SATA PHY code into a standalone driver */ - -/* Base addresses */ -#define SPEAR1340_SATA_BASE UL(0xB1000000) - -/* Power Management Registers */ -#define SPEAR1340_PCM_CFG (VA_MISC_BASE + 0x100) -#define SPEAR1340_PCM_WKUP_CFG (VA_MISC_BASE + 0x104) -#define SPEAR1340_SWITCH_CTR (VA_MISC_BASE + 0x108) - -#define SPEAR1340_PERIP1_SW_RST (VA_MISC_BASE + 0x318) -#define SPEAR1340_PERIP2_SW_RST (VA_MISC_BASE + 0x31C) -#define SPEAR1340_PERIP3_SW_RST (VA_MISC_BASE + 0x320) - -/* PCIE - SATA configuration registers */ -#define SPEAR1340_PCIE_SATA_CFG (VA_MISC_BASE + 0x424) -/* PCIE CFG MASks */ -#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11) -#define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10) -#define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9) -#define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8) -#define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4) -#define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3) -#define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2) -#define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1) -#define SPEAR1340_PCIE_SATA_SEL_PCIE (0) -#define SPEAR1340_PCIE_SATA_SEL_SATA (1) -#define SPEAR1340_SATA_PCIE_CFG_MASK 0xF1F -#define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \ - SPEAR1340_PCIE_CFG_AUX_CLK_EN | \ - SPEAR1340_PCIE_CFG_CORE_CLK_EN | \ - SPEAR1340_PCIE_CFG_POWERUP_RESET | \ - SPEAR1340_PCIE_CFG_DEVICE_PRESENT) -#define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \ - SPEAR1340_SATA_CFG_PM_CLK_EN | \ - SPEAR1340_SATA_CFG_POWERUP_RESET | \ - SPEAR1340_SATA_CFG_RX_CLK_EN | \ - SPEAR1340_SATA_CFG_TX_CLK_EN) - -#define SPEAR1340_PCIE_MIPHY_CFG (VA_MISC_BASE + 0x428) -#define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31) -#define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27) -#define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27) -#define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27) -#define SPEAR1340_MIPHY_PLL_RATIO_TOP (x) (x << 0) -#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \ - (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ - SPEAR1340_MIPHY_CLK_REF_DIV2 | \ - SPEAR1340_MIPHY_PLL_RATIO_TOP(60)) -#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \ - (SPEAR1340_MIPHY_PLL_RATIO_TOP(120)) -#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \ - (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ - SPEAR1340_MIPHY_PLL_RATIO_TOP(25)) - -/* SATA device registration */ -static int sata_miphy_init (struct device *dev,void __iomem *addr) -{ -writel (SPEAR1340_SATA_CFG_VAL ,SPEAR1340_PCIE_SATA_CFG ); -writel (SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK , -SPEAR1340_PCIE_MIPHY_CFG ); -/* Switch on sata power domain */ -writel ((readl (SPEAR1340_PCM_CFG ) | (0x800 )),SPEAR1340_PCM_CFG ); -msleep (20 ); -/* Disable PCIE SATA Controller reset */ -writel ((readl (SPEAR1340_PERIP1_SW_RST ) & (~0x1000 )), -SPEAR1340_PERIP1_SW_RST ); -msleep (20 ); - -return 0 ; -} - -void sata_miphy_exit (struct device *dev) -{ -writel (0 ,SPEAR1340_PCIE_SATA_CFG ); -writel (0 ,SPEAR1340_PCIE_MIPHY_CFG ); - -/* Enable PCIE SATA Controller reset */ -writel ((readl (SPEAR1340_PERIP1_SW_RST ) | (0x1000 )), -SPEAR1340_PERIP1_SW_RST ); -msleep (20 ); -/* Switch off sata power domain */ -writel ((readl (SPEAR1340_PCM_CFG ) & (~0x800 )),SPEAR1340_PCM_CFG ); -msleep (20 ); -} - -int sata_suspend (struct device *dev) -{ -if (dev->power.power_state.event ==PM_EVENT_FREEZE ) -return 0 ; - -sata_miphy_exit (dev); - -return 0 ; -} - -int sata_resume (struct device *dev) -{ -if (dev->power.power_state.event ==PM_EVENT_THAW ) -return 0 ; - -return sata_miphy_init (dev,NULL ); -} - -static struct ahci_platform_data sata_pdata = { - .init = sata_miphy_init, - .exit = sata_miphy_exit, - .suspend = sata_suspend, - .resume = sata_resume, -}; - -/* Add SPEAr1340 auxdata to pass platform data */ -static struct of_dev_auxdata spear1340_auxdata_lookup[]__initdata = { -OF_DEV_AUXDATA ("snps,spear-ahci" ,SPEAR1340_SATA_BASE ,NULL , - &sata_pdata), - {} -};static void __init spear1340_dt_init (void ) { -of_platform_populate (NULL , of_default_bus_match_table, - spear1340_auxdata_lookup,NULL ); +of_platform_populate (NULL , of_default_bus_match_table,NULL ,NULL );platform_device_register_simple ("spear-cpufreq" ,-1 ,NULL ,0 ); }drivers/phy/Kconfig +12
-0@@ -166,4 +166,16 @@ config PHY_XGENE help This option enables support for APM X-Gene SoC multi-purpose PHY. +config PHY_ST_SPEAR1310_MIPHY + tristate "ST SPEAR1310-MIPHY driver" + select GENERIC_PHY + help + Support for ST SPEAr1310 MIPHY which can be used for PCIe and SATA. + +config PHY_ST_SPEAR1340_MIPHY + tristate "ST SPEAR1340-MIPHY driver" + select GENERIC_PHY + help + Support for ST SPEAr1340 MIPHY which can be used for PCIe and SATA. + endmenudrivers/phy/Makefile +2
-0@@ -18,3 +18,5 @@ obj-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o obj-$(CONFIG_PHY_EXYNOS4X12_USB2) += phy-exynos4x12-usb2.o obj-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o obj-$(CONFIG_PHY_XGENE) += phy-xgene.o +obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o +obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.odrivers/phy/phy-spear1310-miphy.c new file +274
-0@@ -0,0 +1,274 @@ +/* +* ST SPEAr1310-miphy driver +* +* Copyright (C) 2014 ST Microelectronics +* Pratyush Anand <[email protected]> +* Mohit Kumar <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +*/ + +#include <linux/bitops.h> +#include <linux/delay.h> +#include <linux/dma-mapping.h> +#include <linux/kernel.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/phy/phy.h> +#include <linux/regmap.h> + +/* SPEAr1310 Registers */ +#define SPEAR1310_PCIE_SATA_CFG 0x3A4 +#define SPEAR1310_PCIE_SATA2_SEL_PCIE (0 << 31) +#define SPEAR1310_PCIE_SATA1_SEL_PCIE (0 << 30) +#define SPEAR1310_PCIE_SATA0_SEL_PCIE (0 << 29) +#define SPEAR1310_PCIE_SATA2_SEL_SATA BIT(31) +#define SPEAR1310_PCIE_SATA1_SEL_SATA BIT(30) +#define SPEAR1310_PCIE_SATA0_SEL_SATA BIT(29) +#define SPEAR1310_SATA2_CFG_TX_CLK_EN BIT(27) +#define SPEAR1310_SATA2_CFG_RX_CLK_EN BIT(26) +#define SPEAR1310_SATA2_CFG_POWERUP_RESET BIT(25) +#define SPEAR1310_SATA2_CFG_PM_CLK_EN BIT(24) +#define SPEAR1310_SATA1_CFG_TX_CLK_EN BIT(23) +#define SPEAR1310_SATA1_CFG_RX_CLK_EN BIT(22) +#define SPEAR1310_SATA1_CFG_POWERUP_RESET BIT(21) +#define SPEAR1310_SATA1_CFG_PM_CLK_EN BIT(20) +#define SPEAR1310_SATA0_CFG_TX_CLK_EN BIT(19) +#define SPEAR1310_SATA0_CFG_RX_CLK_EN BIT(18) +#define SPEAR1310_SATA0_CFG_POWERUP_RESET BIT(17) +#define SPEAR1310_SATA0_CFG_PM_CLK_EN BIT(16) +#define SPEAR1310_PCIE2_CFG_DEVICE_PRESENT BIT(11) +#define SPEAR1310_PCIE2_CFG_POWERUP_RESET BIT(10) +#define SPEAR1310_PCIE2_CFG_CORE_CLK_EN BIT(9) +#define SPEAR1310_PCIE2_CFG_AUX_CLK_EN BIT(8) +#define SPEAR1310_PCIE1_CFG_DEVICE_PRESENT BIT(7) +#define SPEAR1310_PCIE1_CFG_POWERUP_RESET BIT(6) +#define SPEAR1310_PCIE1_CFG_CORE_CLK_EN BIT(5) +#define SPEAR1310_PCIE1_CFG_AUX_CLK_EN BIT(4) +#define SPEAR1310_PCIE0_CFG_DEVICE_PRESENT BIT(3) +#define SPEAR1310_PCIE0_CFG_POWERUP_RESET BIT(2) +#define SPEAR1310_PCIE0_CFG_CORE_CLK_EN BIT(1) +#define SPEAR1310_PCIE0_CFG_AUX_CLK_EN BIT(0) + +#define SPEAR1310_PCIE_CFG_MASK (x) ((0xF << (x * 4)) | BIT((x + 29))) +#define SPEAR1310_SATA_CFG_MASK (x) ((0xF << (x * 4 + 16)) | \ + BIT((x + 29))) +#define SPEAR1310_PCIE_CFG_VAL (x) \ + (SPEAR1310_PCIE_SATA##x##_SEL_PCIE | \ + SPEAR1310_PCIE##x##_CFG_AUX_CLK_EN | \ + SPEAR1310_PCIE##x##_CFG_CORE_CLK_EN | \ + SPEAR1310_PCIE##x##_CFG_POWERUP_RESET | \ + SPEAR1310_PCIE##x##_CFG_DEVICE_PRESENT) +#define SPEAR1310_SATA_CFG_VAL (x) \ + (SPEAR1310_PCIE_SATA##x##_SEL_SATA | \ + SPEAR1310_SATA##x##_CFG_PM_CLK_EN | \ + SPEAR1310_SATA##x##_CFG_POWERUP_RESET | \ + SPEAR1310_SATA##x##_CFG_RX_CLK_EN | \ + SPEAR1310_SATA##x##_CFG_TX_CLK_EN) + +#define SPEAR1310_PCIE_MIPHY_CFG_1 0x3A8 +#define SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT BIT(31) +#define SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 BIT(28) +#define SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP (x) (x << 16) +#define SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT BIT(15) +#define SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 BIT(12) +#define SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP (x) (x << 0) +#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_MASK (0xFFFF) +#define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK (0xFFFF << 16) +#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA \ + (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \ + SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 | \ + SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(60) | \ + SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \ + SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 | \ + SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(60)) +#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \ + (SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(120)) +#define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE \ + (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \ + SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(25) | \ + SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \ + SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(25)) + +#define SPEAR1310_PCIE_MIPHY_CFG_2 0x3AC + +enum spear1310_miphy_mode { +SATA , +PCIE , +}; + +struct spear1310_miphy_priv { +/* instance id of this phy */ +u32 id; +/* phy mode: 0 for SATA 1 for PCIe */ +enum spear1310_miphy_mode mode; +/* regmap for any soc specific misc registers */ +struct regmap *misc; +/* phy struct pointer */ +struct phy *phy; +}; + +static int spear1310_miphy_pcie_init (struct spear1310_miphy_priv *priv) +{ +u32 val; + +regmap_update_bits (priv->misc,SPEAR1310_PCIE_MIPHY_CFG_1 , +SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK , +SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE ); + +switch (priv->id) { +case 0 : + val =SPEAR1310_PCIE_CFG_VAL (0 ); +break ; +case 1 : + val =SPEAR1310_PCIE_CFG_VAL (1 ); +break ; +case 2 : + val =SPEAR1310_PCIE_CFG_VAL (2 ); +break ; +default : +return -EINVAL ; + } + +regmap_update_bits (priv->misc,SPEAR1310_PCIE_SATA_CFG , +SPEAR1310_PCIE_CFG_MASK (priv->id), val); + +return 0 ; +} + +static int spear1310_miphy_pcie_exit (struct spear1310_miphy_priv *priv) +{ +regmap_update_bits (priv->misc,SPEAR1310_PCIE_SATA_CFG , +SPEAR1310_PCIE_CFG_MASK (priv->id),0 ); + +regmap_update_bits (priv->misc,SPEAR1310_PCIE_MIPHY_CFG_1 , +SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK ,0 ); + +return 0 ; +} + +static int spear1310_miphy_init (struct phy *phy) +{ +struct spear1310_miphy_priv *priv =phy_get_drvdata (phy); +int ret =0 ; + +if (priv->mode ==PCIE ) + ret =spear1310_miphy_pcie_init (priv); + +return ret; +} + +static int spear1310_miphy_exit (struct phy *phy) +{ +struct spear1310_miphy_priv *priv =phy_get_drvdata (phy); +int ret =0 ; + +if (priv->mode ==PCIE ) + ret =spear1310_miphy_pcie_exit (priv); + +return ret; +} + +static const struct of_device_id spear1310_miphy_of_match[] = { + { .compatible ="st,spear1310-miphy" }, + { }, +}; +MODULE_DEVICE_TABLE (of, spear1310_miphy_of_match); + +static struct phy_ops spear1310_miphy_ops = { + .init = spear1310_miphy_init, + .exit = spear1310_miphy_exit, + .owner =THIS_MODULE , +}; + +static struct phy *spear1310_miphy_xlate (struct device *dev, +struct of_phandle_args *args) +{ +struct spear1310_miphy_priv *priv =dev_get_drvdata (dev); + +if (args->args_count <1 ) { +dev_err (dev,"DT did not pass correct no of args\n" ); +return NULL ; + } + + priv->mode = args->args[0 ]; + +if (priv->mode !=SATA && priv->mode !=PCIE ) { +dev_err (dev,"DT did not pass correct phy mode\n" ); +return NULL ; + } + +return priv->phy; +} + +static int __init spear1310_miphy_probe (struct platform_device *pdev) +{ +struct device *dev = &pdev->dev; +struct spear1310_miphy_priv *priv; +struct phy_provider *phy_provider; + + priv =devm_kzalloc (dev,sizeof (*priv),GFP_KERNEL ); +if (!priv) { +dev_err (dev,"can't alloc spear1310_miphy private date memory\n" ); +return -ENOMEM ; + } + + priv->misc = +syscon_regmap_lookup_by_phandle (dev->of_node,"misc" ); +if (IS_ERR (priv->misc)) { +dev_err (dev,"failed to find misc regmap\n" ); +return PTR_ERR (priv->misc); + } + +if (of_property_read_u32 (dev->of_node,"phy-id" , &priv->id)) { +dev_err (dev,"failed to find phy id\n" ); +return -EINVAL ; + } + + priv->phy =devm_phy_create (dev, &spear1310_miphy_ops,NULL ); +if (IS_ERR (priv->phy)) { +dev_err (dev,"failed to create SATA PCIe PHY\n" ); +return PTR_ERR (priv->phy); + } + +dev_set_drvdata (dev, priv); +phy_set_drvdata (priv->phy, priv); + + phy_provider = +devm_of_phy_provider_register (dev, spear1310_miphy_xlate); +if (IS_ERR (phy_provider)) { +dev_err (dev,"failed to register phy provider\n" ); +return PTR_ERR (phy_provider); + } + +return 0 ; +} + +static struct platform_driver spear1310_miphy_driver = { + .probe = spear1310_miphy_probe, + .driver = { + .name ="spear1310-miphy" , + .owner =THIS_MODULE , + .of_match_table =of_match_ptr (spear1310_miphy_of_match), + }, +}; + +static int __init spear1310_miphy_phy_init (void ) +{ +return platform_driver_register (&spear1310_miphy_driver); +} +module_init (spear1310_miphy_phy_init); + +static void __exit spear1310_miphy_phy_exit(void) +{ +platform_driver_unregister (&spear1310_miphy_driver); +} +module_exit (spear1310_miphy_phy_exit); + +MODULE_DESCRIPTION ("ST SPEAR1310-MIPHY driver" ); +MODULE_AUTHOR ("Pratyush Anand <[email protected]>" ); +MODULE_LICENSE ("GPL v2" );drivers/phy/phy-spear1340-miphy.c new file +300
-0@@ -0,0 +1,300 @@ +/* +* ST spear1340-miphy driver +* +* Copyright (C) 2014 ST Microelectronics +* Pratyush Anand <[email protected]> +* Mohit Kumar <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +*/ + +#include <linux/bitops.h> +#include <linux/delay.h> +#include <linux/dma-mapping.h> +#include <linux/kernel.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/phy/phy.h> +#include <linux/regmap.h> + +/* SPEAr1340 Registers */ +/* Power Management Registers */ +#define SPEAR1340_PCM_CFG 0x100 +#define SPEAR1340_PCM_CFG_SATA_POWER_EN BIT(11) +#define SPEAR1340_PCM_WKUP_CFG 0x104 +#define SPEAR1340_SWITCH_CTR 0x108 + +#define SPEAR1340_PERIP1_SW_RST 0x318 +#define SPEAR1340_PERIP1_SW_RSATA BIT(12) +#define SPEAR1340_PERIP2_SW_RST 0x31C +#define SPEAR1340_PERIP3_SW_RST 0x320 + +/* PCIE - SATA configuration registers */ +#define SPEAR1340_PCIE_SATA_CFG 0x424 +/* PCIE CFG MASks */ +#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT BIT(11) +#define SPEAR1340_PCIE_CFG_POWERUP_RESET BIT(10) +#define SPEAR1340_PCIE_CFG_CORE_CLK_EN BIT(9) +#define SPEAR1340_PCIE_CFG_AUX_CLK_EN BIT(8) +#define SPEAR1340_SATA_CFG_TX_CLK_EN BIT(4) +#define SPEAR1340_SATA_CFG_RX_CLK_EN BIT(3) +#define SPEAR1340_SATA_CFG_POWERUP_RESET BIT(2) +#define SPEAR1340_SATA_CFG_PM_CLK_EN BIT(1) +#define SPEAR1340_PCIE_SATA_SEL_PCIE (0) +#define SPEAR1340_PCIE_SATA_SEL_SATA (1) +#define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F +#define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \ + SPEAR1340_PCIE_CFG_AUX_CLK_EN | \ + SPEAR1340_PCIE_CFG_CORE_CLK_EN | \ + SPEAR1340_PCIE_CFG_POWERUP_RESET | \ + SPEAR1340_PCIE_CFG_DEVICE_PRESENT) +#define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \ + SPEAR1340_SATA_CFG_PM_CLK_EN | \ + SPEAR1340_SATA_CFG_POWERUP_RESET | \ + SPEAR1340_SATA_CFG_RX_CLK_EN | \ + SPEAR1340_SATA_CFG_TX_CLK_EN) + +#define SPEAR1340_PCIE_MIPHY_CFG 0x428 +#define SPEAR1340_MIPHY_OSC_BYPASS_EXT BIT(31) +#define SPEAR1340_MIPHY_CLK_REF_DIV2 BIT(27) +#define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27) +#define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27) +#define SPEAR1340_MIPHY_PLL_RATIO_TOP (x) (x << 0) +#define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF +#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \ + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ + SPEAR1340_MIPHY_CLK_REF_DIV2 | \ + SPEAR1340_MIPHY_PLL_RATIO_TOP(60)) +#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \ + (SPEAR1340_MIPHY_PLL_RATIO_TOP(120)) +#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \ + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ + SPEAR1340_MIPHY_PLL_RATIO_TOP(25)) + +enum spear1340_miphy_mode { +SATA , +PCIE , +}; + +struct spear1340_miphy_priv { +/* phy mode: 0 for SATA 1 for PCIe */ +enum spear1340_miphy_mode mode; +/* regmap for any soc specific misc registers */ +struct regmap *misc; +/* phy struct pointer */ +struct phy *phy; +}; + +static int spear1340_miphy_sata_init (struct spear1340_miphy_priv *priv) +{ +regmap_update_bits (priv->misc,SPEAR1340_PCIE_SATA_CFG , +SPEAR1340_PCIE_SATA_CFG_MASK ,SPEAR1340_SATA_CFG_VAL ); +regmap_update_bits (priv->misc,SPEAR1340_PCIE_MIPHY_CFG , +SPEAR1340_PCIE_MIPHY_CFG_MASK , +SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK ); +/* Switch on sata power domain */ +regmap_update_bits (priv->misc,SPEAR1340_PCM_CFG , +SPEAR1340_PCM_CFG_SATA_POWER_EN , +SPEAR1340_PCM_CFG_SATA_POWER_EN ); +msleep (20 ); +/* Disable PCIE SATA Controller reset */ +regmap_update_bits (priv->misc,SPEAR1340_PERIP1_SW_RST , +SPEAR1340_PERIP1_SW_RSATA ,0 ); +msleep (20 ); + +return 0 ; +} + +static int spear1340_miphy_sata_exit (struct spear1340_miphy_priv *priv) +{ +regmap_update_bits (priv->misc,SPEAR1340_PCIE_SATA_CFG , +SPEAR1340_PCIE_SATA_CFG_MASK ,0 ); +regmap_update_bits (priv->misc,SPEAR1340_PCIE_MIPHY_CFG , +SPEAR1340_PCIE_MIPHY_CFG_MASK ,0 ); + +/* Enable PCIE SATA Controller reset */ +regmap_update_bits (priv->misc,SPEAR1340_PERIP1_SW_RST , +SPEAR1340_PERIP1_SW_RSATA , +SPEAR1340_PERIP1_SW_RSATA ); +msleep (20 ); +/* Switch off sata power domain */ +regmap_update_bits (priv->misc,SPEAR1340_PCM_CFG , +SPEAR1340_PCM_CFG_SATA_POWER_EN ,0 ); +msleep (20 ); + +return 0 ; +} + +static int spear1340_miphy_pcie_init (struct spear1340_miphy_priv *priv) +{ +regmap_update_bits (priv->misc,SPEAR1340_PCIE_MIPHY_CFG , +SPEAR1340_PCIE_MIPHY_CFG_MASK , +SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE ); +regmap_update_bits (priv->misc,SPEAR1340_PCIE_SATA_CFG , +SPEAR1340_PCIE_SATA_CFG_MASK ,SPEAR1340_PCIE_CFG_VAL ); + +return 0 ; +} + +static int spear1340_miphy_pcie_exit (struct spear1340_miphy_priv *priv) +{ +regmap_update_bits (priv->misc,SPEAR1340_PCIE_MIPHY_CFG , +SPEAR1340_PCIE_MIPHY_CFG_MASK ,0 ); +regmap_update_bits (priv->misc,SPEAR1340_PCIE_SATA_CFG , +SPEAR1340_PCIE_SATA_CFG_MASK ,0 ); + +return 0 ; +} + +static int spear1340_miphy_init (struct phy *phy) +{ +struct spear1340_miphy_priv *priv =phy_get_drvdata (phy); +int ret =0 ; + +if (priv->mode ==SATA ) + ret =spear1340_miphy_sata_init (priv); +else if (priv->mode ==PCIE ) + ret =spear1340_miphy_pcie_init (priv); + +return ret; +} + +static int spear1340_miphy_exit (struct phy *phy) +{ +struct spear1340_miphy_priv *priv =phy_get_drvdata (phy); +int ret =0 ; + +if (priv->mode ==SATA ) + ret =spear1340_miphy_sata_exit (priv); +else if (priv->mode ==PCIE ) + ret =spear1340_miphy_pcie_exit (priv); + +return ret; +} + +static const struct of_device_id spear1340_miphy_of_match[] = { + { .compatible ="st,spear1340-miphy" }, + { }, +}; +MODULE_DEVICE_TABLE (of, spear1340_miphy_of_match); + +static struct phy_ops spear1340_miphy_ops = { + .init = spear1340_miphy_init, + .exit = spear1340_miphy_exit, + .owner =THIS_MODULE , +}; + +#ifdef CONFIG_PM_SLEEP +static int spear1340_miphy_suspend (struct device *dev) +{ +struct spear1340_miphy_priv *priv =dev_get_drvdata (dev); +int ret =0 ; + +if (priv->mode ==SATA ) + ret =spear1340_miphy_sata_exit (priv); + +return ret; +} + +static int spear1340_miphy_resume (struct device *dev) +{ +struct spear1340_miphy_priv *priv =dev_get_drvdata (dev); +int ret =0 ; + +if (priv->mode ==SATA ) + ret =spear1340_miphy_sata_init (priv); + +return ret; +} +#endif + +static SIMPLE_DEV_PM_OPS(spear1340_miphy_pm_ops, spear1340_miphy_suspend, + spear1340_miphy_resume); + +static struct phy *spear1340_miphy_xlate (struct device *dev, +struct of_phandle_args *args) +{ +struct spear1340_miphy_priv *priv =dev_get_drvdata (dev); + +if (args->args_count <1 ) { +dev_err (dev,"DT did not pass correct no of args\n" ); +return NULL ; + } + + priv->mode = args->args[0 ]; + +if (priv->mode !=SATA && priv->mode !=PCIE ) { +dev_err (dev,"DT did not pass correct phy mode\n" ); +return NULL ; + } + +return priv->phy; +} + +static int __init spear1340_miphy_probe (struct platform_device *pdev) +{ +struct device *dev = &pdev->dev; +struct spear1340_miphy_priv *priv; +struct phy_provider *phy_provider; + + priv =devm_kzalloc (dev,sizeof (*priv),GFP_KERNEL ); +if (!priv) { +dev_err (dev,"can't alloc spear1340_miphy private date memory\n" ); +return -ENOMEM ; + } + + priv->misc = +syscon_regmap_lookup_by_phandle (dev->of_node,"misc" ); +if (IS_ERR (priv->misc)) { +dev_err (dev,"failed to find misc regmap\n" ); +return PTR_ERR (priv->misc); + } + + priv->phy =devm_phy_create (dev, &spear1340_miphy_ops,NULL ); +if (IS_ERR (priv->phy)) { +dev_err (dev,"failed to create SATA PCIe PHY\n" ); +return PTR_ERR (priv->phy); + } + +dev_set_drvdata (dev, priv); +phy_set_drvdata (priv->phy, priv); + + phy_provider = +devm_of_phy_provider_register (dev, spear1340_miphy_xlate); +if (IS_ERR (phy_provider)) { +dev_err (dev,"failed to register phy provider\n" ); +return PTR_ERR (phy_provider); + } + +return 0 ; +} + +static struct platform_driver spear1340_miphy_driver = { + .probe = spear1340_miphy_probe, + .driver = { + .name ="spear1340-miphy" , + .owner =THIS_MODULE , + .pm = &spear1340_miphy_pm_ops, + .of_match_table =of_match_ptr (spear1340_miphy_of_match), + }, +}; + +static int __init spear1340_miphy_phy_init (void ) +{ +return platform_driver_register (&spear1340_miphy_driver); +} +module_init (spear1340_miphy_phy_init); + +static void __exit spear1340_miphy_phy_exit(void) +{ +platform_driver_unregister (&spear1340_miphy_driver); +} +module_exit (spear1340_miphy_phy_exit); + +MODULE_DESCRIPTION ("ST SPEAR1340-MIPHY driver" ); +MODULE_AUTHOR ("Pratyush Anand <[email protected]>" ); +MODULE_LICENSE ("GPL v2" );
PATCH v8 5/9 phy: SPEAr1310/40-miphy: Add phy driver for PCIe and SATA
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
SPEAr1310/40 uses miphy for PCIe and SATA phy. This driver adds support for the same.
AHCI phy hookups from arch specific code has been cleaned up.
--- arch/arm/boot/dts/spear1310-evb.dts | 4 + arch/arm/boot/dts/spear1310.dtsi | 39 ++++- arch/arm/boot/dts/spear1340-evb.dts | 4 + arch/arm/boot/dts/spear1340.dtsi | 12 ++- arch/arm/boot/dts/spear13xx.dtsi | 5 + arch/arm/mach-spear/Kconfig | 3 + arch/arm/mach-spear/spear1340.c | 127 +--------------- drivers/phy/Kconfig | 12 ++ drivers/phy/Makefile | 2 + drivers/phy/phy-spear1310-miphy.c | 274 ++++++++++++++++++++++++++++++++ drivers/phy/phy-spear1340-miphy.c | 300 +++++++++++++++++++++++++++++++++++ 11 files changed, 652 insertions(+), 130 deletions(-) create mode 100644 drivers/phy/phy-spear1310-miphy.c create mode 100644 drivers/phy/phy-spear1340-miphy.c
arch/arm/boot/dts/spear1310-evb.dts +4 -0
@@ -106,6 +106,10 @@ status = "okay"; }; + miphy@eb800000 { + status = "okay"; + }; + cf@b2800000 { status = "okay"; };
arch/arm/boot/dts/spear1310.dtsi +36 -3
@@ -29,24 +29,57 @@ #gpio-cells = <2>; }; - ahci@b1000000 { + miphy0: miphy@eb800000 { + compatible = "st,miphy", "st,spear1310-miphy"; + reg = <0xeb800000 0x4000>; + misc = <&misc>; + phy-id = <0>; + #phy-cells = <1>; + status = "disabled"; + }; + + miphy1: miphy@eb804000 { + compatible = "st,miphy", "st,spear1310-miphy"; + reg = <0xeb804000 0x4000>; + misc = <&misc>; + phy-id = <1>; + #phy-cells = <1>; + status = "disabled"; + }; + + miphy2: miphy@eb808000 { + compatible = "st,miphy", "st,spear1310-miphy"; + reg = <0xeb808000 0x4000>; + misc = <&misc>; + phy-id = <2>; + #phy-cells = <1>; + status = "disabled"; + }; + + ahci0: ahci@b1000000 { compatible = "snps,spear-ahci"; reg = <0xb1000000 0x10000>; interrupts = <0 68 0x4>; + phys = <&miphy0 0>; + phy-names = "sata-phy"; status = "disabled"; }; - ahci@b1800000 { + ahci1: ahci@b1800000 { compatible = "snps,spear-ahci"; reg = <0xb1800000 0x10000>; interrupts = <0 69 0x4>; + phys = <&miphy1 0>; + phy-names = "sata-phy"; status = "disabled"; }; - ahci@b4000000 { + ahci2: ahci@b4000000 { compatible = "snps,spear-ahci"; reg = <0xb4000000 0x10000>; interrupts = <0 70 0x4>; + phys = <&miphy2 0>; + phy-names = "sata-phy"; status = "disabled"; };
arch/arm/boot/dts/spear1340-evb.dts +4 -0
@@ -122,6 +122,10 @@ status = "okay"; }; + miphy@eb800000 { + status = "okay"; + }; + dma@ea800000 { status = "okay"; };
arch/arm/boot/dts/spear1340.dtsi +11 -1
@@ -31,10 +31,20 @@ status = "disabled"; }; - ahci@b1000000 { + miphy0: miphy@eb800000 { + compatible = "st,miphy", "st,spear1340-miphy"; + reg = <0xeb800000 0x4000>; + misc = <&misc>; + #phy-cells = <1>; + status = "disabled"; + }; + + ahci0: ahci@b1000000 { compatible = "snps,spear-ahci"; reg = <0xb1000000 0x10000>; interrupts = <0 72 0x4>; + phys = <&miphy0 0>; + phy-names = "sata-phy"; status = "disabled"; };
arch/arm/boot/dts/spear13xx.dtsi +5 -0
@@ -220,6 +220,11 @@ 0xd8000000 0xd8000000 0x01000000 0xe0000000 0xe0000000 0x10000000>; + misc: syscon@e0700000 { + compatible = "st,spear1340-misc", "syscon"; + reg = <0xe0700000 0x1000>; + }; + gpio0: gpio@e0600000 { compatible = "arm,pl061", "arm,primecell"; reg = <0xe0600000 0x1000>;
arch/arm/mach-spear/Kconfig +3 -0
@@ -20,6 +20,7 @@ config ARCH_SPEAR13XX select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select PINCTRL + select MFD_SYSCON help Supports for ARM's SPEAR13XX family
@@ -28,12 +29,14 @@ if ARCH_SPEAR13XX config MACH_SPEAR1310 bool "SPEAr1310 Machine support with Device Tree" select PINCTRL_SPEAR1310 + select PHY_ST_SPEAR1310_MIPHY help Supports ST SPEAr1310 machine configured via the device-tree config MACH_SPEAR1340 bool "SPEAr1340 Machine support with Device Tree" select PINCTRL_SPEAR1340 + select PHY_ST_SPEAR1340_MIPHY help Supports ST SPEAr1340 machine configured via the device-tree
arch/arm/mach-spear/spear1340.c +1 -126
139 lines not on this page · raw message
drivers/phy/Kconfig +12 -0
@@ -166,4 +166,16 @@ config PHY_XGENE help This option enables support for APM X-Gene SoC multi-purpose PHY. +config PHY_ST_SPEAR1310_MIPHY + tristate "ST SPEAR1310-MIPHY driver" + select GENERIC_PHY + help + Support for ST SPEAr1310 MIPHY which can be used for PCIe and SATA. + +config PHY_ST_SPEAR1340_MIPHY + tristate "ST SPEAR1340-MIPHY driver" + select GENERIC_PHY + help + Support for ST SPEAr1340 MIPHY which can be used for PCIe and SATA. + endmenu
drivers/phy/Makefile +2 -0
@@ -18,3 +18,5 @@ obj-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o obj-$(CONFIG_PHY_EXYNOS4X12_USB2) += phy-exynos4x12-usb2.o obj-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o obj-$(CONFIG_PHY_XGENE) += phy-xgene.o +obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o +obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
drivers/phy/phy-spear1310-miphy.c new file +274 -0
274 lines not on this page · raw message
drivers/phy/phy-spear1340-miphy.c new file +300 -0
300 lines not on this page · raw message
Signature · 1 line
1.7.0.1
PATCH v8 5/9 phy: SPEAr1310/40-miphy: Add phy driver for PCIe and SATA
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
SPEAr1310/40 uses miphy for PCIe and SATA phy. This driver adds support for the same.
AHCI phy hookups from arch specific code has been cleaned up.
--- arch/arm/boot/dts/spear1310-evb.dts | 4 + arch/arm/boot/dts/spear1310.dtsi | 39 ++++- arch/arm/boot/dts/spear1340-evb.dts | 4 + arch/arm/boot/dts/spear1340.dtsi | 12 ++- arch/arm/boot/dts/spear13xx.dtsi | 5 + arch/arm/mach-spear/Kconfig | 3 + arch/arm/mach-spear/spear1340.c | 127 +--------------- drivers/phy/Kconfig | 12 ++ drivers/phy/Makefile | 2 + drivers/phy/phy-spear1310-miphy.c | 274 ++++++++++++++++++++++++++++++++ drivers/phy/phy-spear1340-miphy.c | 300 +++++++++++++++++++++++++++++++++++ 11 files changed, 652 insertions(+), 130 deletions(-) create mode 100644 drivers/phy/phy-spear1310-miphy.c create mode 100644 drivers/phy/phy-spear1340-miphy.c
arch/arm/boot/dts/spear1310-evb.dts +4 -0
@@ -106,6 +106,10 @@ status = "okay"; }; + miphy@eb800000 { + status = "okay"; + }; + cf@b2800000 { status = "okay"; };
arch/arm/boot/dts/spear1310.dtsi +36 -3
@@ -29,24 +29,57 @@ #gpio-cells = <2>; }; - ahci@b1000000 { + miphy0: miphy@eb800000 { + compatible = "st,miphy", "st,spear1310-miphy"; + reg = <0xeb800000 0x4000>; + misc = <&misc>; + phy-id = <0>; + #phy-cells = <1>; + status = "disabled"; + }; + + miphy1: miphy@eb804000 { + compatible = "st,miphy", "st,spear1310-miphy"; + reg = <0xeb804000 0x4000>; + misc = <&misc>; + phy-id = <1>; + #phy-cells = <1>; + status = "disabled"; + }; + + miphy2: miphy@eb808000 { + compatible = "st,miphy", "st,spear1310-miphy"; + reg = <0xeb808000 0x4000>; + misc = <&misc>; + phy-id = <2>; + #phy-cells = <1>; + status = "disabled"; + }; + + ahci0: ahci@b1000000 { compatible = "snps,spear-ahci"; reg = <0xb1000000 0x10000>; interrupts = <0 68 0x4>; + phys = <&miphy0 0>; + phy-names = "sata-phy"; status = "disabled"; }; - ahci@b1800000 { + ahci1: ahci@b1800000 { compatible = "snps,spear-ahci"; reg = <0xb1800000 0x10000>; interrupts = <0 69 0x4>; + phys = <&miphy1 0>; + phy-names = "sata-phy"; status = "disabled"; }; - ahci@b4000000 { + ahci2: ahci@b4000000 { compatible = "snps,spear-ahci"; reg = <0xb4000000 0x10000>; interrupts = <0 70 0x4>; + phys = <&miphy2 0>; + phy-names = "sata-phy"; status = "disabled"; };
arch/arm/boot/dts/spear1340-evb.dts +4 -0
@@ -122,6 +122,10 @@ status = "okay"; }; + miphy@eb800000 { + status = "okay"; + }; + dma@ea800000 { status = "okay"; };
arch/arm/boot/dts/spear1340.dtsi +11 -1
@@ -31,10 +31,20 @@ status = "disabled"; }; - ahci@b1000000 { + miphy0: miphy@eb800000 { + compatible = "st,miphy", "st,spear1340-miphy"; + reg = <0xeb800000 0x4000>; + misc = <&misc>; + #phy-cells = <1>; + status = "disabled"; + }; + + ahci0: ahci@b1000000 { compatible = "snps,spear-ahci"; reg = <0xb1000000 0x10000>; interrupts = <0 72 0x4>; + phys = <&miphy0 0>; + phy-names = "sata-phy"; status = "disabled"; };
arch/arm/boot/dts/spear13xx.dtsi +5 -0
@@ -220,6 +220,11 @@ 0xd8000000 0xd8000000 0x01000000 0xe0000000 0xe0000000 0x10000000>; + misc: syscon@e0700000 { + compatible = "st,spear1340-misc", "syscon"; + reg = <0xe0700000 0x1000>; + }; + gpio0: gpio@e0600000 { compatible = "arm,pl061", "arm,primecell"; reg = <0xe0600000 0x1000>;
arch/arm/mach-spear/Kconfig +3 -0
@@ -20,6 +20,7 @@ config ARCH_SPEAR13XX select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select PINCTRL + select MFD_SYSCON help Supports for ARM's SPEAR13XX family
@@ -28,12 +29,14 @@ if ARCH_SPEAR13XX config MACH_SPEAR1310 bool "SPEAr1310 Machine support with Device Tree" select PINCTRL_SPEAR1310 + select PHY_ST_SPEAR1310_MIPHY help Supports ST SPEAr1310 machine configured via the device-tree config MACH_SPEAR1340 bool "SPEAr1340 Machine support with Device Tree" select PINCTRL_SPEAR1340 + select PHY_ST_SPEAR1340_MIPHY help Supports ST SPEAr1340 machine configured via the device-tree
arch/arm/mach-spear/spear1340.c +1 -126
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drivers/phy/Kconfig +12 -0
@@ -166,4 +166,16 @@ config PHY_XGENE help This option enables support for APM X-Gene SoC multi-purpose PHY. +config PHY_ST_SPEAR1310_MIPHY + tristate "ST SPEAR1310-MIPHY driver" + select GENERIC_PHY + help + Support for ST SPEAr1310 MIPHY which can be used for PCIe and SATA. + +config PHY_ST_SPEAR1340_MIPHY + tristate "ST SPEAR1340-MIPHY driver" + select GENERIC_PHY + help + Support for ST SPEAr1340 MIPHY which can be used for PCIe and SATA. + endmenu
drivers/phy/Makefile +2 -0
@@ -18,3 +18,5 @@ obj-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o obj-$(CONFIG_PHY_EXYNOS4X12_USB2) += phy-exynos4x12-usb2.o obj-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o obj-$(CONFIG_PHY_XGENE) += phy-xgene.o +obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o +obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
drivers/phy/phy-spear1310-miphy.c new file +274 -0
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drivers/phy/phy-spear1340-miphy.c new file +300 -0
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PATCH v8 1/9 clk: SPEAr13XX: Fix pcie clock name
From: Pratyush Anand <[email protected]>
Follow dt clock naming convention for PCIe clocks.
--- drivers/clk/spear/spear1310_clock.c | 6 +++--- drivers/clk/spear/spear1340_clock.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-)
drivers/clk/spear/spear1310_clock.c +3 -3
@@ -742,19 +742,19 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) clk =clk_register_gate (NULL ,"pcie_sata_0_clk" ,"ahb_clk" ,0 ,SPEAR1310_PERIP1_CLK_ENB ,SPEAR1310_PCIE_SATA_0_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie.0" ); +clk_register_clkdev (clk,NULL ,"b1000000.pcie" );clk_register_clkdev (clk,NULL ,"b1000000.ahci" ); clk =clk_register_gate (NULL ,"pcie_sata_1_clk" ,"ahb_clk" ,0 ,SPEAR1310_PERIP1_CLK_ENB ,SPEAR1310_PCIE_SATA_1_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie.1" ); +clk_register_clkdev (clk,NULL ,"b1800000.pcie" );clk_register_clkdev (clk,NULL ,"b1800000.ahci" ); clk =clk_register_gate (NULL ,"pcie_sata_2_clk" ,"ahb_clk" ,0 ,SPEAR1310_PERIP1_CLK_ENB ,SPEAR1310_PCIE_SATA_2_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie.2" ); +clk_register_clkdev (clk,NULL ,"b4000000.pcie" );clk_register_clkdev (clk,NULL ,"b4000000.ahci" ); clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
drivers/clk/spear/spear1340_clock.c +1 -1
@@ -839,7 +839,7 @@ void __init spear1340_clk_init(void __iomem *misc_base) clk =clk_register_gate (NULL ,"pcie_sata_clk" ,"ahb_clk" ,0 ,SPEAR1340_PERIP1_CLK_ENB ,SPEAR1340_PCIE_SATA_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie" ); +clk_register_clkdev (clk,NULL ,"b1000000.pcie" );clk_register_clkdev (clk,NULL ,"b1000000.ahci" ); clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
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PATCH v8 2/9 SPEAr13XX: Fix static mapping table
In reply to a message not in the archiveFrom: Pratyush Anand <[email protected]>
SPEAr13XX was using virtual address space 0xFE000000 to map physical address space 0xB3000000. pci_remap_io uses 0xFEE00000 as virtual address. So change 0xFE000000 to 0xF9000000.
--- arch/arm/mach-spear/include/mach/spear.h | 4 ++-- arch/arm/mach-spear/spear13xx.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-)
arch/arm/mach-spear/include/mach/spear.h +2 -2
@@ -52,10 +52,10 @@#ifdef CONFIG_ARCH_SPEAR13XX #define PERIP_GRP2_BASE UL(0xB3000000) -#define VA_PERIP_GRP2_BASE IOMEM(0xFE000000) +#define VA_PERIP_GRP2_BASE IOMEM(0xF9000000)#define MCIF_SDHCI_BASE UL(0xB3000000)#define SYSRAM0_BASE UL(0xB3800000) -#define VA_SYSRAM0_BASE IOMEM(0xFE800000) +#define VA_SYSRAM0_BASE IOMEM(0xF9800000)#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600)#define PERIP_GRP1_BASE UL(0xE0000000)
arch/arm/mach-spear/spear13xx.c +1 -1
@@ -52,7 +52,7 @@ void __init spear13xx_l2x0_init(void)/* * Following will create 16MB static virtual/physical mappings * PHYSICAL VIRTUAL -* 0xB3000000 0xFE000000 +* 0xB3000000 0xF9000000 * 0xE0000000 0xFD000000 * 0xEC000000 0xFC000000 * 0xED000000 0xFB000000
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PATCH v8 5/9 phy: SPEAr1310/40-miphy: Add phy driver for PCIe and SATA
In reply to a message not in the archiveFrom: Pratyush Anand <[email protected]>
SPEAr1310/40 uses miphy for PCIe and SATA phy. This driver adds support for the same.
AHCI phy hookups from arch specific code has been cleaned up.
--- arch/arm/boot/dts/spear1310-evb.dts | 4 + arch/arm/boot/dts/spear1310.dtsi | 39 ++++- arch/arm/boot/dts/spear1340-evb.dts | 4 + arch/arm/boot/dts/spear1340.dtsi | 12 ++- arch/arm/boot/dts/spear13xx.dtsi | 5 + arch/arm/mach-spear/Kconfig | 3 + arch/arm/mach-spear/spear1340.c | 127 +--------------- drivers/phy/Kconfig | 12 ++ drivers/phy/Makefile | 2 + drivers/phy/phy-spear1310-miphy.c | 274 ++++++++++++++++++++++++++++++++ drivers/phy/phy-spear1340-miphy.c | 300 +++++++++++++++++++++++++++++++++++ 11 files changed, 652 insertions(+), 130 deletions(-) create mode 100644 drivers/phy/phy-spear1310-miphy.c create mode 100644 drivers/phy/phy-spear1340-miphy.c
arch/arm/boot/dts/spear1310-evb.dts +4 -0
@@ -106,6 +106,10 @@ status = "okay"; }; + miphy@eb800000 { + status = "okay"; + }; + cf@b2800000 { status = "okay"; };
arch/arm/boot/dts/spear1310.dtsi +36 -3
@@ -29,24 +29,57 @@ #gpio-cells = <2>; }; - ahci@b1000000 { + miphy0: miphy@eb800000 { + compatible = "st,miphy", "st,spear1310-miphy"; + reg = <0xeb800000 0x4000>; + misc = <&misc>; + phy-id = <0>; + #phy-cells = <1>; + status = "disabled"; + }; + + miphy1: miphy@eb804000 { + compatible = "st,miphy", "st,spear1310-miphy"; + reg = <0xeb804000 0x4000>; + misc = <&misc>; + phy-id = <1>; + #phy-cells = <1>; + status = "disabled"; + }; + + miphy2: miphy@eb808000 { + compatible = "st,miphy", "st,spear1310-miphy"; + reg = <0xeb808000 0x4000>; + misc = <&misc>; + phy-id = <2>; + #phy-cells = <1>; + status = "disabled"; + }; + + ahci0: ahci@b1000000 { compatible = "snps,spear-ahci"; reg = <0xb1000000 0x10000>; interrupts = <0 68 0x4>; + phys = <&miphy0 0>; + phy-names = "sata-phy"; status = "disabled"; }; - ahci@b1800000 { + ahci1: ahci@b1800000 { compatible = "snps,spear-ahci"; reg = <0xb1800000 0x10000>; interrupts = <0 69 0x4>; + phys = <&miphy1 0>; + phy-names = "sata-phy"; status = "disabled"; }; - ahci@b4000000 { + ahci2: ahci@b4000000 { compatible = "snps,spear-ahci"; reg = <0xb4000000 0x10000>; interrupts = <0 70 0x4>; + phys = <&miphy2 0>; + phy-names = "sata-phy"; status = "disabled"; };
arch/arm/boot/dts/spear1340-evb.dts +4 -0
@@ -122,6 +122,10 @@ status = "okay"; }; + miphy@eb800000 { + status = "okay"; + }; + dma@ea800000 { status = "okay"; };
arch/arm/boot/dts/spear1340.dtsi +11 -1
@@ -31,10 +31,20 @@ status = "disabled"; }; - ahci@b1000000 { + miphy0: miphy@eb800000 { + compatible = "st,miphy", "st,spear1340-miphy"; + reg = <0xeb800000 0x4000>; + misc = <&misc>; + #phy-cells = <1>; + status = "disabled"; + }; + + ahci0: ahci@b1000000 { compatible = "snps,spear-ahci"; reg = <0xb1000000 0x10000>; interrupts = <0 72 0x4>; + phys = <&miphy0 0>; + phy-names = "sata-phy"; status = "disabled"; };
arch/arm/boot/dts/spear13xx.dtsi +5 -0
@@ -220,6 +220,11 @@ 0xd8000000 0xd8000000 0x01000000 0xe0000000 0xe0000000 0x10000000>; + misc: syscon@e0700000 { + compatible = "st,spear1340-misc", "syscon"; + reg = <0xe0700000 0x1000>; + }; + gpio0: gpio@e0600000 { compatible = "arm,pl061", "arm,primecell"; reg = <0xe0600000 0x1000>;
arch/arm/mach-spear/Kconfig +3 -0
@@ -20,6 +20,7 @@ config ARCH_SPEAR13XX select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select PINCTRL + select MFD_SYSCON help Supports for ARM's SPEAR13XX family
@@ -28,12 +29,14 @@ if ARCH_SPEAR13XX config MACH_SPEAR1310 bool "SPEAr1310 Machine support with Device Tree" select PINCTRL_SPEAR1310 + select PHY_ST_SPEAR1310_MIPHY help Supports ST SPEAr1310 machine configured via the device-tree config MACH_SPEAR1340 bool "SPEAr1340 Machine support with Device Tree" select PINCTRL_SPEAR1340 + select PHY_ST_SPEAR1340_MIPHY help Supports ST SPEAr1340 machine configured via the device-tree
arch/arm/mach-spear/spear1340.c +1 -126
139 lines not on this page · raw message
drivers/phy/Kconfig +12 -0
@@ -166,4 +166,16 @@ config PHY_XGENE help This option enables support for APM X-Gene SoC multi-purpose PHY. +config PHY_ST_SPEAR1310_MIPHY + tristate "ST SPEAR1310-MIPHY driver" + select GENERIC_PHY + help + Support for ST SPEAr1310 MIPHY which can be used for PCIe and SATA. + +config PHY_ST_SPEAR1340_MIPHY + tristate "ST SPEAR1340-MIPHY driver" + select GENERIC_PHY + help + Support for ST SPEAr1340 MIPHY which can be used for PCIe and SATA. + endmenu
drivers/phy/Makefile +2 -0
@@ -18,3 +18,5 @@ obj-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o obj-$(CONFIG_PHY_EXYNOS4X12_USB2) += phy-exynos4x12-usb2.o obj-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o obj-$(CONFIG_PHY_XGENE) += phy-xgene.o +obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o +obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
drivers/phy/phy-spear1310-miphy.c new file +274 -0
274 lines not on this page · raw message
drivers/phy/phy-spear1340-miphy.c new file +300 -0
300 lines not on this page · raw message
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PATCH v8 7/9 SPEAr13XX: dts: Add PCIe node information
In reply to a message not in the archiveFrom: Pratyush Anand <[email protected]>
SPEAr1310 and SPEAr1340 supports 3 and 1 PCIe controller respectively. These controllers are based on synopsys designware controller.
--- arch/arm/boot/dts/spear1310.dtsi | 48 ++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/spear1340.dtsi | 16 ++++++++++++ 2 files changed, 64 insertions(+), 0 deletions(-)
arch/arm/boot/dts/spear1310.dtsi +48 -0
@@ -83,6 +83,54 @@ status = "disabled"; }; + pcie0: pcie@b1000000 { + compatible = "st,spear1340-pcie", "snps,dw-pcie"; + reg = <0xb1000000 0x4000>; + interrupts = <0 68 0x4>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 0 68 0x4>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */ + 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + status = "disabled"; + }; + + pcie1: pcie@b1800000 { + compatible = "st,spear1340-pcie", "snps,dw-pcie"; + reg = <0xb1800000 0x4000>; + interrupts = <0 69 0x4>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 0 69 0x4>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x90000000 0x90000000 0 0x00020000 /* configuration space */ + 0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */ + status = "disabled"; + }; + + pcie2: pcie@b4000000 { + compatible = "st,spear1340-pcie", "snps,dw-pcie"; + reg = <0xb4000000 0x4000>; + interrupts = <0 70 0x4>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 0 70 0x4>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0xc0000000 0xc0000000 0 0x00020000 /* configuration space */ + 0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + status = "disabled"; + }; + gmac1: eth@5c400000 { compatible = "st,spear600-gmac"; reg = <0x5c400000 0x8000>;
arch/arm/boot/dts/spear1340.dtsi +16 -0
@@ -48,6 +48,22 @@ status = "disabled"; }; + pcie0: pcie@b1000000 { + compatible = "st,spear1340-pcie", "snps,dw-pcie"; + reg = <0xb1000000 0x4000>; + interrupts = <0 68 0x4>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 0 68 0x4>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */ + 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + status = "disabled"; + }; + i2s-play@b2400000 { compatible = "snps,designware-i2s"; reg = <0xb2400000 0x10000>;
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PATCH v8 8/9 pcie: SPEAr13xx: Add designware wrapper support
In reply to a message not in the archiveFrom: Pratyush Anand <[email protected]>
SPEAr1310 and SPEAr1340 SOC uses designware PCIe controller. Add SPEAr13xx PCIe driver based on designware controller driver.
SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed with ahci/sata pins. By default evaluation board of both controller works for ahci mode.
To use these patches on SPEAr1340/1310 evaluation board, do the necessary modifications on board and enable (okay) pcie and miphy from respective evb dtsi file.
Add Mohit Kumar as maintainer for ST SPEAr13xx PCIe driver.
--- MAINTAINERS | 6 + arch/arm/boot/dts/spear1310.dtsi | 6 + arch/arm/boot/dts/spear1340.dtsi | 2 + arch/arm/boot/dts/spear13xx.dtsi | 4 +- arch/arm/mach-spear/Kconfig | 1 + drivers/pci/host/Kconfig | 8 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pcie-spear13xx.c | 407 +++++++++++++++++++++++++++++++++++++ 8 files changed, 433 insertions(+), 2 deletions(-) create mode 100644 drivers/pci/host/pcie-spear13xx.c
MAINTAINERS +6 -0
@@ -6734,6 +6734,12 @@ L: [email protected] S: Maintained F: drivers/pci/host/*designware* +PCIE DRIVER FOR ST SPEAR13XX +M: Mohit Kumar <[email protected]> +L: [email protected] +S: Maintained +F: drivers/pci/host/pcie-spear13xx.c + PCMCIA SUBSYSTEM P: Linux PCMCIA Team L: [email protected]
arch/arm/boot/dts/spear1310.dtsi +6 -0
@@ -90,6 +90,8 @@ interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 0 68 0x4>; num-lanes = <1>; + phys = <&miphy0 1>; + phy-names = "pcie-phy"; #address-cells = <3>; #size-cells = <2>; device_type = "pci";
@@ -106,6 +108,8 @@ interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 0 69 0x4>; num-lanes = <1>; + phys = <&miphy1 1>; + phy-names = "pcie-phy"; #address-cells = <3>; #size-cells = <2>; device_type = "pci";
@@ -122,6 +126,8 @@ interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 0 70 0x4>; num-lanes = <1>; + phys = <&miphy2 1>; + phy-names = "pcie-phy"; #address-cells = <3>; #size-cells = <2>; device_type = "pci";
arch/arm/boot/dts/spear1340.dtsi +2 -0
@@ -55,6 +55,8 @@ interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 0 68 0x4>; num-lanes = <1>; + phys = <&miphy0 1>; + phy-names = "pcie-phy"; #address-cells = <3>; #size-cells = <2>; device_type = "pci";
arch/arm/boot/dts/spear13xx.dtsi +2 -2
@@ -83,8 +83,8 @@ #size-cells = <1>; compatible = "simple-bus"; ranges = <0x50000000 0x50000000 0x10000000 - 0xb0000000 0xb0000000 0x10000000 - 0xd0000000 0xd0000000 0x02000000 + 0x80000000 0x80000000 0x20000000 + 0xb0000000 0xb0000000 0x22000000 0xd8000000 0xd8000000 0x01000000 0xe0000000 0xe0000000 0x10000000>;
arch/arm/mach-spear/Kconfig +1 -0
@@ -21,6 +21,7 @@ config ARCH_SPEAR13XX select HAVE_ARM_TWD if SMP select PINCTRL select MFD_SYSCON + select MIGHT_HAVE_PCI help Supports for ARM's SPEAR13XX family
drivers/pci/host/Kconfig +8 -0
@@ -33,4 +33,12 @@ config PCI_RCAR_GEN2 There are 3 internal PCI controllers available with a single built-in EHCI/OHCI host controller present on each one. +config PCIE_SPEAR13XX + tristate "STMicroelectronics SPEAr PCIe controller" + depends on ARCH_SPEAR13XX + select PCIEPORTBUS + select PCIE_DW + help + Say Y here if you want PCIe support on SPEAr13XX SoCs. + endmenu
drivers/pci/host/Makefile +1 -0
@@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o +obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
drivers/pci/host/pcie-spear13xx.c new file +407 -0
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PATCH v8 9/9 SPEAr13xx: defconfig: Update
In reply to a message not in the archiveEnable PCIe, EABI, VFP and NFS configs in default configuration file for SPEAr13xx.
--- arch/arm/configs/spear13xx_defconfig | 16 ++++++++++++++++ 1 files changed, 16 insertions(+), 0 deletions(-)
arch/arm/configs/spear13xx_defconfig +16 -0
@@ -11,13 +11,24 @@ CONFIG_ARCH_SPEAR13XX=y CONFIG_MACH_SPEAR1310=y CONFIG_MACH_SPEAR1340=y # CONFIG_SWP_EMULATE is not set +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCIE_SPEAR13XX=y CONFIG_SMP=y # CONFIG_SMP_ON_UP is not set # CONFIG_ARM_CPU_TOPOLOGY is not set +CONFIG_AEABI=y CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_VFP=y CONFIG_BINFMT_MISC=y CONFIG_NET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_NET_IPIP=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_OF_PARTS=y
@@ -27,6 +38,7 @@ CONFIG_MTD_NAND=y CONFIG_MTD_NAND_FSMC=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_BLK_DEV_SD=y CONFIG_ATA=y # CONFIG_SATA_PMP is not set CONFIG_SATA_AHCI_PLATFORM=y
@@ -66,6 +78,7 @@ CONFIG_USB=y # CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_USB_STORAGE=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SPEAR=y
@@ -79,11 +92,14 @@ CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_SECURITY=y CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=y CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_FAT_DEFAULT_IOCHARSET="ascii" CONFIG_TMPFS=y CONFIG_JFFS2_FS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=m
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PATCH v8 6/9 SPEAr13XX: Add binding information for PCIe controller
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
SPEAr13XX uses designware PCIe controller. This patch adds information for the PCIe binding properties which are specific to SPEAr13XX SoC series.
--- .../devicetree/bindings/pci/spear13xx-pcie.txt | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
Documentation/devicetree/bindings/pci/spear13xx-pcie.txt new file +14 -0
@@ -0,0 +1,14 @@ +SPEAr13XX PCIe DT detail: +================================ + +SPEAr13XX uses synopsis designware PCIe controller and ST MiPHY as phy +controller. + +Required properties: +- compatible : should be "st,spear1340-pcie", "snps,dw-pcie". +- phys : phandle to phy node associated with pcie controller +- phy-names : must be "pcie-phy" +- All other definitions as per generic PCI bindings + + Optional properties: +- st,pcie-is-gen1 indicates that forced gen1 initialization is needed.
Signature · 6 lines
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PATCH v8 7/9 SPEAr13XX: dts: Add PCIe node information
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
SPEAr1310 and SPEAr1340 supports 3 and 1 PCIe controller respectively. These controllers are based on synopsys designware controller.
--- arch/arm/boot/dts/spear1310.dtsi | 48 ++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/spear1340.dtsi | 16 ++++++++++++ 2 files changed, 64 insertions(+), 0 deletions(-)
arch/arm/boot/dts/spear1310.dtsi +48 -0
@@ -83,6 +83,54 @@ status = "disabled"; }; + pcie0: pcie at b1000000 { + compatible = "st,spear1340-pcie", "snps,dw-pcie"; + reg = <0xb1000000 0x4000>; + interrupts = <0 68 0x4>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 0 68 0x4>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */ + 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + status = "disabled"; + }; + + pcie1: pcie at b1800000 { + compatible = "st,spear1340-pcie", "snps,dw-pcie"; + reg = <0xb1800000 0x4000>; + interrupts = <0 69 0x4>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 0 69 0x4>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x90000000 0x90000000 0 0x00020000 /* configuration space */ + 0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */ + status = "disabled"; + }; + + pcie2: pcie at b4000000 { + compatible = "st,spear1340-pcie", "snps,dw-pcie"; + reg = <0xb4000000 0x4000>; + interrupts = <0 70 0x4>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 0 70 0x4>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0xc0000000 0xc0000000 0 0x00020000 /* configuration space */ + 0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + status = "disabled"; + }; + gmac1: eth at 5c400000 { compatible = "st,spear600-gmac"; reg = <0x5c400000 0x8000>;
arch/arm/boot/dts/spear1340.dtsi +16 -0
@@ -48,6 +48,22 @@ status = "disabled"; }; + pcie0: pcie at b1000000 { + compatible = "st,spear1340-pcie", "snps,dw-pcie"; + reg = <0xb1000000 0x4000>; + interrupts = <0 68 0x4>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 0 68 0x4>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */ + 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + status = "disabled"; + }; + i2s-play at b2400000 { compatible = "snps,designware-i2s"; reg = <0xb2400000 0x10000>;
Signature · 1 line
1.7.0.1
PATCH v8 7/9 SPEAr13XX: dts: Add PCIe node information
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
SPEAr1310 and SPEAr1340 supports 3 and 1 PCIe controller respectively. These controllers are based on synopsys designware controller.
--- arch/arm/boot/dts/spear1310.dtsi | 48 ++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/spear1340.dtsi | 16 ++++++++++++ 2 files changed, 64 insertions(+), 0 deletions(-)
arch/arm/boot/dts/spear1310.dtsi +48 -0
@@ -83,6 +83,54 @@ status = "disabled"; }; + pcie0: pcie@b1000000 { + compatible = "st,spear1340-pcie", "snps,dw-pcie"; + reg = <0xb1000000 0x4000>; + interrupts = <0 68 0x4>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 0 68 0x4>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */ + 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + status = "disabled"; + }; + + pcie1: pcie@b1800000 { + compatible = "st,spear1340-pcie", "snps,dw-pcie"; + reg = <0xb1800000 0x4000>; + interrupts = <0 69 0x4>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 0 69 0x4>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x90000000 0x90000000 0 0x00020000 /* configuration space */ + 0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */ + status = "disabled"; + }; + + pcie2: pcie@b4000000 { + compatible = "st,spear1340-pcie", "snps,dw-pcie"; + reg = <0xb4000000 0x4000>; + interrupts = <0 70 0x4>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 0 70 0x4>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0xc0000000 0xc0000000 0 0x00020000 /* configuration space */ + 0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + status = "disabled"; + }; + gmac1: eth@5c400000 { compatible = "st,spear600-gmac"; reg = <0x5c400000 0x8000>;
arch/arm/boot/dts/spear1340.dtsi +16 -0
@@ -48,6 +48,22 @@ status = "disabled"; }; + pcie0: pcie@b1000000 { + compatible = "st,spear1340-pcie", "snps,dw-pcie"; + reg = <0xb1000000 0x4000>; + interrupts = <0 68 0x4>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 0 68 0x4>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */ + 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + status = "disabled"; + }; + i2s-play@b2400000 { compatible = "snps,designware-i2s"; reg = <0xb2400000 0x10000>;
Signature · 1 line
1.7.0.1
PATCH v8 7/9 SPEAr13XX: dts: Add PCIe node information
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
SPEAr1310 and SPEAr1340 supports 3 and 1 PCIe controller respectively. These controllers are based on synopsys designware controller.
--- arch/arm/boot/dts/spear1310.dtsi | 48 ++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/spear1340.dtsi | 16 ++++++++++++ 2 files changed, 64 insertions(+), 0 deletions(-)
arch/arm/boot/dts/spear1310.dtsi +48 -0
@@ -83,6 +83,54 @@ status = "disabled"; }; + pcie0: pcie@b1000000 { + compatible = "st,spear1340-pcie", "snps,dw-pcie"; + reg = <0xb1000000 0x4000>; + interrupts = <0 68 0x4>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 0 68 0x4>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */ + 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + status = "disabled"; + }; + + pcie1: pcie@b1800000 { + compatible = "st,spear1340-pcie", "snps,dw-pcie"; + reg = <0xb1800000 0x4000>; + interrupts = <0 69 0x4>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 0 69 0x4>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x90000000 0x90000000 0 0x00020000 /* configuration space */ + 0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */ + status = "disabled"; + }; + + pcie2: pcie@b4000000 { + compatible = "st,spear1340-pcie", "snps,dw-pcie"; + reg = <0xb4000000 0x4000>; + interrupts = <0 70 0x4>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 0 70 0x4>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0xc0000000 0xc0000000 0 0x00020000 /* configuration space */ + 0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + status = "disabled"; + }; + gmac1: eth@5c400000 { compatible = "st,spear600-gmac"; reg = <0x5c400000 0x8000>;
arch/arm/boot/dts/spear1340.dtsi +16 -0
@@ -48,6 +48,22 @@ status = "disabled"; }; + pcie0: pcie@b1000000 { + compatible = "st,spear1340-pcie", "snps,dw-pcie"; + reg = <0xb1000000 0x4000>; + interrupts = <0 68 0x4>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 0 68 0x4>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */ + 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + status = "disabled"; + }; + i2s-play@b2400000 { compatible = "snps,designware-i2s"; reg = <0xb2400000 0x10000>;
Signature · 1 line
1.7.0.1
PATCH v8 8/9 pcie: SPEAr13xx: Add designware wrapper support
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
SPEAr1310 and SPEAr1340 SOC uses designware PCIe controller. Add SPEAr13xx PCIe driver based on designware controller driver.
SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed with ahci/sata pins. By default evaluation board of both controller works for ahci mode.
To use these patches on SPEAr1340/1310 evaluation board, do the necessary modifications on board and enable (okay) pcie and miphy from respective evb dtsi file.
Add Mohit Kumar as maintainer for ST SPEAr13xx PCIe driver.
--- MAINTAINERS | 6 + arch/arm/boot/dts/spear1310.dtsi | 6 + arch/arm/boot/dts/spear1340.dtsi | 2 + arch/arm/boot/dts/spear13xx.dtsi | 4 +- arch/arm/mach-spear/Kconfig | 1 + drivers/pci/host/Kconfig | 8 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pcie-spear13xx.c | 407 +++++++++++++++++++++++++++++++++++++ 8 files changed, 433 insertions(+), 2 deletions(-) create mode 100644 drivers/pci/host/pcie-spear13xx.c
MAINTAINERS +6 -0
@@ -6734,6 +6734,12 @@ L: [email protected] S: Maintained F: drivers/pci/host/*designware* +PCIE DRIVER FOR ST SPEAR13XX +M: Mohit Kumar <[email protected]> +L: [email protected] +S: Maintained +F: drivers/pci/host/pcie-spear13xx.c + PCMCIA SUBSYSTEM P: Linux PCMCIA Team L: [email protected]
arch/arm/boot/dts/spear1310.dtsi +6 -0
@@ -90,6 +90,8 @@ interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 0 68 0x4>; num-lanes = <1>; + phys = <&miphy0 1>; + phy-names = "pcie-phy"; #address-cells = <3>; #size-cells = <2>; device_type = "pci";
@@ -106,6 +108,8 @@ interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 0 69 0x4>; num-lanes = <1>; + phys = <&miphy1 1>; + phy-names = "pcie-phy"; #address-cells = <3>; #size-cells = <2>; device_type = "pci";
@@ -122,6 +126,8 @@ interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 0 70 0x4>; num-lanes = <1>; + phys = <&miphy2 1>; + phy-names = "pcie-phy"; #address-cells = <3>; #size-cells = <2>; device_type = "pci";
arch/arm/boot/dts/spear1340.dtsi +2 -0
@@ -55,6 +55,8 @@ interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 0 68 0x4>; num-lanes = <1>; + phys = <&miphy0 1>; + phy-names = "pcie-phy"; #address-cells = <3>; #size-cells = <2>; device_type = "pci";
arch/arm/boot/dts/spear13xx.dtsi +2 -2
@@ -83,8 +83,8 @@ #size-cells = <1>; compatible = "simple-bus"; ranges = <0x50000000 0x50000000 0x10000000 - 0xb0000000 0xb0000000 0x10000000 - 0xd0000000 0xd0000000 0x02000000 + 0x80000000 0x80000000 0x20000000 + 0xb0000000 0xb0000000 0x22000000 0xd8000000 0xd8000000 0x01000000 0xe0000000 0xe0000000 0x10000000>;
arch/arm/mach-spear/Kconfig +1 -0
@@ -21,6 +21,7 @@ config ARCH_SPEAR13XX select HAVE_ARM_TWD if SMP select PINCTRL select MFD_SYSCON + select MIGHT_HAVE_PCI help Supports for ARM's SPEAR13XX family
drivers/pci/host/Kconfig +8 -0
@@ -33,4 +33,12 @@ config PCI_RCAR_GEN2 There are 3 internal PCI controllers available with a single built-in EHCI/OHCI host controller present on each one. +config PCIE_SPEAR13XX + tristate "STMicroelectronics SPEAr PCIe controller" + depends on ARCH_SPEAR13XX + select PCIEPORTBUS + select PCIE_DW + help + Say Y here if you want PCIe support on SPEAr13XX SoCs. + endmenu
drivers/pci/host/Makefile +1 -0
@@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o +obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
drivers/pci/host/pcie-spear13xx.c new file +407 -0
407 lines not on this page · raw message
Signature · 1 line
1.7.0.1
PATCH v8 8/9 pcie: SPEAr13xx: Add designware wrapper support
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
SPEAr1310 and SPEAr1340 SOC uses designware PCIe controller. Add SPEAr13xx PCIe driver based on designware controller driver.
SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed with ahci/sata pins. By default evaluation board of both controller works for ahci mode.
To use these patches on SPEAr1340/1310 evaluation board, do the necessary modifications on board and enable (okay) pcie and miphy from respective evb dtsi file.
Add Mohit Kumar as maintainer for ST SPEAr13xx PCIe driver.
--- MAINTAINERS | 6 + arch/arm/boot/dts/spear1310.dtsi | 6 + arch/arm/boot/dts/spear1340.dtsi | 2 + arch/arm/boot/dts/spear13xx.dtsi | 4 +- arch/arm/mach-spear/Kconfig | 1 + drivers/pci/host/Kconfig | 8 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pcie-spear13xx.c | 407 +++++++++++++++++++++++++++++++++++++ 8 files changed, 433 insertions(+), 2 deletions(-) create mode 100644 drivers/pci/host/pcie-spear13xx.c
MAINTAINERS +6 -0
@@ -6734,6 +6734,12 @@ L: [email protected] S: Maintained F: drivers/pci/host/*designware* +PCIE DRIVER FOR ST SPEAR13XX +M: Mohit Kumar <[email protected]> +L: [email protected] +S: Maintained +F: drivers/pci/host/pcie-spear13xx.c + PCMCIA SUBSYSTEM P: Linux PCMCIA Team L: [email protected]
arch/arm/boot/dts/spear1310.dtsi +6 -0
@@ -90,6 +90,8 @@ interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 0 68 0x4>; num-lanes = <1>; + phys = <&miphy0 1>; + phy-names = "pcie-phy"; #address-cells = <3>; #size-cells = <2>; device_type = "pci";
@@ -106,6 +108,8 @@ interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 0 69 0x4>; num-lanes = <1>; + phys = <&miphy1 1>; + phy-names = "pcie-phy"; #address-cells = <3>; #size-cells = <2>; device_type = "pci";
@@ -122,6 +126,8 @@ interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 0 70 0x4>; num-lanes = <1>; + phys = <&miphy2 1>; + phy-names = "pcie-phy"; #address-cells = <3>; #size-cells = <2>; device_type = "pci";
arch/arm/boot/dts/spear1340.dtsi +2 -0
@@ -55,6 +55,8 @@ interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 0 68 0x4>; num-lanes = <1>; + phys = <&miphy0 1>; + phy-names = "pcie-phy"; #address-cells = <3>; #size-cells = <2>; device_type = "pci";
arch/arm/boot/dts/spear13xx.dtsi +2 -2
@@ -83,8 +83,8 @@ #size-cells = <1>; compatible = "simple-bus"; ranges = <0x50000000 0x50000000 0x10000000 - 0xb0000000 0xb0000000 0x10000000 - 0xd0000000 0xd0000000 0x02000000 + 0x80000000 0x80000000 0x20000000 + 0xb0000000 0xb0000000 0x22000000 0xd8000000 0xd8000000 0x01000000 0xe0000000 0xe0000000 0x10000000>;
arch/arm/mach-spear/Kconfig +1 -0
@@ -21,6 +21,7 @@ config ARCH_SPEAR13XX select HAVE_ARM_TWD if SMP select PINCTRL select MFD_SYSCON + select MIGHT_HAVE_PCI help Supports for ARM's SPEAR13XX family
drivers/pci/host/Kconfig +8 -0
@@ -33,4 +33,12 @@ config PCI_RCAR_GEN2 There are 3 internal PCI controllers available with a single built-in EHCI/OHCI host controller present on each one. +config PCIE_SPEAR13XX + tristate "STMicroelectronics SPEAr PCIe controller" + depends on ARCH_SPEAR13XX + select PCIEPORTBUS + select PCIE_DW + help + Say Y here if you want PCIe support on SPEAr13XX SoCs. + endmenu
drivers/pci/host/Makefile +1 -0
@@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o +obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
drivers/pci/host/pcie-spear13xx.c new file +407 -0
407 lines not on this page · raw message
Signature · 1 line
1.7.0.1
PATCH v8 8/9 pcie: SPEAr13xx: Add designware wrapper support
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
SPEAr1310 and SPEAr1340 SOC uses designware PCIe controller. Add SPEAr13xx PCIe driver based on designware controller driver.
SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed with ahci/sata pins. By default evaluation board of both controller works for ahci mode.
To use these patches on SPEAr1340/1310 evaluation board, do the necessary modifications on board and enable (okay) pcie and miphy from respective evb dtsi file.
Add Mohit Kumar as maintainer for ST SPEAr13xx PCIe driver.
--- MAINTAINERS | 6 + arch/arm/boot/dts/spear1310.dtsi | 6 + arch/arm/boot/dts/spear1340.dtsi | 2 + arch/arm/boot/dts/spear13xx.dtsi | 4 +- arch/arm/mach-spear/Kconfig | 1 + drivers/pci/host/Kconfig | 8 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pcie-spear13xx.c | 407 +++++++++++++++++++++++++++++++++++++ 8 files changed, 433 insertions(+), 2 deletions(-) create mode 100644 drivers/pci/host/pcie-spear13xx.c
MAINTAINERS +6 -0
@@ -6734,6 +6734,12 @@ L: [email protected] S: Maintained F: drivers/pci/host/*designware* +PCIE DRIVER FOR ST SPEAR13XX +M: Mohit Kumar <[email protected]> +L: [email protected] +S: Maintained +F: drivers/pci/host/pcie-spear13xx.c + PCMCIA SUBSYSTEM P: Linux PCMCIA Team L: [email protected]
arch/arm/boot/dts/spear1310.dtsi +6 -0
@@ -90,6 +90,8 @@ interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 0 68 0x4>; num-lanes = <1>; + phys = <&miphy0 1>; + phy-names = "pcie-phy"; #address-cells = <3>; #size-cells = <2>; device_type = "pci";
@@ -106,6 +108,8 @@ interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 0 69 0x4>; num-lanes = <1>; + phys = <&miphy1 1>; + phy-names = "pcie-phy"; #address-cells = <3>; #size-cells = <2>; device_type = "pci";
@@ -122,6 +126,8 @@ interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 0 70 0x4>; num-lanes = <1>; + phys = <&miphy2 1>; + phy-names = "pcie-phy"; #address-cells = <3>; #size-cells = <2>; device_type = "pci";
arch/arm/boot/dts/spear1340.dtsi +2 -0
@@ -55,6 +55,8 @@ interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 0 68 0x4>; num-lanes = <1>; + phys = <&miphy0 1>; + phy-names = "pcie-phy"; #address-cells = <3>; #size-cells = <2>; device_type = "pci";
arch/arm/boot/dts/spear13xx.dtsi +2 -2
@@ -83,8 +83,8 @@ #size-cells = <1>; compatible = "simple-bus"; ranges = <0x50000000 0x50000000 0x10000000 - 0xb0000000 0xb0000000 0x10000000 - 0xd0000000 0xd0000000 0x02000000 + 0x80000000 0x80000000 0x20000000 + 0xb0000000 0xb0000000 0x22000000 0xd8000000 0xd8000000 0x01000000 0xe0000000 0xe0000000 0x10000000>;
arch/arm/mach-spear/Kconfig +1 -0
@@ -21,6 +21,7 @@ config ARCH_SPEAR13XX select HAVE_ARM_TWD if SMP select PINCTRL select MFD_SYSCON + select MIGHT_HAVE_PCI help Supports for ARM's SPEAR13XX family
drivers/pci/host/Kconfig +8 -0
@@ -33,4 +33,12 @@ config PCI_RCAR_GEN2 There are 3 internal PCI controllers available with a single built-in EHCI/OHCI host controller present on each one. +config PCIE_SPEAR13XX + tristate "STMicroelectronics SPEAr PCIe controller" + depends on ARCH_SPEAR13XX + select PCIEPORTBUS + select PCIE_DW + help + Say Y here if you want PCIe support on SPEAr13XX SoCs. + endmenu
drivers/pci/host/Makefile +1 -0
@@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o +obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
drivers/pci/host/pcie-spear13xx.c new file +407 -0
407 lines not on this page · raw message
Signature · 1 line
1.7.0.1
PATCH v8 9/9 SPEAr13xx: defconfig: Update
In reply to Mohit KumarEnable PCIe, EABI, VFP and NFS configs in default configuration file for SPEAr13xx.
--- arch/arm/configs/spear13xx_defconfig | 16 ++++++++++++++++ 1 files changed, 16 insertions(+), 0 deletions(-)
arch/arm/configs/spear13xx_defconfig +16 -0
@@ -11,13 +11,24 @@ CONFIG_ARCH_SPEAR13XX=y CONFIG_MACH_SPEAR1310=y CONFIG_MACH_SPEAR1340=y # CONFIG_SWP_EMULATE is not set +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCIE_SPEAR13XX=y CONFIG_SMP=y # CONFIG_SMP_ON_UP is not set # CONFIG_ARM_CPU_TOPOLOGY is not set +CONFIG_AEABI=y CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_VFP=y CONFIG_BINFMT_MISC=y CONFIG_NET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_NET_IPIP=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_OF_PARTS=y
@@ -27,6 +38,7 @@ CONFIG_MTD_NAND=y CONFIG_MTD_NAND_FSMC=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_BLK_DEV_SD=y CONFIG_ATA=y # CONFIG_SATA_PMP is not set CONFIG_SATA_AHCI_PLATFORM=y
@@ -66,6 +78,7 @@ CONFIG_USB=y # CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_USB_STORAGE=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SPEAR=y
@@ -79,11 +92,14 @@ CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_SECURITY=y CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=y CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_FAT_DEFAULT_IOCHARSET="ascii" CONFIG_TMPFS=y CONFIG_JFFS2_FS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=m
Signature · 1 line
1.7.0.1
PATCH v8 9/9 SPEAr13xx: defconfig: Update
In reply to Mohit KumarEnable PCIe, EABI, VFP and NFS configs in default configuration file for SPEAr13xx.
--- arch/arm/configs/spear13xx_defconfig | 16 ++++++++++++++++ 1 files changed, 16 insertions(+), 0 deletions(-)
arch/arm/configs/spear13xx_defconfig +16 -0
@@ -11,13 +11,24 @@ CONFIG_ARCH_SPEAR13XX=y CONFIG_MACH_SPEAR1310=y CONFIG_MACH_SPEAR1340=y # CONFIG_SWP_EMULATE is not set +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCIE_SPEAR13XX=y CONFIG_SMP=y # CONFIG_SMP_ON_UP is not set # CONFIG_ARM_CPU_TOPOLOGY is not set +CONFIG_AEABI=y CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_VFP=y CONFIG_BINFMT_MISC=y CONFIG_NET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_NET_IPIP=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_OF_PARTS=y
@@ -27,6 +38,7 @@ CONFIG_MTD_NAND=y CONFIG_MTD_NAND_FSMC=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_BLK_DEV_SD=y CONFIG_ATA=y # CONFIG_SATA_PMP is not set CONFIG_SATA_AHCI_PLATFORM=y
@@ -66,6 +78,7 @@ CONFIG_USB=y # CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_USB_STORAGE=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SPEAR=y
@@ -79,11 +92,14 @@ CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_SECURITY=y CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=y CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_FAT_DEFAULT_IOCHARSET="ascii" CONFIG_TMPFS=y CONFIG_JFFS2_FS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=m
Signature · 1 line
1.7.0.1
PATCH v8 9/9 SPEAr13xx: defconfig: Update
In reply to Mohit KumarEnable PCIe, EABI, VFP and NFS configs in default configuration file for SPEAr13xx.
--- arch/arm/configs/spear13xx_defconfig | 16 ++++++++++++++++ 1 files changed, 16 insertions(+), 0 deletions(-)
arch/arm/configs/spear13xx_defconfig +16 -0
@@ -11,13 +11,24 @@ CONFIG_ARCH_SPEAR13XX=y CONFIG_MACH_SPEAR1310=y CONFIG_MACH_SPEAR1340=y # CONFIG_SWP_EMULATE is not set +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCIE_SPEAR13XX=y CONFIG_SMP=y # CONFIG_SMP_ON_UP is not set # CONFIG_ARM_CPU_TOPOLOGY is not set +CONFIG_AEABI=y CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_VFP=y CONFIG_BINFMT_MISC=y CONFIG_NET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_NET_IPIP=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_OF_PARTS=y
@@ -27,6 +38,7 @@ CONFIG_MTD_NAND=y CONFIG_MTD_NAND_FSMC=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_BLK_DEV_SD=y CONFIG_ATA=y # CONFIG_SATA_PMP is not set CONFIG_SATA_AHCI_PLATFORM=y
@@ -66,6 +78,7 @@ CONFIG_USB=y # CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_USB_STORAGE=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SPEAR=y
@@ -79,11 +92,14 @@ CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_SECURITY=y CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=y CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_FAT_DEFAULT_IOCHARSET="ascii" CONFIG_TMPFS=y CONFIG_JFFS2_FS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=m
Signature · 1 line
1.7.0.1
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Hi Arnd/Bjorn,
Quoted 22 lines · Mohit KUMAR
Hello Arnd,
Quoted 20 lines
-----Original Message-----
From: Mohit KUMAR DCG
Sent: Tuesday, April 15, 2014 5:20 PM
To: spear-devel; [email protected]; [email protected]; [email protected]; [email protected]
Cc: Mohit KUMAR DCG
Subject: [PATCH V8 0/9] PCI: Add SPEAr13xx PCie supportPatch# 1 and 2: Improvement and fixes for SPEAr13xx support. Patch# 3,4 and 6: Add DT bindings for spear1310/40-miphy, misc and pcie node Patch# 5: Add spear1310/40-miphy driver and support for spear1310/40 miphy wrapper.
Patch# 7-9: Add SPEAr13xx PCIe driver and dt support.These pathes are tested with linux-3.15 tag of arm-soc tree. Tested with SPEAr1310 evaluation board with:
- INTEL PRO 100/100 EP card
- USB xhci gen2 card
- Above cards connected through LeCROY PTC switch
Quoted 5 lines
Quoted 2 lines
Modifications for SATA are tested with SPEAr1340-evb board
I think 3.16 windows is about to close, are you planning to merge this series? Pls let me know if something pending on our part.
If you could let us know the status of this patch series inclusion.
Regards
Pratyush
Quoted 91 lines
Regards
MohitQuoted 86 lines
Changes since v7:
- Rebase over for-linus-3.15 tag of arm-soc tree so that complete patch series can be applied cleanly.
- Incorporated few comments on comment style and superfluous comments Changes since v6:
- Split miphy driver for SPEAr1310 and SPEAr1340
- Some cleanup and incorporated other minor comments Changes since v5:
- Split DT bindings for misc, miphy-40lp and pcie node into sepearte patches
- Merge config optionsPCIE_SPEAR13XXandPCI_MSIinto defconfig patch
- Incorporated other minor comments
Changes since v4:
- Uses per device function pointers passed from .data field to theof_device_idinstead ofof_device_is_compatible.
- Incorporated other minor comments from v4Changes since v3:
- Phy driver renamed to phy-miphy40lp
- ahci phy hook patch used as suggested by Arnd
- Incorporated other minor comments from v3Changes since v2:
- Incorporated comments to move SPEAr13xx PCIe and SATA phy specific routines to
the phy framework
- Modify ahci driver to include phy hooks
- phy-core driver modifications forsubsys_initcall()Changes since v1:
- Few patches of the series are already accepted and applied to mainline e.g. pcie designware driver improvements,fixes for IO translation bug, PCIe dw
driver maintainer. So dropped these from v2.
- Incorporated comment to move the common/reset PCIe code to the seperate driver
- PCIe and SATA share common PHY configuration registers, so move SATA platform code to the system config driver Fourth patch is improves pcie designware driver and fixes the IO translation bug. IO translation bug fix leads to the working of PCIe EP devices connected to RC through switch.Mohit Kumar (1):
SPEAr13xx: defconfig: UpdatePratyush Anand (8):
clk: SPEAr13XX: Fix pcie clock name
SPEAr13XX: Fix static mapping table
phy: SPEAr1310/40-miphy: Add binding information
SPEAr: misc: Add binding information
phy: SPEAr1310/40-miphy: Add phy driver for PCIe and SATA
SPEAr13XX: Add binding information for PCIe controller
SPEAr13XX: dts: Add PCIe node information
pcie: SPEAr13xx: Add designware wrapper support.../devicetree/bindings/arm/spear-misc.txt | 9 + .../devicetree/bindings/pci/spear13xx-pcie.txt | 14 + .../devicetree/bindings/phy/st-spear1310-miphy.txt | 12 + .../devicetree/bindings/phy/st-spear1340-miphy.txt | 11 + MAINTAINERS | 6 + arch/arm/boot/dts/spear1310-evb.dts | 4 + arch/arm/boot/dts/spear1310.dtsi | 93 +++++- arch/arm/boot/dts/spear1340-evb.dts | 4 + arch/arm/boot/dts/spear1340.dtsi | 30 ++- arch/arm/boot/dts/spear13xx.dtsi | 9 +- arch/arm/configs/spear13xx_defconfig | 16 + arch/arm/mach-spear/Kconfig | 4 + arch/arm/mach-spear/include/mach/spear.h | 4 +- arch/arm/mach-spear/spear1340.c | 127 +------ arch/arm/mach-spear/spear13xx.c | 2 +- drivers/clk/spear/spear1310_clock.c | 6 +- drivers/clk/spear/spear1340_clock.c | 2 +- drivers/pci/host/Kconfig | 8 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pcie-spear13xx.c | 407 ++++++++++++++++++++ drivers/phy/Kconfig | 12 + drivers/phy/Makefile | 2 + drivers/phy/phy-spear1310-miphy.c | 274 +++++++++++++ drivers/phy/phy-spear1340-miphy.c | 300 ++++++++++++++ 24 files changed, 1218 insertions(+), 139 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt create mode 100644 Documentation/devicetree/bindings/pci/spear13xx- pcie.txt create mode 100644 Documentation/devicetree/bindings/phy/st- spear1310-miphy.txt create mode 100644 Documentation/devicetree/bindings/phy/st- spear1340-miphy.txt create mode 100644 drivers/pci/host/pcie-spear13xx.c create mode 100644
drivers/phy/phy-spear1310-miphy.ccreate mode 100644drivers/phy/phy-spear1340-miphy.c
Hi Arnd,
Any update on status of this patchset? Is it OK for it to go through arm-soc tree or should it be splitted into separate parts which would go through pci/phy/arm-soc trees?
[ The patchset applies fine to next-20140707 after fixing trivial
reject in drivers/pci/host/Makefile in patch #8. To make it build the following line from patch #8 needs to be dropped:
+ spin_lock_init(&pp->conf_lock);
]
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
Quoted 126 lines · Pratyush Anand
Hi Arnd/Bjorn,
Quoted 22 lines · Mohit KUMAR
Hello Arnd,
Quoted 20 lines
-----Original Message-----
From: Mohit KUMAR DCG
Sent: Tuesday, April 15, 2014 5:20 PM
To: spear-devel; [email protected]; [email protected]; [email protected]; [email protected]
Cc: Mohit KUMAR DCG
Subject: [PATCH V8 0/9] PCI: Add SPEAr13xx PCie supportPatch# 1 and 2: Improvement and fixes for SPEAr13xx support. Patch# 3,4 and 6: Add DT bindings for spear1310/40-miphy, misc and pcie node Patch# 5: Add spear1310/40-miphy driver and support for spear1310/40 miphy wrapper.
Patch# 7-9: Add SPEAr13xx PCIe driver and dt support.These pathes are tested with linux-3.15 tag of arm-soc tree. Tested with SPEAr1310 evaluation board with:
- INTEL PRO 100/100 EP card
- USB xhci gen2 card
- Above cards connected through LeCROY PTC switchQuoted 5 lines
Quoted 2 lines
Modifications for SATA are tested with SPEAr1340-evb board
I think 3.16 windows is about to close, are you planning to merge this series? Pls let me know if something pending on our part.
If you could let us know the status of this patch series inclusion.
Regards
PratyushQuoted 90 lines
Regards
MohitQuoted 86 lines
Changes since v7:
- Rebase over for-linus-3.15 tag of arm-soc tree so that complete patch series can be applied cleanly.
- Incorporated few comments on comment style and superfluous comments Changes since v6:
- Split miphy driver for SPEAr1310 and SPEAr1340
- Some cleanup and incorporated other minor comments Changes since v5:
- Split DT bindings for misc, miphy-40lp and pcie node into sepearte patches
- Merge config optionsPCIE_SPEAR13XXandPCI_MSIinto defconfig patch
- Incorporated other minor comments
Changes since v4:
- Uses per device function pointers passed from .data field to theof_device_idinstead ofof_device_is_compatible.
- Incorporated other minor comments from v4Changes since v3:
- Phy driver renamed to phy-miphy40lp
- ahci phy hook patch used as suggested by Arnd
- Incorporated other minor comments from v3Changes since v2:
- Incorporated comments to move SPEAr13xx PCIe and SATA phy specific routines to
the phy framework
- Modify ahci driver to include phy hooks
- phy-core driver modifications forsubsys_initcall()Changes since v1:
- Few patches of the series are already accepted and applied to mainline e.g. pcie designware driver improvements,fixes for IO translation bug, PCIe dw
driver maintainer. So dropped these from v2.
- Incorporated comment to move the common/reset PCIe code to the seperate driver
- PCIe and SATA share common PHY configuration registers, so move SATA platform code to the system config driver Fourth patch is improves pcie designware driver and fixes the IO translation bug. IO translation bug fix leads to the working of PCIe EP devices connected to RC through switch.Mohit Kumar (1):
SPEAr13xx: defconfig: UpdatePratyush Anand (8):
clk: SPEAr13XX: Fix pcie clock name
SPEAr13XX: Fix static mapping table
phy: SPEAr1310/40-miphy: Add binding information
SPEAr: misc: Add binding information
phy: SPEAr1310/40-miphy: Add phy driver for PCIe and SATA
SPEAr13XX: Add binding information for PCIe controller
SPEAr13XX: dts: Add PCIe node information
pcie: SPEAr13xx: Add designware wrapper support.../devicetree/bindings/arm/spear-misc.txt | 9 + .../devicetree/bindings/pci/spear13xx-pcie.txt | 14 + .../devicetree/bindings/phy/st-spear1310-miphy.txt | 12 + .../devicetree/bindings/phy/st-spear1340-miphy.txt | 11 + MAINTAINERS | 6 + arch/arm/boot/dts/spear1310-evb.dts | 4 + arch/arm/boot/dts/spear1310.dtsi | 93 +++++- arch/arm/boot/dts/spear1340-evb.dts | 4 + arch/arm/boot/dts/spear1340.dtsi | 30 ++- arch/arm/boot/dts/spear13xx.dtsi | 9 +- arch/arm/configs/spear13xx_defconfig | 16 + arch/arm/mach-spear/Kconfig | 4 + arch/arm/mach-spear/include/mach/spear.h | 4 +- arch/arm/mach-spear/spear1340.c | 127 +------ arch/arm/mach-spear/spear13xx.c | 2 +- drivers/clk/spear/spear1310_clock.c | 6 +- drivers/clk/spear/spear1340_clock.c | 2 +- drivers/pci/host/Kconfig | 8 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pcie-spear13xx.c | 407 ++++++++++++++++++++ drivers/phy/Kconfig | 12 + drivers/phy/Makefile | 2 + drivers/phy/phy-spear1310-miphy.c | 274 +++++++++++++ drivers/phy/phy-spear1340-miphy.c | 300 ++++++++++++++ 24 files changed, 1218 insertions(+), 139 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt create mode 100644 Documentation/devicetree/bindings/pci/spear13xx- pcie.txt create mode 100644 Documentation/devicetree/bindings/phy/st- spear1310-miphy.txt create mode 100644 Documentation/devicetree/bindings/phy/st- spear1340-miphy.txt create mode 100644 drivers/pci/host/pcie-spear13xx.c create mode 100644
drivers/phy/phy-spear1310-miphy.ccreate mode 100644drivers/phy/phy-spear1340-miphy.c
Hello Bartlomiej,
Quoted 11 lines
-----Original Message-----
From: Bartlomiej Zolnierkiewicz [mailto:[email protected]]
Sent: Monday, July 07, 2014 9:01 PM
To: Pratyush ANAND
Cc: Arnd Bergmann ([email protected]); 'Bjorn Helgaas' ([email protected]); Mohit KUMAR DCG; spear-devel; linux- [email protected]; [email protected]; linux- [email protected]; Mark Nicholson
Subject: Re: [PATCH V8 0/9] PCI: Add SPEAr13xx PCie support
Quoted 5 lines
Hi Arnd,
Any update on status of this patchset? Is it OK for it to go through arm-soc tree or should it be splitted into separate parts which would go through pci/phy/arm-soc trees?
- These patches are rebased over 3-16-rc3 to go through arm-soc tree. Somehow we are having 'sync' issue in providing web link for spear public repository with these patches.
It will be resolve soon, and I will provide the link.
Quoted 6 lines
[ The patchset applies fine to next-20140707 after fixing trivial
reject indrivers/pci/host/Makefilein patch #8. To make it build the following line from patch #8 needs to be dropped:+
spin_lock_init(&pp->conf_lock);
- yes, I have already considered this while rebasing.
Thanks
Mohit
Quoted 143 lines
]
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung ElectronicsQuoted 30 lines · Pratyush Anand
Hi Arnd/Bjorn,
Quoted 27 lines · Mohit KUMAR
Hello Arnd,
Quoted 15 lines
-----Original Message-----
From: Mohit KUMAR DCG
Sent: Tuesday, April 15, 2014 5:20 PM
To: spear-devel; [email protected]; [email protected]; [email protected]; [email protected]
Cc: Mohit KUMAR DCG
Subject: [PATCH V8 0/9] PCI: Add SPEAr13xx PCie supportPatch# 1 and 2: Improvement and fixes for SPEAr13xx support. Patch# 3,4 and 6: Add DT bindings for spear1310/40-miphy, misc and pcie node Patch# 5: Add spear1310/40-miphy driver and support for spear1310/40 miphy wrapper.
Patch# 7-9: Add SPEAr13xx PCIe driver and dt support.Quoted 8 lines
These pathes are tested with linux-3.15 tag of arm-soc tree. Tested with SPEAr1310 evaluation board with:
- INTEL PRO 100/100 EP card
- USB xhci gen2 card
- Above cards connected through LeCROY PTC switchModifications for SATA are tested with SPEAr1340-evb board
I think 3.16 windows is about to close, are you planning to merge this
series?
Quoted 18 lines
Quoted 1 line
Pls let me know if something pending on our part.
If you could let us know the status of this patch series inclusion.
Regards
PratyushQuoted 11 lines
Regards
MohitQuoted 7 lines
Changes since v7:
- Rebase over for-linus-3.15 tag of arm-soc tree so that complete patch series can be applied cleanly.
- Incorporated few comments on comment style and superfluous comments Changes since v6:
- Split miphy driver for SPEAr1310 and SPEAr1340
- Some cleanup and incorporated other minor comments Changes sincev5:
Quoted 21 lines
Quoted 21 lines
Quoted 21 lines
- Split DT bindings for misc, miphy-40lp and pcie node into sepearte patches
- Merge config optionsPCIE_SPEAR13XXandPCI_MSIinto defconfig patch
- Incorporated other minor comments Changes since v4:
- Uses per device function pointers passed from .data field to theof_device_idinstead ofof_device_is_compatible.
- Incorporated other minor comments from v4Changes since v3:
- Phy driver renamed to phy-miphy40lp
- ahci phy hook patch used as suggested by Arnd
- Incorporated other minor comments from v3Changes since v2:
- Incorporated comments to move SPEAr13xx PCIe and SATA phy specific routines to
the phy framework
- Modify ahci driver to include phy hooks
- phy-core driver modifications forsubsys_initcall()Quoted 2 lines
Quoted 2 lines
Quoted 2 lines
Changes since v1:
- Few patches of the series are already accepted and applied tomainline e.g.
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
pcie designware driver improvements,fixes for IO translation bug,
PCIe dw driver maintainer. So dropped these from v2.
- Incorporated comment to move the common/reset PCIe code to the seperate driver
- PCIe and SATA share common PHY configuration registers, so move SATA platform code to the system config driver Fourth patch is improves pcie designware driver and fixes the IO translation bug. IO translation bug fix leads to the working of PCIe EP devices connectedto RC through switch.
Quoted 26 lines
Quoted 26 lines
Quoted 26 lines
Mohit Kumar (1):
SPEAr13xx: defconfig: UpdatePratyush Anand (8):
clk: SPEAr13XX: Fix pcie clock name
SPEAr13XX: Fix static mapping table
phy: SPEAr1310/40-miphy: Add binding information
SPEAr: misc: Add binding information
phy: SPEAr1310/40-miphy: Add phy driver for PCIe and SATA
SPEAr13XX: Add binding information for PCIe controller
SPEAr13XX: dts: Add PCIe node information
pcie: SPEAr13xx: Add designware wrapper support.../devicetree/bindings/arm/spear-misc.txt | 9 + .../devicetree/bindings/pci/spear13xx-pcie.txt | 14 + .../devicetree/bindings/phy/st-spear1310-miphy.txt | 12 + .../devicetree/bindings/phy/st-spear1340-miphy.txt | 11 + MAINTAINERS | 6 + arch/arm/boot/dts/spear1310-evb.dts | 4 + arch/arm/boot/dts/spear1310.dtsi | 93 +++++- arch/arm/boot/dts/spear1340-evb.dts | 4 + arch/arm/boot/dts/spear1340.dtsi | 30 ++- arch/arm/boot/dts/spear13xx.dtsi | 9 +- arch/arm/configs/spear13xx_defconfig | 16 + arch/arm/mach-spear/Kconfig | 4 +Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
arch/arm/mach-spear/include/mach/spear.h | 4 +- arch/arm/mach-spear/spear1340.c | 127 +------ arch/arm/mach-spear/spear13xx.c | 2 +- drivers/clk/spear/spear1310_clock.c | 6 +- drivers/clk/spear/spear1340_clock.c | 2 +- drivers/pci/host/Kconfig | 8 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pcie-spear13xx.c | 407++++++++++++++++++++
Quoted 16 lines
Quoted 16 lines
Quoted 16 lines
drivers/phy/Kconfig | 12 + drivers/phy/Makefile | 2 + drivers/phy/phy-spear1310-miphy.c | 274 +++++++++++++ drivers/phy/phy-spear1340-miphy.c | 300 ++++++++++++++ 24 files changed, 1218 insertions(+), 139 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt create mode 100644 Documentation/devicetree/bindings/pci/spear13xx- pcie.txt create mode 100644 Documentation/devicetree/bindings/phy/st- spear1310-miphy.txt create mode 100644 Documentation/devicetree/bindings/phy/st- spear1340-miphy.txt create mode 100644 drivers/pci/host/pcie-spear13xx.c create mode100644
drivers/phy/phy-spear1310-miphy.ccreate mode 100644drivers/phy/phy-spear1340-miphy.c
Quoted 5 lines · Mohit KUMAR DCG
- These patches are rebased over 3-16-rc3 to go through arm-soc tree. Somehow we are having 'sync' issue in providing web link for spear public repository with these patches.
It will be resolve soon, and I will provide the link.
I can push these to some Linaro repo of mine if you want. And you can send a pull request from there then.
Hello Viresh,
Quoted 13 lines
-----Original Message-----
From: [email protected] [mailto:[email protected]] On Behalf Of Viresh Kumar
Sent: Tuesday, July 08, 2014 9:59 AM
To: Mohit KUMAR DCG
Cc: Bartlomiej Zolnierkiewicz; Pratyush ANAND; Arnd Bergmann
([email protected]); 'Bjorn Helgaas' ([email protected]); spear-devel; [email protected]; [email protected]; linux- [email protected]; Mark Nicholson
Subject: Re: [PATCH V8 0/9] PCI: Add SPEAr13xx PCie supportOn Tue, Jul 8, 2014 at 9:21 AM, Mohit KUMAR DCG <[email protected]> wrote:
Quoted 8 lines
Quoted 5 lines
- These patches are rebased over 3-16-rc3 to go through arm-soc tree. Somehow we are having 'sync' issue in providing web link for spear public repository with these patches.
It will be resolve soon, and I will provide the link.
I can push these to some Linaro repo of mine if you want. And you can send a pull request from there then.
Pls find attached patches to push through your repo. These are rebased over the top
of 3.16-rc3.
Thanks
Mohit
Quoted 2 lines · Mohit KUMAR DCG
Pls find attached patches to push through your repo. These are rebased over the top
of 3.16-rc3.
git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/linux.git
spear/pcie-support-v8
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Quoted 6 lines · Viresh Kumar
Quoted 2 lines · Mohit KUMAR DCG
Pls find attached patches to push through your repo. These are rebased over the top
of 3.16-rc3.
git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/linux.git
spear/pcie-support-v8
I'm currently at the Linaro sprint in Le Mans, so Olof is doing all the arm-soc merges. Mohit or Pratyush, please send a formal pull request (using "git request-pull") to [email protected] with Cc to everyone on Cc here so Olof can pick it up.
Please also include a description of the overall series and the reasons why we decided to merge it through arm-soc in the pull request email. Thanks!
Arnd