QCOM 8074 cpuidle driver
Subsystems (4)
v5 cover QCOM 8074 cpuidle driver
Changes since v4:
[ https://www.mail-archive.com/linux-arm-msm at vger.kernel.org/msg10327.html ]
- Update to the v8 of ARM generic idle states patches
- Use platform device model for cpuidle-qcom
- Clean up msm-pm.c to remove unnecessary include files and functions
- Update commit text and documentation for all idle states
- Remove scm-boot relocate patch from this series, submitted earlier [ https://www.mail-archive.com/linux-arm-msm at vger.kernel.org/msg10518.html ]
Changes since v3:
[ https://www.mail-archive.com/linux-arm-msm at vger.kernel.org/msg10288.html ]
- Fix CONFIG_QCOM_PM Kconfig as bool
- More clean ups in spm.c and spm-devices.c
- Removed and re-organized data structures to make initialization simple
- Remove export of sequence flush functions
- Updated commit text
- Comments for use of barriers.
- Rebase on top of 3.17-rc1
Changes since v2:
[ https://www.mail-archive.com/linux-arm-msm at vger.kernel.org/msg10148.html ]
- Prune all the drivers to support basic WFI and power down cpuidle functionality. Remove debug code.
- Integrate KConfig changes into the drivers' patches.
- Use Lorenzo's ARM idle-states patches as the basis for reading cpuidle c-states from DT.
[ http://marc.info/?l=linux-pm&m=140794514812383&w=2 ]
- Incorporate review comments
- Rebase on top of 3.16
Changes since v1/RFC:
[ https://www.mail-archive.com/linux-arm-msm at vger.kernel.org/msg10065.html ]
- Remove hotplug from the patch series. Will submit it separately.
- Fix SPM drivers per the review comments
- Modify patch sequence to compile SPM drivers independent of msm-pm, so as to allow wfi() calls to use SPM even without SoC interface driver.
8074 like any ARM SoC can do architectural clock gating, that helps save on power, but not enough of leakage power. Leakage power of the SoC can be further reduced by turning off power to the core. To aid this, every core (cpu and L2) is accompanied by a Sub-system Power Manager (SPM), that can be configured to indicate the low power mode, the core would be put into and the SPM programs the peripheral h/w accordingly to enter low power and turn off the power rail to the core.
The idle invocation hierarchy -
CPUIDLE
|
cpuidle-qcom.c [CPUIdle driver]
|
------> msm-pm.c [SoC Interface layer for QCOM chipsets]
|
------> spm-devices.c [SPM devices manager]
| |
| ------> spm.c [SPM h/w driver]
|
------> scm-boot.c [SCM interface layer]
|
------------------------|--------------------------
(EL) Secure Monitor Code
|
|
wfi();
------------------------|--------------------------
(HW) [CPU] {clock gate}
|
-----> [SPM] {statemachine}The patchset does the following -
- Add new Secure Monitor flags to support warmboot of a quad core system.
- Introduce the SPM driver to control power to the core. The SPM h/w IP works in conjunction with the Krait CPU/L2. When the core executes WFI instruction, the core is clockgated and the SPM state machine takes over and powers the core down. An interrupt from GIC, resumes the SPM state machine which brings the cpu out of the low power mode.
- Add a SPM device manager to configure multiple SPM devices.
- Add the device tree configuration for each of the SPM nodes. There is one for each cpu. There is one for each cpu.
- Introduce the SoC driver interface layer to configure SPM per the core's idle state. To power down the cpu core, the SPM h/w needs to be set up correctly
to power down the core, when the core executes WFI. Linux is expected to call into Secure Monitor to power down the core. At reset, the core will start in seure mode and will be returned back to Linux.
- Add CPUIDLE driver for QCOM cpus. The cpuidle driver uses the SoC interface layer to configure the SPM to allow Krait to be powered down. The cpuidle driver is based on ARM idle-state framework for cpuidle drivers.
- Provide device configuration for 8074 SoC. Current support is for WFI and standalone power collapse, which powers only the core independent of the other cores and caches.
Thanks,
Lina
Lina Iyer (7):
msm: scm: Add SCM warmboot flags for quad core targets.
qcom: spm: Add Subsystem Power Manager driver (SAW2)
qcom: spm-devices: Add SPM device manager for the SoC
arm: dts: qcom: Add SPM device bindings for 8974
qcom: msm-pm: Add cpu low power mode functions
qcom: cpuidle: Add cpuidle driver for QCOM cpus
arm: dts: qcom: Add idle states device nodes for 8974
.../bindings/arm/msm/qcom,idle-state.txt | 72 ++++++++ Documentation/devicetree/bindings/arm/msm/spm.txt | 47 +++++ arch/arm/boot/dts/qcom-msm8974-pm.dtsi | 69 +++++++ arch/arm/boot/dts/qcom-msm8974.dtsi | 30 +++- drivers/cpuidle/Kconfig.arm | 7 + drivers/cpuidle/Makefile | 1 + drivers/cpuidle/cpuidle-qcom.c | 87 +++++++++ drivers/soc/qcom/Kconfig | 8 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/msm-pm.c | 106 +++++++++++ drivers/soc/qcom/spm-devices.c | 198 +++++++++++++++++++++ drivers/soc/qcom/spm-drv.h | 69 +++++++ drivers/soc/qcom/spm.c | 192 ++++++++++++++++++++ include/soc/qcom/pm.h | 31 ++++ include/soc/qcom/scm-boot.h | 2 + include/soc/qcom/spm.h | 38 ++++ 16 files changed, 954 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt create mode 100644 Documentation/devicetree/bindings/arm/msm/spm.txt create mode 100644 arch/arm/boot/dts/qcom-msm8974-pm.dtsi create mode 100644 drivers/cpuidle/cpuidle-qcom.c create mode 100644 drivers/soc/qcom/msm-pm.c create mode 100644 drivers/soc/qcom/spm-devices.c create mode 100644 drivers/soc/qcom/spm-drv.h create mode 100644 drivers/soc/qcom/spm.c create mode 100644 include/soc/qcom/pm.h create mode 100644 include/soc/qcom/spm.h
Signature · 1 line
1.9.1
PATCH v5 1/7 msm: scm: Add SCM warmboot flags for quad core targets.
Quad core targets like APQ8074, APQ8064, APQ8084 need SCM support set up warm boot addresses in the Secure Monitor. Extend the SCM flags to support warmboot addresses for secondary cores.
--- include/soc/qcom/scm-boot.h | 2 ++ 1 file changed, 2 insertions(+)
include/soc/qcom/scm-boot.h +2 -0
@@ -18,6 +18,8 @@#define SCM_FLAG_COLDBOOT_CPU3 0x20#define SCM_FLAG_WARMBOOT_CPU0 0x04#define SCM_FLAG_WARMBOOT_CPU1 0x02 +#define SCM_FLAG_WARMBOOT_CPU2 0x10 +#define SCM_FLAG_WARMBOOT_CPU3 0x40int scm_set_boot_addr (phys_addr_t addr,int flags);
Signature · 1 line
1.9.1
PATCH v5 2/7 qcom: spm: Add Subsystem Power Manager driver (SAW2)
In reply to Lina IyerBased on work by many authors, available at codeaurora.org
SPM is a hardware block that controls the peripheral logic surrounding the application cores (cpu/l$). When the core executes WFI instruction, the SPM takes over the putting the core in low power state as configured. The wake up for the SPM is an interrupt at the GIC, which then completes the rest of low power mode sequence and brings the core out of low power mode.
The SPM has a set of control registers that configure the SPMs individually based on the type of the core and the runtime conditions. SPM is a finite state machine block to which a sequence is provided and it interprets the bytes and executes them in sequence. Each low power mode that the core can enter into is provided to the SPM as a sequence.
Configure the SPM to set the core (cpu or L2) into its low power mode, the index of the first command in the sequence is set in the SPM_CTL register. When the core executes ARM wfi instruction, it triggers the SPM state machine to start executing from that index. The SPM state machine waits until the interrupt occurs and starts executing the rest of the sequence until it hits the end of the sequence. The end of the sequence jumps the core out of its low power mode.
[lina: simplify the driver for initial submission, clean up and update commit text]
--- drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/spm-drv.h | 69 ++++++++++++++++ drivers/soc/qcom/spm.c | 192 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 262 insertions(+) create mode 100644 drivers/soc/qcom/spm-drv.h create mode 100644 drivers/soc/qcom/spm.c
drivers/soc/qcom/Makefile +1 -0
@@ -1,3 +1,4 @@ obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o +obj-$(CONFIG_QCOM_PM) += spm.o CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1) obj-$(CONFIG_QCOM_SCM) += scm.o scm-boot.o
drivers/soc/qcom/spm-drv.h new file +69 -0
69 lines not on this page · raw message
drivers/soc/qcom/spm.c new file +192 -0
192 lines not on this page · raw message
Signature · 1 line
1.9.1
PATCH v5 2/7 qcom: spm: Add Subsystem Power Manager driver (SAW2)
Hi Lina,
drivers/soc/qcom/Makefile line 2
Quoted 12 lines · Lina Iyer
drivers/soc/qcom/spm.c | 192 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 262 insertions(+) create mode 100644 drivers/soc/qcom/spm-drv.h create mode 100644 drivers/soc/qcom/spm.cdrivers/soc/qcom/Makefile +1
-0@@ -1,3 +1,4 @@ obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o +obj-$(CONFIG_QCOM_PM) += spm.o
CONFIG_QCOM_PM is missing in Kconfig hence this driver wont build. I see it is added in patch #3. Please move it to this patch so that this driver builds.
drivers/soc/qcom/spm-drv.h
Quoted 5 lines
drivers/soc/qcom/Makefile +0
-0CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1) obj-$(CONFIG_QCOM_SCM) += scm.o scm-boot.odrivers/soc/qcom/spm-drv.h new file +0
-0
Thanks
Pramod
PATCH v5 3/7 qcom: spm-devices: Add SPM device manager for the SoC
In reply to Lina IyerBased on work by many authors, available at codeaurora.org
Each cpu or an L2$ has an SPM device. They are identical instances of the same SPM block. This allows for multiple instances be grouped and managed collectively. spm-devices.c is the SPM device manager managing multiple SPM devices on top of the driver layer.
Device configuration of each SPM is picked up from the DTS. The hardware configuration of each of the SPM is handled by the driver (spm.c).
[lina: simplify the driver for initial submission, clean up and update commit text]
--- Documentation/devicetree/bindings/arm/msm/spm.txt | 47 +++++ drivers/soc/qcom/Kconfig | 8 + drivers/soc/qcom/Makefile | 2 +- drivers/soc/qcom/spm-devices.c | 198 ++++++++++++++++++++++ include/soc/qcom/spm.h | 38 +++++ 5 files changed, 292 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/arm/msm/spm.txt create mode 100644 drivers/soc/qcom/spm-devices.c create mode 100644 include/soc/qcom/spm.h
Documentation/devicetree/bindings/arm/msm/spm.txt new file +47 -0
@@ -0,0 +1,47 @@ +* Subsystem Power Manager (SAW2) + +S4 generation of MSMs have SPM hardware blocks to control the Application +Processor Sub-System power. These SPM blocks run individual state machine +to determine what the core (L2 or Krait/Scorpion) would do when the WFI +instruction is executed by the core. + +The devicetree representation of the SPM block should be: + +Required properties + +- compatible: Could be one of - + "qcom,spm-v2.1" +- reg: The physical address and the size of the SPM's memory mapped registers +- qcom,cpu: phandle for the CPU that the SPM block is attached to. + This field is required on only for SPMs that control the CPU. +- qcom,saw2-clk-div: SAW2 configuration register to program the SPM runtime + clocks. +- qcom,saw2-delays: The SPM delay values that SPM sequences would refer to. +- qcom,saw2-enable: The SPM control register to enable/disable the sleep state + machine. + +Optional properties + +- qcom,saw2-spm-cmd-wfi: The WFI command sequence +- qcom,saw2-spm-cmd-ret: The Retention command sequence +- qcom,saw2-spm-cmd-spc: The Standalone PC command sequence +- qcom,saw2-spm-cmd-pc: The Power Collapse command sequence. This sequence may + turn off other SoC components. +- qcom,saw2-spm-cmd-gdhs: GDHS (Globally Distributed Head Switch) command + sequence. This sequence will retain the memory but turn off the logic. +- +Example: + spm at f9089000 { + compatible = "qcom,spm-v2.1"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9089000 0x1000>; + qcom,cpu = <&CPU0>; + qcom,saw2-clk-div = <0x1>; + qcom,saw2-delays = <0x20000400>; + qcom,saw2-enable = <0x1>; + qcom,saw2-spm-cmd-wfi = [03 0b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 50 80 60 70 10 92 + a0 b0 03 68 70 3b 92 a0 b0 + 82 2b 50 10 30 02 22 30 0f]; + };
drivers/soc/qcom/Kconfig +8 -0
@@ -11,3 +11,11 @@ config QCOM_GSBI config QCOM_SCM bool + +config QCOM_PM + bool "Qualcomm Power Management" + depends on PM && ARCH_QCOM + help + QCOM Platform specific power driver to manage cores and L2 low power + modes. It interface with various system drivers to put the cores in + low power modes.
drivers/soc/qcom/Makefile +1 -1
@@ -1,4 +1,4 @@ obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o -obj-$(CONFIG_QCOM_PM) += spm.o +obj-$(CONFIG_QCOM_PM) += spm.o spm-devices.o CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1) obj-$(CONFIG_QCOM_SCM) += scm.o scm-boot.o
drivers/soc/qcom/spm-devices.c new file +198 -0
198 lines not on this page · raw message
include/soc/qcom/spm.h new file +38 -0
@@ -0,0 +1,38 @@ +/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 and +* only version 2 as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef __QCOM_SPM_H +#define __QCOM_SPM_H + +enum { +MSM_SPM_MODE_DISABLED , +MSM_SPM_MODE_CLOCK_GATING , +MSM_SPM_MODE_RETENTION , +MSM_SPM_MODE_GDHS , +MSM_SPM_MODE_POWER_COLLAPSE , +MSM_SPM_MODE_NR +}; + +struct msm_spm_device ; + +#if defined(CONFIG_QCOM_PM ) + +int msm_spm_set_low_power_mode (u32 mode); + +#else + +static inline int msm_spm_set_low_power_mode (u32 mode) +{return -ENOSYS ; } + +#endif /* CONFIG_QCOM_PM */ + +#endif /* __QCOM_SPM_H */
Signature · 1 line
1.9.1
PATCH v5 4/7 arm: dts: qcom: Add SPM device bindings for 8974
In reply to Lina IyerAdd SPM device bindings for QCOM 8974 based cpus. SPM is the sub-system power manager and controls the logic around the cores (cpu and L2).
Each core has an instance of SPM and controls only that core. Each cpu SPM is configured to support WFI and SPC (standalone-power collapse).
--- arch/arm/boot/dts/qcom-msm8974-pm.dtsi | 69 ++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/qcom-msm8974.dtsi | 10 +++-- 2 files changed, 75 insertions(+), 4 deletions(-) create mode 100644 arch/arm/boot/dts/qcom-msm8974-pm.dtsi
arch/arm/boot/dts/qcom-msm8974-pm.dtsi new file +69 -0
@@ -0,0 +1,69 @@ +/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + spm at f9089000 { + compatible = "qcom,spm-v2.1"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9089000 0x1000>; + qcom,cpu = <&CPU0>; + qcom,saw2-clk-div = <0x01>; + qcom,saw2-delays = <0x3C102800>; + qcom,saw2-enable = <0x01>; + qcom,saw2-spm-cmd-wfi = [03 0b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 80 10 E8 5B 03 3B E8 5B 82 10 0B + 30 06 26 30 0F]; + }; + + spm at f9099000 { + compatible = "qcom,spm-v2.1"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9099000 0x1000>; + qcom,cpu = <&CPU1>; + qcom,saw2-clk-div = <0x01>; + qcom,saw2-delays = <0x3C102800>; + qcom,saw2-enable = <0x01>; + qcom,saw2-spm-cmd-wfi = [03 0b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 80 10 E8 5B 03 3B E8 5B 82 10 0B + 30 06 26 30 0F]; + }; + + spm at f90a9000 { + compatible = "qcom,spm-v2.1"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf90a9000 0x1000>; + qcom,cpu = <&CPU2>; + qcom,saw2-clk-div = <0x01>; + qcom,saw2-delays = <0x3C102800>; + qcom,saw2-enable = <0x01>; + qcom,saw2-spm-cmd-wfi = [03 0b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 80 10 E8 5B 03 3B E8 5B 82 10 0B + 30 06 26 30 0F]; + }; + + spm at f90b9000 { + compatible = "qcom,spm-v2.1"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf90b9000 0x1000>; + qcom,cpu = <&CPU3>; + qcom,saw2-clk-div = <0x01>; + qcom,saw2-delays = <0x3C102800>; + qcom,saw2-enable = <0x01>; + qcom,saw2-spm-cmd-wfi = [03 0b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 80 10 E8 5B 03 3B E8 5B 82 10 0B + 30 06 26 30 0F]; + }; +};
arch/arm/boot/dts/qcom-msm8974.dtsi +6 -4
@@ -14,7 +14,7 @@ #size-cells = <0>; interrupts = <1 9 0xf04>; - cpu at 0 { + CPU0: cpu at 0 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu";
@@ -23,7 +23,7 @@ qcom,acc = <&acc0>; }; - cpu at 1 { + CPU1: cpu at 1 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu";
@@ -32,7 +32,7 @@ qcom,acc = <&acc1>; }; - cpu at 2 { + CPU2: cpu at 2 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu";
@@ -41,7 +41,7 @@ qcom,acc = <&acc2>; }; - cpu at 3 { + CPU3: cpu at 3 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu";
@@ -238,3 +238,5 @@ }; }; }; + +#include "qcom-msm8974-pm.dtsi"
Signature · 1 line
1.9.1
PATCH v5 5/7 qcom: msm-pm: Add cpu low power mode functions
In reply to Lina IyerBased on work by many authors, available at codeaurora.org
Add interface layer to abstract and handle hardware specific functionality for executing various cpu low power modes in QCOM chipsets.
QCOM cpus support multiple low power modes. The C-States are defined as -
* WFI (clock gating)
* Retention (clock gating at lower power)
* Standalone Power Collapse (Standalone PC or SPC) - The power to the cpu is lost and the cpu warmboots.
* Power Collapse (PC) - Same as SPC, but is a cognizant of the fact that the SoC may do deeper sleep modes.
[lina: simplify the driver for an initial submission, add commit text description of idle states]
--- drivers/soc/qcom/Makefile | 2 +- drivers/soc/qcom/msm-pm.c | 106 ++++++++++++++++++++++++++++++++++++++++++++++ include/soc/qcom/pm.h | 31 ++++++++++++++ 3 files changed, 138 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/qcom/msm-pm.c create mode 100644 include/soc/qcom/pm.h
drivers/soc/qcom/Makefile +1 -1
@@ -1,4 +1,4 @@ obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o -obj-$(CONFIG_QCOM_PM) += spm.o spm-devices.o +obj-$(CONFIG_QCOM_PM) += spm.o spm-devices.o msm-pm.o CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1) obj-$(CONFIG_QCOM_SCM) += scm.o scm-boot.o
drivers/soc/qcom/msm-pm.c new file +106 -0
106 lines not on this page · raw message
include/soc/qcom/pm.h new file +31 -0
@@ -0,0 +1,31 @@ +/* +* Copyright (c) 2009-2014, The Linux Foundation. All rights reserved. +* +* This software is licensed under the terms of the GNU General Public +* License version 2, as published by the Free Software Foundation, and +* may be copied, distributed, and modified under those terms. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +#ifndef __QCOM_PM_H +#define __QCOM_PM_H + +enum msm_pm_sleep_mode { +MSM_PM_SLEEP_MODE_WFI , +MSM_PM_SLEEP_MODE_RET , +MSM_PM_SLEEP_MODE_SPC , +MSM_PM_SLEEP_MODE_PC , +MSM_PM_SLEEP_MODE_NR , +}; + +enum msm_pm_l2_scm_flag { +MSM_SCM_L2_ON =0 , +MSM_SCM_L2_OFF =1 +}; + +#endif /* __QCOM_PM_H */
Signature · 1 line
1.9.1
PATCH v5 6/7 qcom: cpuidle: Add cpuidle driver for QCOM cpus
In reply to Lina IyerAdd cpuidle driver interface to allow cpus to go into C-States. Use the cpuidle DT interface common across ARM architectures to provide the C-State information to the cpuidle framework.
Supported modes at this time are clock gating (wfi) and cpu power down (Standalone PC or spc).
--- .../bindings/arm/msm/qcom,idle-state.txt | 72 ++++++++++++++++++ drivers/cpuidle/Kconfig.arm | 7 ++ drivers/cpuidle/Makefile | 1 + drivers/cpuidle/cpuidle-qcom.c | 87 ++++++++++++++++++++++ 4 files changed, 167 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt create mode 100644 drivers/cpuidle/cpuidle-qcom.c
Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt new file +72 -0
@@ -0,0 +1,72 @@ +QCOM Idle States for cpuidle driver + +ARM provides idle-state node to define the cpuidle states, as defined in [1]. +cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle +states. Idle states have different enter/exit latency and residency values. +The idle states supported by the QCOM SoC are defined as - + + * WFI + * Retention + * Standalone Power Collapse (Standalone PC or SPC) + * Power Collapse (PC) + +WFI: WFI does a little more in addition to architectural clock gating. ARM +processors when execute the wfi instruction will gate their internal clocks. +QCOM cpus use this instruction as a trigger for the SPM state machine. Usually +with a cpu entering WFI, the SPM is configured to do clock-gating as well. The +SPM state machine waits for the interrrupt to trigger the core back in to +active. When all CPUs in the SoC, clock gate using the ARM wfi instruction, the +second level cache usually can also clock gate sensing no cpu activity. When a +cpu is ready to run, it needs the cache to be active before starting execution. +Allowing the SPM to execute the clock gating statemachine and waiting for +interrupt on behalf of the processor has a benefit of guaranteeing that the +system state is conducive for the core to resume execution. + +Retention: Retention is a low power state where the core is clockgated and the +memory and the registers associated with the core are retained. The voltage +may be reduced to the minimum value needed to keep the processor registers +active. Retention is triggered when the core executes wfi instruction. The SPM +should be configured to execute the retention sequence and would wait for +interrupt, before restoring the cpu to execution state. Retention may have a +slightly higher latency than WFI. + +Standalone PC: A cpu can power down and warmboot if there is a sufficient time +between now and the next know wake up. SPC mode is used to indicate a core +entering a power down state without consulting any other cpu or the system +resources. This helps save power only on that core. Like WFI and Retention, the +core executes wfi and the SPM programmed to do SPC would use the cpu control +logic to power down the core's supply and restore it back when woken up by an +interrupt. Applying power and reseting the core causes the core to warmboot +back into secure mode which trampolines the control back to the kernel. To +enter a power down state the kernel needs to call into the secure layer which +would then execute the ARM wfi instruction. Failing to do so, would result in a +crash enforced by the warm boot code in the secure layer. On a SoC with +write-back L1 cache, the cache would need to be flushed. + +Power Collapse: This state is similiar to the SPC mode, but distinguishes +itself in the fact that the cpu acknowledges and permits the SoC to enter +deeper sleep modes. In a hierarchical power domain SoC, this means L2 and other +caches can be flushed, system bus, clocks - lowered, and SoC main XO turned off +and voltages reduced, provided all cpus enter this state. In other words, it is +a coupled idle state. Since the span of low power modes possible at this state +is vast, the exit latency and the residency of this low power mode would be +considered high even though at a cpu level, this essentially is cpu power down. +The SPM in this state also may handshake with the Resource power manager +processor in the SoC to indicate a complete subsystem shut down. + +The idle-state for QCOM SoCs are distinguished by the compatible property of +the node. They indicate to the cpuidle driver the entry point to use for +cpuidle. The devicetree representation of the idle state should be - + +Required properties: + +- compatible: Must be "arm,idle-state" + and one of - + "qcom,idle-state-wfi", + "qcom,idle-state-ret", + "qcom,idle-state-spc", + "qcom,idle-state-pc", + +Other required and optional properties are specified in [1]. + +[1]. Documentation/devicetree/bindings/arm/idle-states.txt
drivers/cpuidle/Kconfig.arm +7 -0
@@ -62,3 +62,10 @@ config ARM_MVEBU_V7_CPUIDLE depends on ARCH_MVEBU help Select this to enable cpuidle on Armada 370, 38x and XP processors. + +config ARM_QCOM_CPUIDLE + bool "CPU Idle drivers for Qualcomm processors" + depends on QCOM_PM + select DT_IDLE_STATES + help + Select this to enable cpuidle for QCOM processors
drivers/cpuidle/Makefile +1 -0
@@ -17,6 +17,7 @@ obj-$(CONFIG_ARM_ZYNQ_CPUIDLE) += cpuidle-zynq.o obj-$(CONFIG_ARM_U8500_CPUIDLE) += cpuidle-ux500.o obj-$(CONFIG_ARM_AT91_CPUIDLE) += cpuidle-at91.o obj-$(CONFIG_ARM_EXYNOS_CPUIDLE) += cpuidle-exynos.o +obj-$(CONFIG_ARM_QCOM_CPUIDLE) += cpuidle-qcom.o ############################################################################### # MIPS drivers
drivers/cpuidle/cpuidle-qcom.c new file +87 -0
87 lines not on this page · raw message
Signature · 1 line
1.9.1
PATCH v5 7/7 arm: dts: qcom: Add idle states device nodes for 8974
In reply to Lina IyerAdd allowable C-States for each cpu using the cpu-idle-states node. ARM spec dictates WFI as the default idle state at 0. Support standalone power collapse (power down that does not affect any SoC idle states) for each cpu.
--- arch/arm/boot/dts/qcom-msm8974.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
arch/arm/boot/dts/qcom-msm8974.dtsi +20 -0
@@ -21,6 +21,7 @@ reg = <0>; next-level-cache = <&L2>; qcom,acc = <&acc0>; + cpu-idle-states = <&CPU_WFI &CPU_SPC>; }; CPU1: cpu at 1 {
@@ -30,6 +31,7 @@ reg = <1>; next-level-cache = <&L2>; qcom,acc = <&acc1>; + cpu-idle-states = <&CPU_WFI &CPU_SPC>; }; CPU2: cpu at 2 {
@@ -39,6 +41,7 @@ reg = <2>; next-level-cache = <&L2>; qcom,acc = <&acc2>; + cpu-idle-states = <&CPU_WFI &CPU_SPC>; }; CPU3: cpu at 3 {
@@ -48,6 +51,7 @@ reg = <3>; next-level-cache = <&L2>; qcom,acc = <&acc3>; + cpu-idle-states = <&CPU_WFI &CPU_SPC>; }; L2: l2-cache {
@@ -55,6 +59,22 @@ cache-level = <2>; qcom,saw = <&saw_l2>; }; + + idle-states { + CPU_WFI: cpu-idle-state-0 { + compatible = "qcom,idle-state-wfi", "arm,idle-state"; + entry-latency-us = <1>; + exit-latency-us = <1>; + min-residency-us = <2>; + }; + + CPU_SPC: cpu-idle-state-1 { + compatible = "qcom,idle-state-spc", "arm,idle-state"; + entry-latency-us = <150>; + exit-latency-us = <200>; + min-residency-us = <2000>; + }; + }; }; cpu-pmu {
Signature · 1 line
1.9.1
PATCH v5 7/7 arm: dts: qcom: Add idle states device nodes for 8974
Quoted 6 lines · Lina Iyer
Add allowable C-States for each cpu using the cpu-idle-states node. ARM spec dictates WFI as the default idle state at 0. Support standalone power collapse (power down that does not affect any SoC idle states) for each cpu.
Signed-off-by Lina Iyer <[email protected]>
[...]
arch/arm/boot/dts/qcom-msm8974.dtsi line 64
Quoted 7 lines
arch/arm/boot/dts/qcom-msm8974.dtsi +3
-0@@ -55,6 +59,22 @@ cache-level = <2>; qcom,saw = <&saw_l2>; }; + + idle-states { + CPU_WFI: cpu-idle-state-0 {
^^^^^^^^^^^^^^^^
Minor nit:
This name is what's being used to populate the idle state's ->name field in the CPUidle driver, which in turn is used by tools like powertop to display state names, etc.
So first, that name field has to be short (it currently gets truncated, dropping the zero), and second that field should be more descriptive, like 'WFI', so viewing in the various tools shows something useful.
Thanks,
Kevin
PATCH v5 7/7 arm: dts: qcom: Add idle states device nodes for 8974
In reply to Lina IyerQuoted 47 lines · Lina Iyer
Add allowable C-States for each cpu using the cpu-idle-states node. ARM spec dictates WFI as the default idle state at 0. Support standalone power collapse (power down that does not affect any SoC idle states) for each cpu.
Signed-off-by Lina Iyer <[email protected]>---
arch/arm/boot/dts/qcom-msm8974.dtsi| 20 ++++++++++++++++++++1 file changed, 20 insertions(+)arch/arm/boot/dts/qcom-msm8974.dtsi +4
-0@@ -21,6 +21,7 @@ reg = <0>; next-level-cache = <&L2>; qcom,acc = <&acc0>; + cpu-idle-states = <&CPU_WFI &CPU_SPC>; }; CPU1: cpu at 1 {@@ -30,6 +31,7 @@ reg = <1>; next-level-cache = <&L2>; qcom,acc = <&acc1>; + cpu-idle-states = <&CPU_WFI &CPU_SPC>; }; CPU2: cpu at 2 {@@ -39,6 +41,7 @@ reg = <2>; next-level-cache = <&L2>; qcom,acc = <&acc2>; + cpu-idle-states = <&CPU_WFI &CPU_SPC>; }; CPU3: cpu at 3 {@@ -48,6 +51,7 @@ reg = <3>; next-level-cache = <&L2>; qcom,acc = <&acc3>; + cpu-idle-states = <&CPU_WFI &CPU_SPC>; }; L2: l2-cache {
arch/arm/boot/dts/qcom-msm8974.dtsi line 64
Quoted 6 lines
arch/arm/boot/dts/qcom-msm8974.dtsi +3
-0@@ -55,6 +59,22 @@ cache-level = <2>; qcom,saw = <&saw_l2>; }; + + idle-states { + CPU_WFI: cpu-idle-state-0 {
I will rename the device node name to something more relevant. The name is used as the idle-state name.
Quoted 19 lines
arch/arm/boot/dts/qcom-msm8974.dtsi +13
-0+ compatible = "qcom,idle-state-wfi", "arm,idle-state"; + entry-latency-us = <1>; + exit-latency-us = <1>; + min-residency-us = <2>; + }; + + CPU_SPC: cpu-idle-state-1 { + compatible = "qcom,idle-state-spc", "arm,idle-state"; + entry-latency-us = <150>; + exit-latency-us = <200>; + min-residency-us = <2000>; + }; + }; }; cpu-pmu {Signature · 1 line
1.9.1
v5 cover QCOM 8074 cpuidle driver
In reply to Lina IyerHi Lina,
With your patchset on top of 3.17-rc4 with v9 of ARM generic idle states patches from Lorenzo I have tested cpuidle on dragonboard8974 with Linaro test suites. All testcases report pass. Also verified manually through sysfs to see changes in usage count and other details about each state on all cpus.
So,
I have a comment/observation only on name entry for each state which reflects only "cpu-idle-state-" as Lorenzo dt-idle driver limits CPUIDLE_NAME_LEN to 16.
Thanks
Pramod.
Quoted 141 lines · Lina Iyer
Changes since v4:
[ https://www.mail-archive.com/[email protected]/msg10327.html ]
- Update to the v8 of ARM generic idle states patches
- Use platform device model for cpuidle-qcom
- Clean upmsm-pm.cto remove unnecessary include files and functions
- Update commit text and documentation for all idle states
- Remove scm-boot relocate patch from this series, submitted earlier [ https://www.mail-archive.com/[email protected]/msg10518.html ]Changes since v3:
[ https://www.mail-archive.com/[email protected]/msg10288.html ]
- FixCONFIG_QCOM_PMKconfigas bool
- More clean ups inspm.candspm-devices.c
- Removed and re-organized data structures to make initialization simple
- Remove export of sequence flush functions
- Updated commit text
- Comments for use of barriers.
- Rebase on top of 3.17-rc1Changes since v2:
[ https://www.mail-archive.com/[email protected]/msg10148.html ]
- Prune all the drivers to support basic WFI and power down cpuidle functionality. Remove debug code.
- Integrate KConfig changes into the drivers' patches.
- Use Lorenzo's ARM idle-states patches as the basis for reading cpuidle c-states from DT.
[ http://marc.info/?l=linux-pm&m=140794514812383&w=2 ]
- Incorporate review comments
- Rebase on top of 3.16Changes since v1/RFC:
[ https://www.mail-archive.com/[email protected]/msg10065.html ]
- Remove hotplug from the patch series. Will submit it separately.
- Fix SPM drivers per the review comments
- Modify patch sequence to compile SPM drivers independent of msm-pm, so as to allowwfi()calls to use SPM even without SoC interface driver.8074 like any ARM SoC can do architectural clock gating, that helps save on power, but not enough of leakage power. Leakage power of the SoC can be further reduced by turning off power to the core. To aid this, every core (cpu and L2) is accompanied by a Sub-system Power Manager (SPM), that can be configured to indicate the low power mode, the core would be put into and the SPM programs the peripheral h/w accordingly to enter low power and turn off the power rail to the core.
The idle invocation hierarchy -
CPUIDLE | cpuidle-qcom.c [CPUIdle driver] | ------> msm-pm.c [SoC Interface layer for QCOM chipsets] | ------> spm-devices.c [SPM devices manager] | | | ------> spm.c [SPM h/w driver] | ------> scm-boot.c [SCM interface layer] | ------------------------|-------------------------- (EL) Secure Monitor Code | | wfi(); ------------------------|-------------------------- (HW) [CPU] {clock gate} | -----> [SPM] {statemachine}The patchset does the following -
- Add new Secure Monitor flags to support warmboot of a quad core system.
- Introduce the SPM driver to control power to the core. The SPM h/w IP works in conjunction with the Krait CPU/L2. When the core executes WFI instruction, the core is clockgated and the SPM state machine takes over and powers the core down. An interrupt from GIC, resumes the SPM state machine which brings the cpu out of the low power mode.
- Add a SPM device manager to configure multiple SPM devices.
- Add the device tree configuration for each of the SPM nodes. There is one for each cpu. There is one for each cpu.
- Introduce the SoC driver interface layer to configure SPM per the core's idle state. To power down the cpu core, the SPM h/w needs to be set up correctly
to power down the core, when the core executes WFI. Linux is expected to call into Secure Monitor to power down the core. At reset, the core will start in seure mode and will be returned back to Linux.- Add CPUIDLE driver for QCOM cpus. The cpuidle driver uses the SoC interface layer to configure the SPM to allow Krait to be powered down. The cpuidle driver is based on ARM idle-state framework for cpuidle drivers.
- Provide device configuration for 8074 SoC. Current support is for WFI and standalone power collapse, which powers only the core independent of the other cores and caches.
Thanks,
LinaLina Iyer (7):
msm: scm: Add SCM warmboot flags for quad core targets.
qcom: spm: Add Subsystem Power Manager driver (SAW2)
qcom: spm-devices: Add SPM device manager for the SoC
arm: dts: qcom: Add SPM device bindings for 8974
qcom: msm-pm: Add cpu low power mode functions
qcom: cpuidle: Add cpuidle driver for QCOM cpus
arm: dts: qcom: Add idle states device nodes for 8974.../bindings/arm/msm/qcom,idle-state.txt | 72 ++++++++ Documentation/devicetree/bindings/arm/msm/spm.txt | 47 +++++ arch/arm/boot/dts/qcom-msm8974-pm.dtsi | 69 +++++++ arch/arm/boot/dts/qcom-msm8974.dtsi | 30 +++- drivers/cpuidle/Kconfig.arm | 7 + drivers/cpuidle/Makefile | 1 + drivers/cpuidle/cpuidle-qcom.c | 87 +++++++++ drivers/soc/qcom/Kconfig | 8 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/msm-pm.c | 106 +++++++++++ drivers/soc/qcom/spm-devices.c | 198 +++++++++++++++++++++ drivers/soc/qcom/spm-drv.h | 69 +++++++ drivers/soc/qcom/spm.c | 192 ++++++++++++++++++++ include/soc/qcom/pm.h | 31 ++++ include/soc/qcom/scm-boot.h | 2 + include/soc/qcom/spm.h | 38 ++++ 16 files changed, 954 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt create mode 100644 Documentation/devicetree/bindings/arm/msm/spm.txt create mode 100644 arch/arm/boot/dts/qcom-msm8974-pm.dtsi create mode 100644 drivers/cpuidle/cpuidle-qcom.c create mode 100644 drivers/soc/qcom/msm-pm.c create mode 100644 drivers/soc/qcom/spm-devices.c create mode 100644 drivers/soc/qcom/spm-drv.h create mode 100644 drivers/soc/qcom/spm.c create mode 100644 include/soc/qcom/pm.h create mode 100644 include/soc/qcom/spm.h
v5 cover QCOM 8074 cpuidle driver
Quoted 11 lines · Pramod Gurav
Hi Lina,
With your patchset on top of 3.17-rc4 with v9 of ARM generic idle states patches from Lorenzo I have tested cpuidle on dragonboard8974 with Linaro test suites. All testcases report pass. Also verified manually through sysfs to see changes in usage count and other details about each state on all cpus.
So,
Tested-by Pramod Gurav <[email protected]>
Thanks!
Quoted 4 lines
I have a comment/observation only on name entry for each state which reflects only "cpu-idle-state-" as Lorenzo dt-idle driver limits
CPUIDLE_NAME_LENto 16.
Yes, Kevin pointed that out. I will address them in the next revision.
Quoted 144 lines
Thanks
Pramod.Quoted 141 lines · Lina Iyer
Changes since v4:
[ https://www.mail-archive.com/linux-arm-msm at vger.kernel.org/msg10327.html ]
- Update to the v8 of ARM generic idle states patches
- Use platform device model for cpuidle-qcom
- Clean upmsm-pm.cto remove unnecessary include files and functions
- Update commit text and documentation for all idle states
- Remove scm-boot relocate patch from this series, submitted earlier [ https://www.mail-archive.com/linux-arm-msm at vger.kernel.org/msg10518.html ]Changes since v3:
[ https://www.mail-archive.com/linux-arm-msm at vger.kernel.org/msg10288.html ]
- FixCONFIG_QCOM_PMKconfigas bool
- More clean ups inspm.candspm-devices.c
- Removed and re-organized data structures to make initialization simple
- Remove export of sequence flush functions
- Updated commit text
- Comments for use of barriers.
- Rebase on top of 3.17-rc1Changes since v2:
[ https://www.mail-archive.com/linux-arm-msm at vger.kernel.org/msg10148.html ]
- Prune all the drivers to support basic WFI and power down cpuidle functionality. Remove debug code.
- Integrate KConfig changes into the drivers' patches.
- Use Lorenzo's ARM idle-states patches as the basis for reading cpuidle c-states from DT.
[ http://marc.info/?l=linux-pm&m=140794514812383&w=2 ]
- Incorporate review comments
- Rebase on top of 3.16Changes since v1/RFC:
[ https://www.mail-archive.com/linux-arm-msm at vger.kernel.org/msg10065.html ]
- Remove hotplug from the patch series. Will submit it separately.
- Fix SPM drivers per the review comments
- Modify patch sequence to compile SPM drivers independent of msm-pm, so as to allowwfi()calls to use SPM even without SoC interface driver.8074 like any ARM SoC can do architectural clock gating, that helps save on power, but not enough of leakage power. Leakage power of the SoC can be further reduced by turning off power to the core. To aid this, every core (cpu and L2) is accompanied by a Sub-system Power Manager (SPM), that can be configured to indicate the low power mode, the core would be put into and the SPM programs the peripheral h/w accordingly to enter low power and turn off the power rail to the core.
The idle invocation hierarchy -
CPUIDLE | cpuidle-qcom.c [CPUIdle driver] | ------> msm-pm.c [SoC Interface layer for QCOM chipsets] | ------> spm-devices.c [SPM devices manager] | | | ------> spm.c [SPM h/w driver] | ------> scm-boot.c [SCM interface layer] | ------------------------|-------------------------- (EL) Secure Monitor Code | | wfi(); ------------------------|-------------------------- (HW) [CPU] {clock gate} | -----> [SPM] {statemachine}The patchset does the following -
- Add new Secure Monitor flags to support warmboot of a quad core system.
- Introduce the SPM driver to control power to the core. The SPM h/w IP works in conjunction with the Krait CPU/L2. When the core executes WFI instruction, the core is clockgated and the SPM state machine takes over and powers the core down. An interrupt from GIC, resumes the SPM state machine which brings the cpu out of the low power mode.
- Add a SPM device manager to configure multiple SPM devices.
- Add the device tree configuration for each of the SPM nodes. There is one for each cpu. There is one for each cpu.
- Introduce the SoC driver interface layer to configure SPM per the core's idle state. To power down the cpu core, the SPM h/w needs to be set up correctly
to power down the core, when the core executes WFI. Linux is expected to call into Secure Monitor to power down the core. At reset, the core will start in seure mode and will be returned back to Linux.- Add CPUIDLE driver for QCOM cpus. The cpuidle driver uses the SoC interface layer to configure the SPM to allow Krait to be powered down. The cpuidle driver is based on ARM idle-state framework for cpuidle drivers.
- Provide device configuration for 8074 SoC. Current support is for WFI and standalone power collapse, which powers only the core independent of the other cores and caches.
Thanks,
LinaLina Iyer (7):
msm: scm: Add SCM warmboot flags for quad core targets.
qcom: spm: Add Subsystem Power Manager driver (SAW2)
qcom: spm-devices: Add SPM device manager for the SoC
arm: dts: qcom: Add SPM device bindings for 8974
qcom: msm-pm: Add cpu low power mode functions
qcom: cpuidle: Add cpuidle driver for QCOM cpus
arm: dts: qcom: Add idle states device nodes for 8974.../bindings/arm/msm/qcom,idle-state.txt | 72 ++++++++ Documentation/devicetree/bindings/arm/msm/spm.txt | 47 +++++ arch/arm/boot/dts/qcom-msm8974-pm.dtsi | 69 +++++++ arch/arm/boot/dts/qcom-msm8974.dtsi | 30 +++- drivers/cpuidle/Kconfig.arm | 7 + drivers/cpuidle/Makefile | 1 + drivers/cpuidle/cpuidle-qcom.c | 87 +++++++++ drivers/soc/qcom/Kconfig | 8 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/msm-pm.c | 106 +++++++++++ drivers/soc/qcom/spm-devices.c | 198 +++++++++++++++++++++ drivers/soc/qcom/spm-drv.h | 69 +++++++ drivers/soc/qcom/spm.c | 192 ++++++++++++++++++++ include/soc/qcom/pm.h | 31 ++++ include/soc/qcom/scm-boot.h | 2 + include/soc/qcom/spm.h | 38 ++++ 16 files changed, 954 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt create mode 100644 Documentation/devicetree/bindings/arm/msm/spm.txt create mode 100644 arch/arm/boot/dts/qcom-msm8974-pm.dtsi create mode 100644 drivers/cpuidle/cpuidle-qcom.c create mode 100644 drivers/soc/qcom/msm-pm.c create mode 100644 drivers/soc/qcom/spm-devices.c create mode 100644 drivers/soc/qcom/spm-drv.h create mode 100644 drivers/soc/qcom/spm.c create mode 100644 include/soc/qcom/pm.h create mode 100644 include/soc/qcom/spm.h