ARM: sunxi: Add basic support for Allwinner A31 (sun6i)

Hi everyone,

This is v3 of the A31 support series. This series add basic (UART and MMC) support for Allwinner's A31 SoC. The patches, excluding the first one, were cherry-picked from u-boot-sunxi. Due to the difference between u-boot mainline and u-boot-sunxi, some patches were rearranged or squashed to better fit the current state of u-boot, and not introduce any build breaks. It follows Ian's initial merge method of sun7i support: introducing various components first, then enabling them in the last commit. I tried to keep the commits separate, thus retaining the original author and Signed-off-bys.

Patch 1 updates the current UART pinmuxing code to use macros for pull-up values. This is for existing platforms, but is included as it would conflict with patch 7.

Patch 2 adds a wrapper around "func(USB, usb, 0)" in BOOT_TARGET_DEVICES to deal with breakage when USB support is not enabled.

Patch 3 adds memory addresses for some hardware blocks new in sun6i.

Patch 4 adds support for the new PRCM (power reset and clock management) block, which also contains PLL bias voltage control.

Patch 5 adds support for the clock module. This patch is a bunch of different sun6i related patches on the clock code, from when sun6i support was introduced to u-boot-sunxi, up to its current form. This is done to avoid various conflicts and needlessly introducing then removing macros.

Patch 6 adds mmc support on sun6i.

Patch 7 adds uart0 pin macros.

Patch 8 adds uart0 muxing on sun6i.

Patch 9 enables sun6i support.

Patch 10 adds a defconfig for the Colombus board, which is an A31 evaluation board.

Changes since v2:

- Added Maxime Ripard as maintainer of Colombus board

Changes since v1:

- Added macros for sun6i uart pinmuxes (patch 7)

- Use gpio macros when muxing uarts (patch 1, 8)

- Clarify what is enabled in PRCM (patch 4)

- Dropped old comments in commit message from Hans (patch 4)

- Use setbits helpers in PRCM code (patch 4)

- Drop SPL code block from clock code (patch 5)

- Make mmc code use fifo in register structure definition, and add reserved area to adjust for sun6i's different fifo address (patch 6)

- Rewrite patch 9 commit message to reflect what is supported

- Split out Colombus board defconfig into separate patch (patch 10)

Cheers
ChenYu

Chen-Yu Tsai (5):
ARM: sunxi: Use macro values for setting UART GPIO pull-ups
ARM: sunxi: Fix build break when CONFIG_USB_EHCI is not defined
ARM: sun6i: Add clock support
ARM: sun6i: Define UART0 pins for A31
ARM: sun6i: Add Colombus board defconfig

Hans de Goede (1):
ARM: sunxi-mmc: Add mmc support for sun6i / A31

Maxime Ripard (2):
ARM: sun6i: Setup the A31 UART0 muxing
ARM: sunxi: Add basic A31 support

Oliver Schinagl (2):
ARM: sun6i: Add base address for the new controllers in A31
ARM: sun6i: Add support for the power reset control module found on

    the A31

 arch/arm/Kconfig                              |   3 +
 arch/arm/cpu/armv7/sunxi/Makefile             |   2 +
 arch/arm/cpu/armv7/sunxi/board.c              |  10 +-
 arch/arm/cpu/armv7/sunxi/clock_sun6i.c        |  70 ++++++++
 arch/arm/cpu/armv7/sunxi/cpu_info.c           |   2 +
 arch/arm/cpu/armv7/sunxi/prcm.c               |  33 ++++
 arch/arm/include/asm/arch-sunxi/clock.h       |   4 +
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 205 ++++++++++++++++++++++
 arch/arm/include/asm/arch-sunxi/cpu.h         |   9 +
 arch/arm/include/asm/arch-sunxi/gpio.h        |   3 +
 arch/arm/include/asm/arch-sunxi/mmc.h         |   5 +-
 arch/arm/include/asm/arch-sunxi/prcm.h        | 238 ++++++++++++++++++++++++++
 board/sunxi/Kconfig                           |  10 +-
 board/sunxi/MAINTAINERS                       |   5 +
 configs/Colombus_defconfig                    |   4 +
 drivers/mmc/sunxi_mmc.c                       |  11 +-
 include/configs/sun6i.h                       |  26 +++
 include/configs/sunxi-common.h                |   8 +-
 18 files changed, 638 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/sunxi/clock_sun6i.c
 create mode 100644 arch/arm/cpu/armv7/sunxi/prcm.c
 create mode 100644 arch/arm/include/asm/arch-sunxi/clock_sun6i.h
 create mode 100644 arch/arm/include/asm/arch-sunxi/prcm.h
 create mode 100644 configs/Colombus_defconfig
 create mode 100644 include/configs/sun6i.h

2.1.1

We have already defined macros for pull-up/down values in the GPIO header. Use them instead of magic numbers when configuring the UART pins.

---
 arch/arm/cpu/armv7/sunxi/board.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

index f2cedbb..95a74c5 100644
@@ -53,15 +53,15 @@ int gpio_init(void)
 #if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
-	sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
+	sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
-	sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
+	sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
-	sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
+	sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
 #else
 #error Unsupported console port number. Please fix pin mux settings in board.c
 #endif

2.1.1

BOOT_TARGET_DEVICES includes USB unconditionally. This breaks when CONFIG_CMD_USB is not defined. Use a secondary macro to conditionally include it when CONFIG_EHCI is enabled, as we do for CONFIG_AHCI.

---
 include/configs/sunxi-common.h | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

index 1d947d7..a31656e 100644
@@ -233,10 +233,16 @@
 #define BOOT_TARGET_DEVICES_SCSI(func)
 #endif
 
+#ifdef CONFIG_USB_EHCI
+#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
+#else
+#define BOOT_TARGET_DEVICES_USB(func)
+#endif
+
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 0) \
 	BOOT_TARGET_DEVICES_SCSI(func) \
-	func(USB, usb, 0) \
+	BOOT_TARGET_DEVICES_USB(func) \
 	func(PXE, pxe, na) \
 	func(DHCP, dhcp, na)
 

2.1.1

From: Oliver Schinagl <[email protected]>

A31 has several new and changed memory address. This patch adds them.

---
 arch/arm/include/asm/arch-sunxi/cpu.h | 9 +++++++++
 1 file changed, 9 insertions(+)

index a987e51d..313e6c8 100644
@@ -95,6 +95,11 @@
 #define SUNXI_MALI400_BASE		0x01c40000
 #define SUNXI_GMAC_BASE			0x01c50000
 
+#define SUNXI_DRAM_COM_BASE		0x01c62000
+#define SUNXI_DRAM_CTL_BASE		0x01c63000
+#define SUNXI_DRAM_PHY_CH1_BASE		0x01c65000
+#define SUNXI_DRAM_PHY_CH2_BASE		0x01c66000
+
 /* module sram */
 #define SUNXI_SRAM_C_BASE		0x01d00000
 

@@ -105,6 +110,10 @@
 #define SUNXI_MP_BASE			0x01e80000
 #define SUNXI_AVG_BASE			0x01ea0000
 
+#define SUNXI_PRCM_BASE			0x01f01400
+#define SUNXI_R_PIO_BASE		0x01f02c00
+#define SUNXI_P2WI_BASE			0x01f03400
+
 /* CoreSight Debug Module */
 #define SUNXI_CSDM_BASE			0x3f500000
 

2.1.1

From: Oliver Schinagl <[email protected]>

The A31 has a new module called PRCM, or Power, Reset Control Module. This module controls clocks and resets for RTC block modules, and also PLL biasing in the main clock module.

This patch adds the register definitions, and also enables the clocks and resets for the RTC block PIO (pin controller) and P2WI (push-pull 2 wire interface) which is used to talk to the PMIC.

[wens at csie.org: rephrase commit message to explain what the hardware
supports and what we actually enable]

---
 arch/arm/cpu/armv7/sunxi/Makefile      |   1 +
 arch/arm/cpu/armv7/sunxi/prcm.c        |  33 +++++
 arch/arm/include/asm/arch-sunxi/prcm.h | 238 +++++++++++++++++++++++++++++++++
 3 files changed, 272 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/sunxi/prcm.c
 create mode 100644 arch/arm/include/asm/arch-sunxi/prcm.h

index e9721b2..f0473d2 100644
@@ -11,6 +11,7 @@ obj-y	+= timer.o
 obj-y	+= board.o
 obj-y	+= clock.o
 obj-y	+= pinmux.o
+obj-$(CONFIG_SUN6I)	+= prcm.o
 obj-$(CONFIG_SUN4I)	+= clock_sun4i.o
 obj-$(CONFIG_SUN5I)	+= clock_sun4i.o
 obj-$(CONFIG_SUN7I)	+= clock_sun4i.o

new file mode 100644
index 0000000..7b3ee89
@@ -0,0 +1,33 @@
+/*
+ * Sunxi A31 Power Management Unit
+ *
+ * (C) Copyright 2013 Oliver Schinagl <[email protected]>
+ * http://linux-sunxi.org
+ *
+ * Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work
+ *
+ * (C) Copyright 2006-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <[email protected]>
+ * Tom Cubie <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/sys_proto.h>
+
+void prcm_init_apb0(void)
+{
+	struct sunxi_prcm_reg *prcm =
+		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+	setbits_le32(&prcm->apb0_gate, PRCM_APB0_GATE_P2WI |
+				       PRCM_APB0_GATE_PIO);
+	setbits_le32(&prcm->apb0_reset, PRCM_APB0_RESET_P2WI |
+					PRCM_APB0_RESET_PIO);
+}

2.1.1

This patch adds the basic clocks support for the Allwinner A31 (sun6i) processor. This code will not been compiled until the build is hooked up in a later patch. It has been split out to keep the patches manageable.

This includes changes from the following commits from u-boot-sunxi:

a92051b ARM: sunxi: Add sun6i clock controller structure
1f72c6f ARM: sun6i: Setup the UART0 clocks
5f2e712 ARM: sunxi: Enable pll6 by default on all models
2be2f2a ARM: sunxi-mmc: Add mmc support for sun6i / A31
12e1633 ARM: sun6i: Add initial clock setup for SPL
1a9c9c6 ARM: sunxi: Split clock code into common, sun4i and sun6i code 0b194ee ARM: sun6i: Properly setup the PLL LDO in clock_init_safe b54c626 sunxi: avoid sr32 for APB1 clock setup.
68fe29c sunxi: remove magic numbers from clock_get_pll{5,6}
c89867d sunxi: clocks: clock_get_pll5 prototype and coding style 501ab1e ARM: sunxi: Fix sun6i PLL6 settings
37f669b ARM: sunxi: Fix macro names for mmc and uart reset offsets 61de1e6 ARM: sunxi: Correct comment for MBUS1 register in sun6i clock definitions

---
 arch/arm/cpu/armv7/sunxi/Makefile             |   1 +
 arch/arm/cpu/armv7/sunxi/clock_sun6i.c        |  70 +++++++++
 arch/arm/include/asm/arch-sunxi/clock.h       |   4 +
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 205 ++++++++++++++++++++++++++
 4 files changed, 280 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/sunxi/clock_sun6i.c
 create mode 100644 arch/arm/include/asm/arch-sunxi/clock_sun6i.h

index f0473d2..2a42dca 100644
@@ -14,6 +14,7 @@ obj-y	+= pinmux.o
 obj-$(CONFIG_SUN6I)	+= prcm.o
 obj-$(CONFIG_SUN4I)	+= clock_sun4i.o
 obj-$(CONFIG_SUN5I)	+= clock_sun4i.o
+obj-$(CONFIG_SUN6I)	+= clock_sun6i.o
 obj-$(CONFIG_SUN7I)	+= clock_sun4i.o
 
 ifndef CONFIG_SPL_BUILD

index 5669f39..8f5d860 100644
@@ -15,7 +15,11 @@
 #define CLK_GATE_CLOSE			0x0
 
 /* clock control module regs definition */
+#ifdef CONFIG_SUN6I
+#include <asm/arch/clock_sun6i.h>
+#else
 #include <asm/arch/clock_sun4i.h>
+#endif
 
 #ifndef __ASSEMBLY__
 int clock_init(void);

2.1.1

From: Hans de Goede <[email protected]>

The mmc hardware on sun6i has an extra reset control that needs to be de-asserted prior to usage. Also the FIFO address is different.

[wens at csie.org: use setbits_le32 for reset control, drop obsolete changes,
rewrite different FIFO address handling, add commit message]

---
 arch/arm/include/asm/arch-sunxi/mmc.h |  5 ++++-
 drivers/mmc/sunxi_mmc.c               | 11 +++++++----
 2 files changed, 11 insertions(+), 5 deletions(-)

index 53196e3..6a31184 100644
@@ -43,7 +43,10 @@ struct sunxi_mmc {
 	u32 chda;		/* 0x90 */
 	u32 cbda;		/* 0x94 */
 	u32 res1[26];
-	u32 fifo;		/* 0x100 FIFO access address */
+#if defined(CONFIG_SUN6I)
+	u32 res2[64];
+#endif
+	u32 fifo;		/* 0x100 (0x200 on sun6i) FIFO access address */
 };
 
 #define SUNXI_MMC_CLK_POWERSAVE		(0x1 << 17)

index bc2c4b3..8f4b50b 100644
@@ -19,7 +19,6 @@
 struct sunxi_mmc_host {
 	unsigned mmc_no;
 	uint32_t *mclkreg;
-	unsigned database;
 	unsigned fatal_err;
 	unsigned mod_clk;
 	struct sunxi_mmc *reg;

@@ -57,7 +56,6 @@ static int mmc_resource_init(int sdc_no)
 		printf("Wrong mmc number %d\n", sdc_no);
 		return -1;
 	}
-	mmchost->database = (unsigned int)mmchost->reg + 0x100;
 	mmchost->mmc_no = sdc_no;
 
 	return 0;

@@ -75,6 +73,11 @@ static int mmc_clk_io_on(int sdc_no)
 	/* config ahb clock */
 	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
 
+#if defined(CONFIG_SUN6I)
+	/* unassert reset */
+	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
+#endif
+
 	/* config mod clock */
 	pll_clk = clock_get_pll6();
 	/* should be close to 100 MHz but no more, so round up */

@@ -194,9 +197,9 @@ static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
 		}
 
 		if (reading)
-			buff[i] = readl(mmchost->database);
+			buff[i] = readl(&mmchost->reg->fifo);
 		else
-			writel(buff[i], mmchost->database);
+			writel(buff[i], &mmchost->reg->fifo);
 	}
 
 	return 0;

2.1.1

UART0 is the default debug/console UART on the A31.

---
 arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++
 1 file changed, 3 insertions(+)

index f7f3d8c..ba7e69b 100644
@@ -132,6 +132,9 @@ enum sunxi_gpio_number {
 
 #define SUN4I_GPH22_SDC1	5
 
+#define SUN6I_GPH20_UART0_TX	2
+#define SUN6I_GPH21_UART0_RX	2
+
 #define SUN4I_GPI4_SDC3		2
 
 /* GPIO pin pull-up/down config */

2.1.1

From: Maxime Ripard <[email protected]>

---
 arch/arm/cpu/armv7/sunxi/board.c | 4 ++++
 1 file changed, 4 insertions(+)

index 95a74c5..b6d63db 100644
@@ -58,6 +58,10 @@ int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
 	sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN6I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX);
+	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);

2.1.1

From: Maxime Ripard <[email protected]>

Add a new sun6i machine that supports UART and MMC.

[wens at csie.org: use SPDX labels, adapt to Kconfig system, drop ifdef
around mmc and smp code, drop MACH_TYPE]

---
 arch/arm/Kconfig                    |  3 +++
 arch/arm/cpu/armv7/sunxi/cpu_info.c |  2 ++
 board/sunxi/Kconfig                 | 10 +++++++++-
 include/configs/sun6i.h             | 26 ++++++++++++++++++++++++++
 4 files changed, 40 insertions(+), 1 deletion(-)
 create mode 100644 include/configs/sun6i.h

index 3efede2..e3e7e78 100644
@@ -444,6 +444,9 @@ config TARGET_SUN4I
 config TARGET_SUN5I
 	bool "Support sun5i"
 
+config TARGET_SUN6I
+	bool "Support sun6i"
+
 config TARGET_SUN7I
 	bool "Support sun7i"
 

index 5cf35ac..40c4e13 100644
@@ -23,6 +23,8 @@ int print_cpuinfo(void)
 	case 7: puts("CPU:   Allwinner A10s (SUN5I)\n"); break;
 	default: puts("CPU:   Allwinner A1X (SUN5I)\n");
 	}
+#elif defined CONFIG_SUN6I
+	puts("CPU:   Allwinner A31 (SUN6I)\n");
 #elif defined CONFIG_SUN7I
 	puts("CPU:   Allwinner A20 (SUN7I)\n");
 #else

index bcd0a55..05defac 100644
@@ -12,6 +12,14 @@ config SYS_CONFIG_NAME
 
 endif
 
+if TARGET_SUN6I
+
+config SYS_CONFIG_NAME
+	string
+	default "sun6i"
+
+endif
+
 if TARGET_SUN7I
 
 config SYS_CONFIG_NAME

@@ -19,7 +27,7 @@ config SYS_CONFIG_NAME
 
 endif
 
-if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN7I
+if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN6I || TARGET_SUN7I
 
 config SYS_CPU
 	default "armv7"

new file mode 100644
index 0000000..93a1d96
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2012-2013 Henrik Nordstrom <[email protected]>
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <[email protected]>
+ * (C) Copyright 2013 Maxime Ripard <[email protected]>
+ *
+ * Configuration settings for the Allwinner A31 (sun6i) CPU
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A31 specific configuration
+ */
+#define CONFIG_SUN6I		/* sun6i SoC generation */
+
+#define CONFIG_SYS_PROMPT		"sun6i# "
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */

2.1.1

The Colombus board is an A31 evaluation board from WITS Technology.

Maxime has kindly agreed to maintain this board.

[1] http://lists.denx.de/pipermail/u-boot/2014-September/190043.html

---
 board/sunxi/MAINTAINERS    | 5 +++++
 configs/Colombus_defconfig | 4 ++++
 2 files changed, 9 insertions(+)
 create mode 100644 configs/Colombus_defconfig

index 6c4226e..7afe45e 100644
@@ -45,3 +45,8 @@ M:	Iain Paton <[email protected]>
 S:	Maintained
 F:	board/sunxi/dram_a20_olinuxino_l2.c
 F:	configs/A20-OLinuXino-Lime2_defconfig
+
+COLOMBUS BOARD
+M:	Maxime Ripard <[email protected]>
+S:	Maintained
+F:	configs/Colombus_defconfig

new file mode 100644
index 0000000..16800de
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="COLOMBUS"
+CONFIG_ARM=y
+CONFIG_TARGET_SUN6I=y
+CONFIG_FDTFILE="sun6i-a31-colombus.dtb"

2.1.1

Thanks!

Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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I'll apply these to u-boot-sunxi#next once I get a spare moment, probably over the w/e.

Cheers,
Ian

Thanks. I'll do basic sun8i next.

Now done.

Cool, thanks!

Cheers,
Ian.