CHV PM fix & Improvements
Subsystems (2)
cover CHV PM fix & Improvements
From: Deepak S <[email protected]>
Adding few of PM fixes and Improvements for CHV/VLV.
Deepak S (5):
drm/i915/chv: Remove Wait for a previous gfx force-off drm/i915: Re-adjusting rc6 promotional timer for chv drm/i915/chv: Set min freq to efficient frequency on chv drm/i915: Modifying RC6 Promotion timer for Media workloads. drm/i915: Setup static bias for GPU
drivers/gpu/drm/i915/i915_drv.c | 6 ++-- drivers/gpu/drm/i915/i915_drv.h | 3 ++ drivers/gpu/drm/i915/i915_gem_execbuffer.c | 15 +++++++++ drivers/gpu/drm/i915/i915_reg.h | 5 +++ drivers/gpu/drm/i915/intel_drv.h | 2 ++ drivers/gpu/drm/i915/intel_lrc.c | 15 +++++++++ drivers/gpu/drm/i915/intel_pm.c | 53 ++++++++++++++++++++++++++++-- 7 files changed, 94 insertions(+), 5 deletions(-)
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PATCH 1/5 drm/i915/chv: Remove Wait for a previous gfx force-off
From: Deepak S <[email protected]>
On CHV, PUNIT team confirmed that 'VLV_GFX_CLK_STATUS_BIT' is not a sticky bit and it will always be set. So ignore Check for previous Gfx force off during suspend and allow the force clk as part S0ix Sequence
--- drivers/gpu/drm/i915/i915_drv.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
drivers/gpu/drm/i915/i915_drv.c +4 -2
@@ -1193,11 +1193,13 @@ int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)int err; val =I915_READ (VLV_GTLC_SURVIVABILITY_REG ); -WARN_ON (!!(val &VLV_GFX_CLK_FORCE_ON_BIT ) == force_on);#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)/* Wait for a previous force-off to settle */ -if (force_on) { +if (force_on && !IS_CHERRYVIEW (dev_priv->dev)) { +/* WARN_ON only for the Valleyview */ +WARN_ON (!!(val &VLV_GFX_CLK_FORCE_ON_BIT ) == force_on); + err =wait_for (!COND ,20 );if (err) { DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
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Re: [PATCH 1/5] drm/i915/chv: Remove Wait for a previous gfx force-off
Quoted 6 lines · On Thu, Feb 26, 2015 at 08:46:54PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
On CHV, PUNIT team confirmed that '
VLV_GFX_CLK_STATUS_BIT' is not a sticky bit and it will always be set. So ignore Check for previous Gfx force off during suspend and allow the force clk as part S0ix Sequence
Do we need the force clock at all since we don't do any gunit register save/restore? I tried to peddle a patch to remove it totally in this bug report, but never got any decent answer back:
https://bugs.freedesktop.org/show_bug.cgi?id=87086
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Signed-off-by Deepak S <[email protected]>--- drivers/gpu/drm/i915/i915_drv.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)drivers/gpu/drm/i915/i915_drv.c +4
-2@@ -1193,11 +1193,13 @@ int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)int err; val =I915_READ (VLV_GTLC_SURVIVABILITY_REG ); -WARN_ON (!!(val &VLV_GFX_CLK_FORCE_ON_BIT ) == force_on);#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)/* Wait for a previous force-off to settle */ -if (force_on) { +if (force_on && !IS_CHERRYVIEW (dev_priv->dev)) { +/* WARN_ON only for the Valleyview */ +WARN_ON (!!(val &VLV_GFX_CLK_FORCE_ON_BIT ) == force_on); + err =wait_for (!COND ,20 );if (err) { DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",Signature · 1 line
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Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH 1/5] drm/i915/chv: Remove Wait for a previous gfx force-off
Quoted 11 lines · Ville Syrjälä
Quoted 6 lines · On Thu, Feb 26, 2015 at 08:46:54PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
On CHV, PUNIT team confirmed that '
VLV_GFX_CLK_STATUS_BIT' is not a sticky bit and it will always be set. So ignore Check for previous Gfx force off during suspend and allow the force clk as part S0ix SequenceDo we need the force clock at all since we don't do any gunit register save/restore? I tried to peddle a patch to remove it totally in this bug report, but never got any decent answer back:
https://bugs.freedesktop.org/show_bug.cgi?id=87086
hmm. your right we might not need. Let me confirm
Quoted 15 lines
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Signed-off-by Deepak S <[email protected]>--- drivers/gpu/drm/i915/i915_drv.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)drivers/gpu/drm/i915/i915_drv.c +0
-1@@ -1193,11 +1193,13 @@ int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)int err; val =I915_READ (VLV_GTLC_SURVIVABILITY_REG ); -WARN_ON (!!(val &VLV_GFX_CLK_FORCE_ON_BIT ) == force_on);
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drivers/gpu/drm/i915/i915_drv.c +4
-1#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)/* Wait for a previous force-off to settle */ -if (force_on) { +if (force_on && !IS_CHERRYVIEW (dev_priv->dev)) { +/* WARN_ON only for the Valleyview */ +WARN_ON (!!(val &VLV_GFX_CLK_FORCE_ON_BIT ) == force_on); + err =wait_for (!COND ,20 );if (err) { DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",Signature · 1 line
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Re: [PATCH 1/5] drm/i915/chv: Remove Wait for a previous gfx force-off
Quoted 9 lines · Deepak S
Quoted 7 lines · Ville Syrjälä
Quoted 6 lines · On Thu, Feb 26, 2015 at 08:46:54PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
On CHV, PUNIT team confirmed that '
VLV_GFX_CLK_STATUS_BIT' is not a sticky bit and it will always be set. So ignore Check for previous Gfx force off during suspend and allow the force clk as part S0ix Sequence
Quoted 6 lines
Quoted 4 lines
Do we need the force clock at all since we don't do any gunit register save/restore? I tried to peddle a patch to remove it totally in this bug report, but never got any decent answer back:
https://bugs.freedesktop.org/show_bug.cgi?id=87086hmm. your right we might not need. Let me confirm
Hi Ville,
Based on the spec we still need to follow the Gfx force clk sequence :( Can you review the patch to skip wait for previous Gfx force-off? This patch has gone through lot of S0ix testing.
Thanks
Deepak
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Signed-off-by Deepak S <[email protected]>--- drivers/gpu/drm/i915/i915_drv.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)drivers/gpu/drm/i915/i915_drv.c +4
-2@@ -1193,11 +1193,13 @@ int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) int err; val =I915_READ (VLV_GTLC_SURVIVABILITY_REG ); -WARN_ON (!!(val &VLV_GFX_CLK_FORCE_ON_BIT ) == force_on);#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)/* Wait for a previous force-off to settle */ -if (force_on) { +if (force_on && !IS_CHERRYVIEW (dev_priv->dev)) { +/* WARN_ON only for the Valleyview */ +WARN_ON (!!(val &VLV_GFX_CLK_FORCE_ON_BIT ) == force_on); + err =wait_for (!COND ,20 );if (err) { DRM_ERROR("timeout waiting for GFX clock force-off
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(%08x)\n",
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PATCH 2/5 drm/i915: Re-adjusting rc6 promotional timer for chv
In reply to [email protected]From: Deepak S <[email protected]>
After feedback from the hardware team we are changing the RC6 promotional timer to increase the power saving without changing performance.
--- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/gpu/drm/i915/intel_pm.c +2 -2
@@ -4799,8 +4799,8 @@ static void cherryview_enable_rps(struct drm_device *dev)I915_WRITE (RING_MAX_IDLE (ring->mmio_base),10 );I915_WRITE (GEN6_RC_SLEEP ,0 ); -/* TO threshold set to 1750 us ( 0x557 * 1.28 us) */ -I915_WRITE (GEN6_RC6_THRESHOLD ,0x557 ); +/* TO threshold set to 500 us ( 0x186 * 1.28 us) */ +I915_WRITE (GEN6_RC6_THRESHOLD ,0x186 );/* allows RC6 residency counter to work */ I915_WRITE(VLV_COUNTER_CONTROL,
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Re: [PATCH 2/5] drm/i915: Re-adjusting rc6 promotional timer for chv
2015-02-26 12:16 GMT-03:00 <[email protected]>:
Quoted 5 lines
From: Deepak S <[email protected]>
After feedback from the hardware team we are changing the RC6 promotional timer to increase the power saving without changing performance.
I can't really say whether this is really what we want since I didn't do any measurements, but the patch seems to do what it says, so:
Quoted 28 lines
Signed-off-by Deepak S <[email protected]>--- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)drivers/gpu/drm/i915/intel_pm.c +2
-3@@ -4799,8 +4799,8 @@ static void cherryview_enable_rps(struct drm_device *dev)I915_WRITE (RING_MAX_IDLE (ring->mmio_base),10 );I915_WRITE (GEN6_RC_SLEEP ,0 ); -/* TO threshold set to 1750 us ( 0x557 * 1.28 us) */ -I915_WRITE (GEN6_RC6_THRESHOLD ,0x557 ); +/* TO threshold set to 500 us ( 0x186 * 1.28 us) */ +I915_WRITE (GEN6_RC6_THRESHOLD ,0x186 );/* allows RC6 residency counter to work */ I915_WRITE(VLV_COUNTER_CONTROL, --1.9.1
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Paulo Zanoni _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH 2/5] drm/i915: Re-adjusting rc6 promotional timer for chv
Quoted 9 lines · Paulo Zanoni
2015-02-26 12:16 GMT-03:00 <[email protected]>:
Quoted 5 lines
From: Deepak S <[email protected]>
After feedback from the hardware team we are changing the RC6 promotional timer to increase the power saving without changing performance.
I can't really say whether this is really what we want since I didn't do any measurements, but the patch seems to do what it says, so:
Reviewed-by Paulo Zanoni <[email protected]>
Hi Paulo,
Measurements was done by hardware team :)
Thanks
Deepak
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Signed-off-by Deepak S <[email protected]>--- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)drivers/gpu/drm/i915/intel_pm.c +2
-3@@ -4799,8 +4799,8 @@ static void cherryview_enable_rps(struct drm_device *dev)I915_WRITE (RING_MAX_IDLE (ring->mmio_base),10 );I915_WRITE (GEN6_RC_SLEEP ,0 ); -/* TO threshold set to 1750 us ( 0x557 * 1.28 us) */ -I915_WRITE (GEN6_RC6_THRESHOLD ,0x557 ); +/* TO threshold set to 500 us ( 0x186 * 1.28 us) */ +I915_WRITE (GEN6_RC6_THRESHOLD ,0x186 );/* allows RC6 residency counter to work */ I915_WRITE(VLV_COUNTER_CONTROL, --1.9.1
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PATCH 3/5 drm/i915/chv: Set min freq to efficient frequency on chv
In reply to [email protected]From: Deepak S <[email protected]>
After feedback from the hardware team, now we set the GPU min freq to RPe. If we drop the freq to RPn, we found that the punit was not setting the voltage to Vnn, So recommendation is to set min freq to RPe.
--- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/gpu/drm/i915/intel_pm.c +1 -1
@@ -4755,7 +4755,7 @@ static void cherryview_init_gt_powersave(struct drm_device *dev) dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;if (dev_priv->rps.min_freq_softlimit ==0 ) - dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; + dev_priv->rps.min_freq_softlimit = dev_priv->rps.efficient_freq;mutex_unlock (&dev_priv->rps.hw_lock); }
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Re: [PATCH 3/5] drm/i915/chv: Set min freq to efficient frequency on chv
Quoted 5 lines · On Thu, Feb 26, 2015 at 08:46:56PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
After feedback from the hardware team, now we set the GPU min freq to RPe. If we drop the freq to RPn, we found that the punit was not setting the voltage to Vnn, So recommendation is to set min freq to RPe.
And does it change the voltage at all? Is there really any advantage to the extra code on idle? Does efficient_freq really consume less power than min_freq when active (assuming a min_freq/efficient_freq busy workload i.e. does a workload that would be 100% busy at min_freq consume less power when run at efficient_freq)?
-Chris
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Re: [PATCH 3/5] drm/i915/chv: Set min freq to efficient frequency on chv
Quoted 7 lines · Chris Wilson
Quoted 5 lines · On Thu, Feb 26, 2015 at 08:46:56PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
After feedback from the hardware team, now we set the GPU min freq to RPe. If we drop the freq to RPn, we found that the punit was not setting the voltage to Vnn, So recommendation is to set min freq to RPe.
And does it change the voltage at all?
Yes Voltage does change when we drop to RPe
Quoted 5 lines
Is there really any advantage to
the extra code on idle?Doesefficient_freqreally consume less power thanmin_freqwhen active (assuming a min_freq/efficient_freq busy workload i.e. does a workload that would be 100% busy atmin_freqconsume less power when run atefficient_freq)?
The delta voltage usage between RPn and RPe is very small like close to zero.
Also, if we run workload 100% busy at Rpe we get better performance without much of voltage loss right? btw, Punit expects us to operate between Rpe & RP0.
Quoted 2 lines
-Chris
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Re: [PATCH 3/5] drm/i915/chv: Set min freq to efficient frequency on chv
Quoted 19 lines · Deepak S
Quoted 7 lines · Chris Wilson
Quoted 5 lines · On Thu, Feb 26, 2015 at 08:46:56PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
After feedback from the hardware team, now we set the GPU min freq to RPe. If we drop the freq to RPn, we found that the punit was not setting the voltage to Vnn, So recommendation is to set min freq to RPe.
And does it change the voltage at all?
Yes Voltage does change when we drop to RPe
Quoted 5 lines
Is there really any advantage to
the extra code on idle?Doesefficient_freqreally consume less power thanmin_freqwhen active (assuming a min_freq/efficient_freq busy workload i.e. does a workload that would be 100% busy atmin_freqconsume less power when run atefficient_freq)?
Quoted 3 lines
The delta voltage usage between RPn and RPe is very small like close to zero.
Also, if we run workload 100% busy at Rpe we get better performance without much of voltage loss right? btw, Punit expects us to operate between Rpe & RP0.
If you need 100% at RPe you obviously can't run at RPn (since that would lead to dropped frames). The question is if you have a workload that requires 100% at RPn do you save power if you ran e.g. 80% at RPe?
If the punit only works reliably between RPe and RP0, then the current RPn is a bit of a misnomer, and that should be the explanation in the commit log. Definitely do not conflate the idea of executing at RPn and RPe with the idea of idling at RPn or RPe - this patch affects idle frequency.
-Chris
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Re: [PATCH 3/5] drm/i915/chv: Set min freq to efficient frequency on chv
Quoted 17 lines · Chris Wilson
Quoted 16 lines · Deepak S
Quoted 7 lines · Chris Wilson
Quoted 5 lines · On Thu, Feb 26, 2015 at 08:46:56PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
After feedback from the hardware team, now we set the GPU min freq to RPe. If we drop the freq to RPn, we found that the punit was not setting the voltage to Vnn, So recommendation is to set min freq to RPe.
And does it change the voltage at all?
Yes Voltage does change when we drop to RPe
Quoted 5 lines
Is there really any advantage to
the extra code on idle?Doesefficient_freqreally consume less power thanmin_freqwhen active (assuming a min_freq/efficient_freq busy workload i.e. does a workload that would be 100% busy atmin_freqconsume less power when run atefficient_freq)?
Quoted 6 lines
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The delta voltage usage between RPn and RPe is very small like close to zero.
Also, if we run workload 100% busy at Rpe we get better performance without much of voltage loss right? btw, Punit expects us to operate between Rpe & RP0.If you need 100% at RPe you obviously can't run at RPn (since that would lead to dropped frames). The question is if you have a workload that requires 100% at RPn do you save power if you ran e.g. 80% at RPe?
We do not expect much of power saving running at RPn. If we need exact number I need to gather the data.
Quoted 8 lines
If the punit only works reliably between RPe and RP0, then the current RPn is a bit of a misnomer, and that should be the explanation in the commit log. Definitely do not conflate the idea of executing at RPn and RPe with the idea of idling at RPn or RPe - this patch affects idle frequency.
-Chris
Yes I understand it affects idle freq but running at RPe gives better performance at lower voltage and also punit drops voltage to help save power I will update the commit msg to explain why we need lower freq at Rpe.
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PATCH 4/5 drm/i915: Modifying RC6 Promotion timer for Media workloads.
In reply to [email protected]From: Deepak S <[email protected]>
In normal cases, RC6 promotion timer is 1700us/500us. This will result in more time spent in C1 state. For more residency in C6 in case of media workloads, this is changed to 250us. Not doing this for 3D workloads as too many C6-C0 transition delays can result in performance impact
--- drivers/gpu/drm/i915/i915_drv.h | 3 +++ drivers/gpu/drm/i915/i915_gem_execbuffer.c | 15 +++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 2 ++ drivers/gpu/drm/i915/intel_lrc.c | 15 +++++++++++++ drivers/gpu/drm/i915/intel_pm.c | 35 ++++++++++++++++++++++++++++++ 5 files changed, 70 insertions(+)
drivers/gpu/drm/i915/i915_drv.h +3 -0
@@ -1160,6 +1160,9 @@ struct intel_gen6_power_mgmt {* Must be taken after struct_mutex if nested. */ struct mutex hw_lock; + +/* Delayed work to adjust RC6 promotion timer */ +struct delayed_work vlv_media_timeout_work; };/* defined intel_pm.c */
drivers/gpu/drm/i915/i915_gem_execbuffer.c +15 -0
@@ -1272,6 +1272,21 @@ i915_gem_ringbuffer_submission(struct drm_device *dev, struct drm_file *file,i915_gem_execbuffer_move_to_active (vmas, ring);i915_gem_execbuffer_retire_commands (dev, file, ring, batch_obj); +/* For vlv/chv, modify RC6 promotion timer upon hitting Media workload only +* This will help in better power savings with media scenarios. +*/ +if (((args->flags &I915_EXEC_RING_MASK ) ==I915_EXEC_BSD ) && +IS_VALLEYVIEW (dev) && dev_priv->rps.enabled) { + +vlv_modify_rc6_promotion_timer (dev_priv, true); + +/* Start a timer for 1 sec to reset this value to original */ +mod_delayed_work (dev_priv->wq, + &dev_priv->rps.vlv_media_timeout_work, +msecs_to_jiffies (1000 )); + + } + error:kfree (cliprects);return ret;
drivers/gpu/drm/i915/intel_drv.h +2 -0
@@ -1234,6 +1234,8 @@ void ilk_wm_get_hw_state(struct drm_device *dev);void skl_wm_get_hw_state (struct drm_device *dev);void skl_ddb_get_hw_state (struct drm_i915_private *dev_priv,struct skl_ddb_allocation *ddb/* out */ ); +void vlv_modify_rc6_promotion_timer (struct drm_i915_private *dev_priv, +bool media_active);/* intel_sdvo.c */
drivers/gpu/drm/i915/intel_lrc.c +15 -0
@@ -716,6 +716,21 @@ int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,i915_gem_execbuffer_move_to_active (vmas, ring);i915_gem_execbuffer_retire_commands (dev, file, ring, batch_obj); +/* +* CHV: Extend RC6 promotion timer upon hitting Media workload to help +* increase power savings with media scenarios. +*/ +if (((args->flags &I915_EXEC_RING_MASK ) ==I915_EXEC_BSD ) && +IS_CHERRYVIEW (dev_priv->dev) && dev_priv->rps.enabled) { + +vlv_modify_rc6_promotion_timer (dev_priv, true); + +/* Start a timer for 1 sec to reset this value to original */ +mod_delayed_work (dev_priv->wq, + &dev_priv->rps.vlv_media_timeout_work, +msecs_to_jiffies (1000 )); + } +return 0 ; }
drivers/gpu/drm/i915/intel_pm.c +35 -0
@@ -3941,6 +3941,9 @@ static void cherryview_disable_rps(struct drm_device *dev) {struct drm_i915_private *dev_priv = dev->dev_private; +/* Cancel any pending work-item */ +cancel_delayed_work_sync (&dev_priv->rps.vlv_media_timeout_work); +I915_WRITE (GEN6_RC_CONTROL ,0 ); }
@@ -3952,6 +3955,9 @@ static void valleyview_disable_rps(struct drm_device *dev)* This what the BIOS expects when going into suspend */ intel_uncore_forcewake_get (dev_priv,FORCEWAKE_ALL ); +/* Cancel any pending work-item */ +cancel_delayed_work_sync (&dev_priv->rps.vlv_media_timeout_work); +I915_WRITE (GEN6_RC_CONTROL ,0 );intel_uncore_forcewake_put (dev_priv,FORCEWAKE_ALL );
@@ -4857,6 +4863,32 @@ static void cherryview_enable_rps(struct drm_device *dev)intel_uncore_forcewake_put (dev_priv,FORCEWAKE_ALL ); } +void vlv_modify_rc6_promotion_timer (struct drm_i915_private *dev_priv, +bool media_active) +{ +if (media_active) { +/* TO threshold set to 250 us ( 0xC3 * 1.28 us) */ +I915_WRITE (GEN6_RC6_THRESHOLD ,0xC3 ); + }else { +if (IS_CHERRYVIEW (dev_priv->dev)) { +/* TO threshold set to 500 us ( 0x186 * 1.28 us) */ +I915_WRITE (GEN6_RC6_THRESHOLD ,0x186 ); + }else { +/* TO threshold set to 1750 us ( 0x557 * 1.28 us) */ +I915_WRITE (GEN6_RC6_THRESHOLD ,0x557 ); + } + } +} + +static void vlv_media_timeout_work_func (struct work_struct *work) +{ + struct drm_i915_private *dev_priv = container_of(work, struct drm_i915_private, + rps.vlv_media_timeout_work.work); + +vlv_modify_rc6_promotion_timer (dev_priv, false); +} + +static void valleyview_enable_rps (struct drm_device *dev) {struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6687,5 +6719,8 @@ void intel_pm_setup(struct drm_device *dev)INIT_DELAYED_WORK (&dev_priv->rps.delayed_resume_work, intel_gen6_powersave_work); +INIT_DELAYED_WORK (&dev_priv->rps.vlv_media_timeout_work, + vlv_media_timeout_work_func); + dev_priv->pm.suspended = false; }
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Re: [PATCH 4/5] drm/i915: Modifying RC6 Promotion timer for Media workloads.
Quoted 7 lines · On Thu, Feb 26, 2015 at 08:46:57PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
In normal cases, RC6 promotion timer is 1700us/500us. This will result in more time spent in C1 state. For more residency in C6 in case of media workloads, this is changed to 250us. Not doing this for 3D workloads as too many C6-C0 transition delays can result in performance impact
I would prefer it if you extended intel_mark_busy() to note the source of work, and so extended the busy/idle tracking per-ring with the appropriate hooks for vlv to modify RPS, like how we already do for the general gen6_rps_busy and gen6_rps_idle.
-Chris
Signature · 5 lines
Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH 4/5] drm/i915: Modifying RC6 Promotion timer for Media workloads.
Quoted 8 lines · Chris Wilson
Quoted 7 lines · On Thu, Feb 26, 2015 at 08:46:57PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
In normal cases, RC6 promotion timer is 1700us/500us. This will result in more time spent in C1 state. For more residency in C6 in case of media workloads, this is changed to 250us. Not doing this for 3D workloads as too many C6-C0 transition delays can result in performance impact
Quoted 5 lines
I would prefer it if you extended
intel_mark_busy()to note the source of work, and so extended the busy/idle tracking per-ring with the appropriate hooks for vlv to modify RPS, like how we already do for the generalgen6_rps_busyandgen6_rps_idle.
-Chris
Thanks Chris. Its better to use existing Framework
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PATCH v2 1/1 drm/i915: Modifying RC6 Promotion timer for Media workloads.
From: Deepak S <[email protected]>
In normal cases, RC6 promotion timer is 1700us/500us. This will result in more time spent in C1 state. For more residency in C6 in case of media workloads, this is changed to 250us. Not doing this for 3D workloads as too many C6-C0 transition delays can result in performance impact.
v2: Extend GPU busy & idle detection framework for rc6 Promotion timer changes (Chris)
--- drivers/gpu/drm/i915/i915_gem.c | 10 +++++++++- drivers/gpu/drm/i915/intel_display.c | 3 ++- drivers/gpu/drm/i915/intel_drv.h | 2 ++ drivers/gpu/drm/i915/intel_pm.c | 27 +++++++++++++++++++++++++++ 4 files changed, 40 insertions(+), 2 deletions(-)
drivers/gpu/drm/i915/i915_gem.c +9 -1
@@ -2428,7 +2428,7 @@ int __i915_add_request(struct intel_engine_cs *ring,struct drm_i915_gem_request *request;struct intel_ringbuffer *ringbuf;u32 request_start; -int ret; +int ret, was_empty; request = ring->outstanding_lazy_request;if (WARN_ON (request ==NULL ))
@@ -2495,6 +2495,7 @@ int __i915_add_request(struct intel_engine_cs *ring, } request->emitted_jiffies = jiffies; + was_empty =list_empty (&ring->request_list);list_add_tail (&request->list, &ring->request_list); request->file_priv =NULL ;
@@ -2519,6 +2520,10 @@ int __i915_add_request(struct intel_engine_cs *ring,queue_delayed_work (dev_priv->wq, &dev_priv->mm.retire_work,round_jiffies_up_relative (HZ )); + +if ((ring->id ==VCS ) && was_empty) +vlv_media_promotion_timer_busy (dev_priv); +intel_mark_busy (dev_priv->dev);return 0 ;
@@ -2802,6 +2807,9 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *ring) }WARN_ON (i915_verify_lists (ring->dev)); + +if (ring->id ==VCS &&list_empty (&ring->request_list)) +vlv_media_promotion_timer_idle (dev_priv); }bool
drivers/gpu/drm/i915/intel_display.c +2 -1
@@ -9172,8 +9172,9 @@ void intel_mark_idle(struct drm_device *dev)intel_decrease_pllclock (crtc); } -if (INTEL_INFO (dev)->gen >=6 ) +if (INTEL_INFO (dev)->gen >=6 ) {gen6_rps_idle (dev->dev_private); + } out:intel_runtime_pm_put (dev_priv);
drivers/gpu/drm/i915/intel_drv.h +2 -0
@@ -1233,6 +1233,8 @@ void ironlake_teardown_rc6(struct drm_device *dev);void gen6_update_ring_freq (struct drm_device *dev);void gen6_rps_idle (struct drm_i915_private *dev_priv);void gen6_rps_boost (struct drm_i915_private *dev_priv); +void vlv_media_promotion_timer_idle (struct drm_i915_private *dev_priv); +void vlv_media_promotion_timer_busy (struct drm_i915_private *dev_priv);void ilk_wm_get_hw_state (struct drm_device *dev);void skl_wm_get_hw_state (struct drm_device *dev); void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
drivers/gpu/drm/i915/intel_pm.c +27 -0
@@ -3961,6 +3961,33 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv)mutex_unlock (&dev_priv->rps.hw_lock); } +void vlv_media_promotion_timer_idle (struct drm_i915_private *dev_priv) +{ +struct drm_device *dev = dev_priv->dev; + +if (!IS_VALLEYVIEW (dev)) +return ; + +if (IS_CHERRYVIEW (dev_priv->dev)) { +/* TO threshold set to 500 us ( 0x186 * 1.28 us) */ +I915_WRITE (GEN6_RC6_THRESHOLD ,0x186 ); + }else { +/* TO threshold set to 1750 us ( 0x557 * 1.28 us) */ +I915_WRITE (GEN6_RC6_THRESHOLD ,0x557 ); + } +} + +void vlv_media_promotion_timer_busy (struct drm_i915_private *dev_priv) +{ +struct drm_device *dev = dev_priv->dev; + +if (!IS_VALLEYVIEW (dev)) +return ; + +/* TO threshold set to 250 us ( 0xC3 * 1.28 us) */ +I915_WRITE (GEN6_RC6_THRESHOLD ,0xC3 ); +} +void intel_set_rps (struct drm_device *dev,u8 val) {if (IS_VALLEYVIEW (dev))
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Re: [PATCH v2] drm/i915: Modifying RC6 Promotion timer for Media workloads.
Quoted 8 lines · On Thu, Mar 05, 2015 at 09:27:59PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
In normal cases, RC6 promotion timer is 1700us/500us. This will result in more time spent in C1 state. For more residency in C6 in case of media workloads, this is changed to 250us. Not doing this for 3D workloads as too many C6-C0 transition delays can result in performance impact.
Quoted 4 lines
v2: Extend GPU busy & idle detection framework for rc6 Promotion timer changes (Chris)
Signed-off-by Deepak S <[email protected]>
I've thougth Chris' idea was to put this into the gen6_rps_boost/idle functions? You could check from within them I think for whether the vcs is still busy ... One more comment below.
-Daniel
Quoted 54 lines
--- drivers/gpu/drm/i915/i915_gem.c | 10 +++++++++- drivers/gpu/drm/i915/intel_display.c | 3 ++- drivers/gpu/drm/i915/intel_drv.h | 2 ++ drivers/gpu/drm/i915/intel_pm.c | 27 +++++++++++++++++++++++++++ 4 files changed, 40 insertions(+), 2 deletions(-)drivers/gpu/drm/i915/i915_gem.c +9
-1@@ -2428,7 +2428,7 @@ int __i915_add_request(struct intel_engine_cs *ring,struct drm_i915_gem_request *request;struct intel_ringbuffer *ringbuf;u32 request_start; -int ret; +int ret, was_empty; request = ring->outstanding_lazy_request;if (WARN_ON (request ==NULL ))@@ -2495,6 +2495,7 @@ int __i915_add_request(struct intel_engine_cs *ring, } request->emitted_jiffies = jiffies; + was_empty =list_empty (&ring->request_list);list_add_tail (&request->list, &ring->request_list); request->file_priv =NULL ;@@ -2519,6 +2520,10 @@ int __i915_add_request(struct intel_engine_cs *ring,queue_delayed_work (dev_priv->wq, &dev_priv->mm.retire_work,round_jiffies_up_relative (HZ )); + +if ((ring->id ==VCS ) && was_empty) +vlv_media_promotion_timer_busy (dev_priv); +intel_mark_busy (dev_priv->dev);return 0 ;@@ -2802,6 +2807,9 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *ring) }WARN_ON (i915_verify_lists (ring->dev)); + +if (ring->id ==VCS &&list_empty (&ring->request_list)) +vlv_media_promotion_timer_idle (dev_priv); }bool drivers/gpu/drm/i915/intel_display.c +0
-0
drivers/gpu/drm/i915/intel_display.c void intel_mark_idle(struct drm_device *dev) · line 9177
Quoted 7 lines
drivers/gpu/drm/i915/intel_display.c +2
-1@@ -9172,8 +9172,9 @@ void intel_mark_idle(struct drm_device *dev)intel_decrease_pllclock (crtc); } -if (INTEL_INFO (dev)->gen >=6 ) +if (INTEL_INFO (dev)->gen >=6 ) {gen6_rps_idle (dev->dev_private); + }
Uncessary hunk. And a bikeshed: I think generally if we name something vlv_ we put the platform checks outside of the function. Or have some other guarantee in place to make sure it's only called on the right platforms. Otherwise we generally pick an intel_ prefix.
Quoted 61 lines
drivers/gpu/drm/i915/intel_display.c +0
-0out:intel_runtime_pm_put (dev_priv);drivers/gpu/drm/i915/intel_drv.h +2
-0@@ -1233,6 +1233,8 @@ void ironlake_teardown_rc6(struct drm_device *dev);void gen6_update_ring_freq (struct drm_device *dev);void gen6_rps_idle (struct drm_i915_private *dev_priv);void gen6_rps_boost (struct drm_i915_private *dev_priv); +void vlv_media_promotion_timer_idle (struct drm_i915_private *dev_priv); +void vlv_media_promotion_timer_busy (struct drm_i915_private *dev_priv);void ilk_wm_get_hw_state (struct drm_device *dev);void skl_wm_get_hw_state (struct drm_device *dev); void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,drivers/gpu/drm/i915/intel_pm.c +27
-0@@ -3961,6 +3961,33 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv)mutex_unlock (&dev_priv->rps.hw_lock); } +void vlv_media_promotion_timer_idle (struct drm_i915_private *dev_priv) +{ +struct drm_device *dev = dev_priv->dev; + +if (!IS_VALLEYVIEW (dev)) +return ; + +if (IS_CHERRYVIEW (dev_priv->dev)) { +/* TO threshold set to 500 us ( 0x186 * 1.28 us) */ +I915_WRITE (GEN6_RC6_THRESHOLD ,0x186 ); + }else { +/* TO threshold set to 1750 us ( 0x557 * 1.28 us) */ +I915_WRITE (GEN6_RC6_THRESHOLD ,0x557 ); + } +} + +void vlv_media_promotion_timer_busy (struct drm_i915_private *dev_priv) +{ +struct drm_device *dev = dev_priv->dev; + +if (!IS_VALLEYVIEW (dev)) +return ; + +/* TO threshold set to 250 us ( 0xC3 * 1.28 us) */ +I915_WRITE (GEN6_RC6_THRESHOLD ,0xC3 ); +} +void intel_set_rps (struct drm_device *dev,u8 val) {if (IS_VALLEYVIEW (dev))Signature · 6 lines
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Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH v2] drm/i915: Modifying RC6 Promotion timer for Media workloads.
Quoted 9 lines · Daniel Vetter
Quoted 8 lines · On Thu, Mar 05, 2015 at 09:27:59PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
In normal cases, RC6 promotion timer is 1700us/500us. This will result in more time spent in C1 state. For more residency in C6 in case of media workloads, this is changed to 250us. Not doing this for 3D workloads as too many C6-C0 transition delays can result in performance impact.
Quoted 8 lines
Quoted 4 lines
v2: Extend GPU busy & idle detection framework for rc6 Promotion timer changes (Chris)
Signed-off-by Deepak S <[email protected]>I've thougth Chris' idea was to put this into the gen6_rps_boost/idle functions? You could check from within them I think for whether the vcs is still busy ... One more comment below.
-Daniel
Hi Daniel,
gen6_rps_boost/idle will be called only for RCS right? Also we get gen6_rps_boost during __wait_request But we want to program promotion timer when we add request to VCS to apply the value immediately.
Thanks
Deepak
Quoted 57 lines
Quoted 57 lines
--- drivers/gpu/drm/i915/i915_gem.c | 10 +++++++++- drivers/gpu/drm/i915/intel_display.c | 3 ++- drivers/gpu/drm/i915/intel_drv.h | 2 ++ drivers/gpu/drm/i915/intel_pm.c | 27 +++++++++++++++++++++++++++ 4 files changed, 40 insertions(+), 2 deletions(-)drivers/gpu/drm/i915/i915_gem.c +9
-1@@ -2428,7 +2428,7 @@ int __i915_add_request(struct intel_engine_cs *ring,struct drm_i915_gem_request *request;struct intel_ringbuffer *ringbuf;u32 request_start; -int ret; +int ret, was_empty; request = ring->outstanding_lazy_request;if (WARN_ON (request ==NULL ))@@ -2495,6 +2495,7 @@ int __i915_add_request(struct intel_engine_cs *ring, } request->emitted_jiffies = jiffies; + was_empty =list_empty (&ring->request_list);list_add_tail (&request->list, &ring->request_list); request->file_priv =NULL ;@@ -2519,6 +2520,10 @@ int __i915_add_request(struct intel_engine_cs *ring,queue_delayed_work (dev_priv->wq, &dev_priv->mm.retire_work,round_jiffies_up_relative (HZ )); + +if ((ring->id ==VCS ) && was_empty) +vlv_media_promotion_timer_busy (dev_priv); +intel_mark_busy (dev_priv->dev);return 0 ;@@ -2802,6 +2807,9 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *ring) }WARN_ON (i915_verify_lists (ring->dev)); + +if (ring->id ==VCS &&list_empty (&ring->request_list)) +vlv_media_promotion_timer_idle (dev_priv); }bool drivers/gpu/drm/i915/intel_display.c +0
-0@@ -9172,8 +9172,9 @@ void intel_mark_idle(struct drm_device *dev)intel_decrease_pllclock (crtc); }
Quoted 8 lines
drivers/gpu/drm/i915/intel_display.c void intel_mark_idle(struct drm_device *dev) · line 9177
Quoted 4 lines
drivers/gpu/drm/i915/intel_display.c +2
-1-if (INTEL_INFO (dev)->gen >=6 ) +if (INTEL_INFO (dev)->gen >=6 ) {gen6_rps_idle (dev->dev_private); + }Uncessary hunk. And a bikeshed: I think generally if we name something
vlv_we put the platform checks outside of the function. Or have some other guarantee in place to make sure it's only called on the right platforms. Otherwise we generally pick anintel_prefix.
Thanks Daniel. I will create intel_ prefix, we might need to extend this for future platforms.
Quoted 57 lines
Quoted 57 lines
drivers/gpu/drm/i915/intel_display.c +0
-0out:intel_runtime_pm_put (dev_priv);drivers/gpu/drm/i915/intel_drv.h +2
-0@@ -1233,6 +1233,8 @@ void ironlake_teardown_rc6(struct drm_device *dev);void gen6_update_ring_freq (struct drm_device *dev);void gen6_rps_idle (struct drm_i915_private *dev_priv);void gen6_rps_boost (struct drm_i915_private *dev_priv); +void vlv_media_promotion_timer_idle (struct drm_i915_private *dev_priv); +void vlv_media_promotion_timer_busy (struct drm_i915_private *dev_priv);void ilk_wm_get_hw_state (struct drm_device *dev);void skl_wm_get_hw_state (struct drm_device *dev); void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,drivers/gpu/drm/i915/intel_pm.c +27
-0@@ -3961,6 +3961,33 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv)mutex_unlock (&dev_priv->rps.hw_lock); } +void vlv_media_promotion_timer_idle (struct drm_i915_private *dev_priv) +{ +struct drm_device *dev = dev_priv->dev; + +if (!IS_VALLEYVIEW (dev)) +return ; + +if (IS_CHERRYVIEW (dev_priv->dev)) { +/* TO threshold set to 500 us ( 0x186 * 1.28 us) */ +I915_WRITE (GEN6_RC6_THRESHOLD ,0x186 ); + }else { +/* TO threshold set to 1750 us ( 0x557 * 1.28 us) */ +I915_WRITE (GEN6_RC6_THRESHOLD ,0x557 ); + } +} + +void vlv_media_promotion_timer_busy (struct drm_i915_private *dev_priv) +{ +struct drm_device *dev = dev_priv->dev; + +if (!IS_VALLEYVIEW (dev)) +return ; + +/* TO threshold set to 250 us ( 0xC3 * 1.28 us) */ +I915_WRITE (GEN6_RC6_THRESHOLD ,0xC3 ); +} +void intel_set_rps (struct drm_device *dev,u8 val) {if (IS_VALLEYVIEW (dev))Signature · 1 line
1.9.1
Quoted 4 lines
Quoted 4 lines
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Re: [PATCH v2] drm/i915: Modifying RC6 Promotion timer for Media workloads.
Quoted 21 lines · Deepak S
Quoted 9 lines · Daniel Vetter
Quoted 8 lines · On Thu, Mar 05, 2015 at 09:27:59PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
In normal cases, RC6 promotion timer is 1700us/500us. This will result in more time spent in C1 state. For more residency in C6 in case of media workloads, this is changed to 250us. Not doing this for 3D workloads as too many C6-C0 transition delays can result in performance impact.
Quoted 8 lines
Quoted 4 lines
v2: Extend GPU busy & idle detection framework for rc6 Promotion timer changes (Chris)
Signed-off-by Deepak S <[email protected]>I've thougth Chris' idea was to put this into the gen6_rps_boost/idle functions? You could check from within them I think for whether the vcs is still busy ... One more comment below.
-Daniel
Quoted 4 lines
Hi Daniel,
gen6_rps_boost/idle will be called only for RCS right? Also we get
gen6_rps_boostduring__wait_requestBut we want to program promotion timer when we add request to VCS to apply the value immediately.
It's gen6_rps_busy/gen6_rps_idle. They are called from intel_mark_busy and intel_mark_idle. It is intel_mark_busy/intel_mark_idle that we want to extend to cover the VCS case as well. I think if you add a ring parameter to the functions, we can start specialising per ring and global state changes. You will then also be in a position to judge what is the best idle timer (and consider making i915_gem_idle_work_handler per ring). The goal is simply to evolve the current infrastucture for idle/busyness handling to cover your use case as well (and hopefully in the process improving the old/general cases).
-Chris
Signature · 5 lines
Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH v2] drm/i915: Modifying RC6 Promotion timer for Media workloads.
Quoted 24 lines · Chris Wilson
Quoted 15 lines · Deepak S
Quoted 13 lines · Daniel Vetter
Quoted 12 lines · On Thu, Mar 05, 2015 at 09:27:59PM +0530, [email protected] wrote:
From: Deepak S <[email protected]>
In normal cases, RC6 promotion timer is 1700us/500us. This will result in more time spent in C1 state. For more residency in C6 in case of media workloads, this is changed to 250us. Not doing this for 3D workloads as too many C6-C0 transition delays can result in performance impact.
v2: Extend GPU busy & idle detection framework for rc6 Promotion timer changes (Chris)
Signed-off-by Deepak S <[email protected]>Quoted 8 lines
Quoted 4 lines
I've thougth Chris' idea was to put this into the gen6_rps_boost/idle functions? You could check from within them I think for whether the vcs is still busy ... One more comment below.
-DanielHi Daniel,
gen6_rps_boost/idle will be called only for RCS right? Also we get
gen6_rps_boostduring__wait_requestBut we want to program promotion timer when we add request to VCS to apply the value immediately.
Quoted 11 lines
It's gen6_rps_busy/gen6_rps_idle. They are called from
intel_mark_busyandintel_mark_idle. It is intel_mark_busy/intel_mark_idle that we want to extend to cover the VCS case as well. I think if you add a ring parameter to the functions, we can start specialising per ring and global state changes. You will then also be in a position to judge what is the best idle timer (and consider makingi915_gem_idle_work_handlerper ring). The goal is simply to evolve the current infrastucture for idle/busyness handling to cover your use case as well (and hopefully in the process improving the old/general cases).
-Chris
Thanks Chris. extending intel_mark_busy/intel_mark_idle makes sense. I will work on adding the change
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PATCH 5/5 drm/i915: Setup static bias for GPU
In reply to [email protected]From: Deepak S <[email protected]>
Based on the spec, Setting up static BIAS for GPU to improve the rps performace.
--- drivers/gpu/drm/i915/i915_reg.h | 5 +++++ drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++++++ 2 files changed, 17 insertions(+)
drivers/gpu/drm/i915/i915_reg.h +5 -0
@@ -662,6 +662,11 @@ enum skl_disp_power_wells {#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 +#define VLV_IOSFB_RPS_OVERRIDE 0x04 +#define VLV_OVERRIDE_RPS_MASK 1 +#define VLV_ENABLE_BIAS_SHARE (1 << 1) +#define VLV_BIAS_VAL (6 << 2) +#define VLV_CZ_CLOCK_TO_MILLI_SEC 100000#define VLV_RP_UP_EI_THRESHOLD 90#define VLV_RP_DOWN_EI_THRESHOLD 70
drivers/gpu/drm/i915/intel_pm.c +12 -0
@@ -4841,6 +4841,12 @@ static void cherryview_enable_rps(struct drm_device *dev)GEN6_RP_UP_BUSY_AVG | GEN6_RP_DOWN_IDLE_AVG); +/* Setting Fixed Bias */ + val =VLV_OVERRIDE_RPS_MASK | +VLV_ENABLE_BIAS_SHARE | +VLV_BIAS_VAL ; +vlv_punit_write (dev_priv,VLV_IOSFB_RPS_OVERRIDE , val); + val =vlv_punit_read (dev_priv,PUNIT_REG_GPU_FREQ_STS );/* RPS code assumes GPLL is used */
@@ -4951,6 +4957,12 @@ static void valleyview_enable_rps(struct drm_device *dev)I915_WRITE (GEN6_RC_CONTROL , rc6_mode); +/* Setting Fixed Bias */ + val =VLV_OVERRIDE_RPS_MASK | +VLV_ENABLE_BIAS_SHARE | +VLV_BIAS_VAL ; +vlv_punit_write (dev_priv,VLV_IOSFB_RPS_OVERRIDE , val); + val =vlv_punit_read (dev_priv,PUNIT_REG_GPU_FREQ_STS );/* RPS code assumes GPLL is used */
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Re: [PATCH 5/5] drm/i915: Setup static bias for GPU
Task id: 5840 -------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 282/282 282/282 ILK 308/308 308/308 SNB 326/326 326/326 IVB 379/379 379/379 BYT 294/294 294/294 HSW -1 387/387 386/387 BDW -1 316/316 315/316
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*HSW igt_gem_pwrite_pread_snooped-pwrite-blt-cpu_mmap-performance PASS(2) DMESG_WARN(1)PASS(1)
*BDW igt_gem_gtt_hog PASS(15) DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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