ARM: qcom: cpuidle support for 8064, 8074, 8084
Subsystems (5)
v16 cover ARM: qcom: cpuidle support for 8064, 8074, 8084
Hi,
This patchset is based on common cpuidle driver for ARM and cpuidle_ops changes by Daniel Lezcano [1]. The cpuidle driver supports ARM architecture clockgating (WFI) and the cpu power state (SPC) for the QCOM cpus.
Changes since v15:
https://www.mail-archive.com/devicetree at vger.kernel.org/msg64700.html
- Clean up cpuidle-arm.c to use devm_kzalloc and print error codes.
- Remove qcom,idle-state-stby as a DT mode, instead use the ARM WFI defined in ARM cpuidle driver for clock gating/standby modes. The platform driver will default to standby for all cpus after executing any low power state. This allows us to be completely compatible with generic ARM cpuidle driver and not send out cpu_pm notifications that are sent out for all 'platform states'.
- Cleaned up comments around setting SPM states.
- Platform idle state (SPC) starts at index 1, previous patch was overwritting ARM WFI state, which is mandated to be default state at index 0.
- Removed duplicate cpu_pm_enter() and cpu_pm_exit() callbacks.
- Re-introduce ARM_QCOM_CPUIDLE defconfig item to enable/disable QCOM cpuidle support.
- Update documentation on standby state to indicate that this state is no longer defined in the DT.
- Remove unused qcom,saw2-v1.* compatibles from documentation.
- Rebased on top of SCM changes that were pulled in Kumar's 'soc' branch [2].
- Removed Reviewed-by tags from DT patches due to change in idle states.
Changes since v14:
- Support for cpuidle_ops
- SPM probe changes to register cpuidle
- Rebase on top of 4.0-rc1
- Remove SCM patches from series. Rebased on top of Kumar's tree
- Removed cpuidle-qcom.c in favor of ARM generic cpuidle driver
- Included Daniel's change for supporting creating cpuidle devices by platform
Tested on: 8074, 8084.
Thanks,
Lina
[1]. https://lkml.org/lkml/2015/3/3/271
[2]. https://www.mail-archive.com/linux-kernel at vger.kernel.org/msg847249.html
Daniel Lezcano (1):
ARM: cpuidle: Register per cpuidle device
Lina Iyer (10):
ARM: qcom: Add Subsystem Power Manager (SPM) driver
ARM: cpuidle: qcom: Add documentation for qcom cpuidle states
ARM: cpuidle: Add cpuidle support for QCOM cpus
ARM: dts: qcom: Add power-controller device node for 8074 Krait CPUs
ARM: dts: qcom: Add power-controller device node for 8084 Krait CPUs
ARM: dts: qcom: Update power-controller device node for 8064 Krait
CPUs
ARM: dts: qcom: Add idle states device nodes for 8974/8074
ARM: dts: qcom: Add idle states device nodes for 8084
ARM: dts: qcom: Add idle state device nodes for 8064
ARM: qcom: Update defconfig to enable cpuidle
.../bindings/arm/msm/qcom,idle-state.txt | 84 +++++ .../devicetree/bindings/arm/msm/qcom,saw2.txt | 29 +- arch/arm/boot/dts/qcom-apq8064.dtsi | 30 +- arch/arm/boot/dts/qcom-apq8084.dtsi | 40 +- arch/arm/boot/dts/qcom-msm8974.dtsi | 40 +- arch/arm/configs/qcom_defconfig | 2 + arch/arm/include/asm/cpuidle_ops.h | 5 + drivers/cpuidle/Kconfig.arm | 7 + drivers/cpuidle/cpuidle-arm.c | 39 +- drivers/soc/qcom/Kconfig | 7 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/spm.c | 408 +++++++++++++++++++++ 12 files changed, 674 insertions(+), 18 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt create mode 100644 drivers/soc/qcom/spm.c
Signature · 1 line
2.1.0
PATCH v16 1/11 ARM: cpuidle: Register per cpuidle device
From: Daniel Lezcano <[email protected]>
Some architectures have some cpus which does not support idle states or may be ready to do idle states only when the platform dependencies are probed.
Let the underlying low level code return -ENOSYS when it is not possible to set an idle state at this time.
--- drivers/cpuidle/cpuidle-arm.c | 39 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-)
drivers/cpuidle/cpuidle-arm.c +37 -2
@@ -17,6 +17,9 @@#include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> +#include <linux/slab.h> +#include <linux/device.h> +#include <linux/cpu.h> #include <asm/cpuidle.h>
@@ -93,6 +96,7 @@ static const struct of_device_id arm_idle_state_match[] __initconst = {static int __init arm_idle_init (void ) {int cpu, ret; +struct cpuidle_device *dev;struct cpuidle_driver *drv = &arm_idle_driver;/*
@@ -105,18 +109,49 @@ static int __init arm_idle_init(void)if (ret <=0 )return ret ? : -ENODEV ; + + ret =cpuidle_register_driver (drv); +if (ret) { +pr_err ("Failed to register cpuidle driver\n" ); +return ret; + } +/* * Call arch CPU operations in order to initialize * idle states suspend back-end specific data */ for_each_possible_cpu (cpu) { ret =arm_cpuidle_init (cpu); + +/* +* -ENOSYS: Either the platform driver shall register +* a cpuidle device for this cpu, or there are no +* supported idle states. +*/ +if (ret == -ENOSYS ) +continue ; +if (ret) { -pr_err ("CPU %d failed to init idle CPU ops\n" , cpu); +pr_err ("CPU %d failed to init idle CPU ops, err=%d\n" , + cpu, ret);return ret; } + + dev =devm_kzalloc (get_cpu_device (cpu),sizeof (*dev), +GFP_KERNEL ); +if (!dev) +return -ENOMEM ; + + dev->cpu = cpu; + ret =cpuidle_register_device (dev); +if (ret) { +pr_err ("Failed to register cpuidle device for CPU %d, err=%d\n" , + cpu, ret); +kfree (dev); +continue ; + } } -return cpuidle_register (drv,NULL ); +return ret; }device_initcall (arm_idle_init);
Signature · 1 line
2.1.0
PATCH v16 2/11 ARM: qcom: Add Subsystem Power Manager (SPM) driver
In reply to Lina IyerSPM is a hardware block that controls the peripheral logic surrounding the application cores (cpu/l$). When the core executes WFI instruction, the SPM takes over the putting the core in low power state as configured. The wake up for the SPM is an interrupt at the GIC, which then completes the rest of low power mode sequence and brings the core out of low power mode.
The SPM has a set of control registers that configure the SPMs individually based on the type of the core and the runtime conditions. SPM is a finite state machine block to which a sequence is provided and it interprets the bytes and executes them in sequence. Each low power mode that the core can enter into is provided to the SPM as a sequence.
Configure the SPM to set the core (cpu or L2) into its low power mode, the index of the first command in the sequence is set in the SPM_CTL register. When the core executes ARM wfi instruction, it triggers the SPM state machine to start executing from that index. The SPM state machine waits until the interrupt occurs and starts executing the rest of the sequence until it hits the end of the sequence. The end of the sequence jumps the core out of its low power mode.
Add support for an idle driver to set up the SPM to place the core in Standby or Standalone power collapse mode when the core is idle.
Based on work by: Mahesh Sivasubramanian <[email protected]>, Ai Li <[email protected]>, Praveen Chidambaram <[email protected]> Original tree available at -git://codeaurora.org/quic/la/kernel/msm-3.10.git
--- .../devicetree/bindings/arm/msm/qcom,saw2.txt | 29 +- drivers/soc/qcom/Kconfig | 7 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/spm.c | 408 +++++++++++++++++++++ 4 files changed, 439 insertions(+), 6 deletions(-) create mode 100644 drivers/soc/qcom/spm.c
Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt +23 -6
@@ -2,11 +2,20 @@ SPM AVS Wrapper 2 (SAW2) The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable -micro-controller that transitions a piece of hardware (like a processor or +power-controller that transitions a piece of hardware (like a processor or subsystem) into and out of low power modes via a direct connection to the PMIC. It can also be wired up to interact with other processors in the system, notifying them when a low power state is entered or exited. +Multiple revisions of the SAW hardware are supported using these Device Nodes. +SAW2 revisions differ in the register offset and configuration data. Also, the +same revision of the SAW in different SoCs may have different configuration +data due the the differences in hardware capabilities. Hence the SoC name, the +version of the SAW hardware in that SoC and the distinction between cpu (big +or Little) or cache, may be needed to uniquely identify the SAW register +configuration and initialization data. The compatible string is used to +indicate this parameter. + PROPERTIES - compatible:
@@ -14,10 +23,11 @@ PROPERTIES Value type: <string> Definition: shall contain "qcom,saw2". A more specific value should be one of: - "qcom,saw2-v1" - "qcom,saw2-v1.1" - "qcom,saw2-v2" - "qcom,saw2-v2.1" + "qcom,saw2-v2" + "qcom,saw2-v2.1" + "qcom,apq8064-saw2-v1.1-cpu" + "qcom,msm8974-saw2-v2.1-cpu" + "qcom,apq8084-saw2-v2.1-cpu" - reg: Usage: required
@@ -26,10 +36,17 @@ PROPERTIES the register region. An optional second element specifies the base address and size of the alias register region. +- regulator: + Usage: optional + Value type: boolean + Definition: Indicates that this SPM device acts as a regulator device + device for the core (CPU or Cache) the SPM is attached + to. Example: - regulator at 2099000 { + power-controller at 2099000 { compatible = "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; + regulator; };
drivers/soc/qcom/Kconfig +7 -0
@@ -9,3 +9,10 @@ config QCOM_GSBI functions for connecting the underlying serial UART, SPI, and I2C devices to the output pins. +config QCOM_PM + bool "Qualcomm Power Management" + depends on ARCH_QCOM + help + QCOM Platform specific power driver to manage cores and L2 low power + modes. It interface with various system drivers to put the cores in + low power modes.
drivers/soc/qcom/Makefile +1 -0
@@ -1 +1,2 @@ obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o +obj-$(CONFIG_QCOM_PM) += spm.o
drivers/soc/qcom/spm.c new file +408 -0
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Signature · 1 line
2.1.0
PATCH v16 3/11 ARM: cpuidle: qcom: Add documentation for qcom cpuidle states
In reply to Lina IyerAdd documentation for cpuidle states of QCOM cpus. In addition to arm-idle-state compatible string, the ARM idle state definition must define one of the following compatible strings -
"qcom,idle-state-ret", "qcom,idle-state-spc", "qcom,idle-state-pc",
The compatibles helps the SPM platform driver to use the correct idle function when the index to the idle state is passed to the platform driver.
--- .../bindings/arm/msm/qcom,idle-state.txt | 84 ++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt
Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt new file +84 -0
@@ -0,0 +1,84 @@ +QCOM Idle States for cpuidle driver + +ARM provides idle-state node to define the cpuidle states, as defined in [1]. +cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle +states. Idle states have different enter/exit latency and residency values. +The idle states supported by the QCOM SoC are defined as - + + * Standby + * Retention + * Standalone Power Collapse (Standalone PC or SPC) + * Power Collapse (PC) + +Standby: Standby does a little more in addition to architectural clock gating. +When the WFI instruction is executed the ARM core would gate its internal +clocks. In addition to gating the clocks, QCOM cpus use this instruction as a +trigger to execute the SPM state machine. The SPM state machine waits for the +interrupt to trigger the core back in to active. This triggers the cache +hierarchy to enter standby states, when all cpus are idle. An interrupt brings +the SPM state machine out of its wait, the next step is to ensure that the +cache hierarchy is also out of standby, and then the cpu is allowed to resume +execution. This state is defined as a generic ARM WFI state by the ARM cpuidle +driver and is not defined in the DT. The SPM state machine should be +configured to execute this state by default and after executing every other +state below. + +Retention: Retention is a low power state where the core is clock gated and +the memory and the registers associated with the core are retained. The +voltage may be reduced to the minimum value needed to keep the processor +registers active. The SPM should be configured to execute the retention +sequence and would wait for interrupt, before restoring the cpu to execution +state. Retention may have a slightly higher latency than Standby. + +Standalone PC: A cpu can power down and warmboot if there is a sufficient time +between the time it enters idle and the next known wake up. SPC mode is used +to indicate a core entering a power down state without consulting any other +cpu or the system resources. This helps save power only on that core. The SPM +sequence for this idle state is programmed to power down the supply to the +core, wait for the interrupt, restore power to the core, and ensure the +system state including cache hierarchy is ready before allowing core to +resume. Applying power and resetting the core causes the core to warmboot +back into Elevation Level (EL) which trampolines the control back to the +kernel. Entering a power down state for the cpu, needs to be done by trapping +into a EL. Failing to do so, would result in a crash enforced by the warm boot +code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to +be flushed in s/w, before powering down the core. + +Power Collapse: This state is similar to the SPC mode, but distinguishes +itself in that the cpu acknowledges and permits the SoC to enter deeper sleep +modes. In a hierarchical power domain SoC, this means L2 and other caches can +be flushed, system bus, clocks - lowered, and SoC main XO clock gated and +voltages reduced, provided all cpus enter this state. Since the span of low +power modes possible at this state is vast, the exit latency and the residency +of this low power mode would be considered high even though at a cpu level, +this essentially is cpu power down. The SPM in this state also may handshake +with the Resource power manager (RPM) processor in the SoC to indicate a +complete application processor subsystem shut down. + +The idle-state for QCOM SoCs are distinguished by the compatible property of +the idle-states device node. + +The devicetree representation of the idle state should be - + +Required properties: + +- compatible: Must be one of - + "qcom,idle-state-ret", + "qcom,idle-state-spc", + "qcom,idle-state-pc", + and "arm,idle-state". + +Other required and optional properties are specified in [1]. + +Example: + + idle-states { + CPU_SPC: spc { + compatible = "qcom,idle-state-spc", "arm,idle-state"; + entry-latency-us = <150>; + exit-latency-us = <200>; + min-residency-us = <2000>; + }; + }; + +[1]. Documentation/devicetree/bindings/arm/idle-states.txt
Signature · 1 line
2.1.0
PATCH v16 4/11 ARM: cpuidle: Add cpuidle support for QCOM cpus
In reply to Lina IyerRegister cpuidle ops for Krait Processor Sub-System. Supports v1 and v2 versions of KPSS.
Define ARM_QCOM_CPUIDLE config item to enable cpuidle support.
--- arch/arm/include/asm/cpuidle_ops.h | 5 +++++ drivers/cpuidle/Kconfig.arm | 7 +++++++ 2 files changed, 12 insertions(+)
arch/arm/include/asm/cpuidle_ops.h +5 -0
@@ -1,3 +1,8 @@/* * List of cpuidle operations */ + +#if IS_ENABLED (CONFIG_ARM_QCOM_CPUIDLE ) +CPUIDLE_OPS(qcom_kpss_v1) +CPUIDLE_OPS(qcom_kpss_v2) +#endif
drivers/cpuidle/Kconfig.arm +7 -0
@@ -75,3 +75,10 @@ config ARM_MVEBU_V7_CPUIDLE depends on ARCH_MVEBU help Select this to enable cpuidle on Armada 370, 38x and XP processors. + +config ARM_QCOM_CPUIDLE + bool "CPU Idle Driver for QCOM processors" + depends on ARCH_QCOM + select ARM_CPUIDLE + help + Select this to enable cpuidle on QCOM processors.
Signature · 1 line
2.1.0
PATCH v16 5/11 ARM: dts: qcom: Add power-controller device node for 8074 Krait CPUs
In reply to Lina IyerEach Krait CPU in the QCOM 8074/8974 SoC has an SAW power controller to regulate the power to the cpu and aide the core in entering idle states. Reference the SAW instance and associate the instance with the CPU core.
--- arch/arm/boot/dts/qcom-msm8974.dtsi | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-)
arch/arm/boot/dts/qcom-msm8974.dtsi +25 -1
@@ -21,6 +21,7 @@ reg = <0>; next-level-cache = <&L2>; qcom,acc = <&acc0>; + qcom,saw = <&saw0>; }; cpu at 1 {
@@ -30,6 +31,7 @@ reg = <1>; next-level-cache = <&L2>; qcom,acc = <&acc1>; + qcom,saw = <&saw1>; }; cpu at 2 {
@@ -39,6 +41,7 @@ reg = <2>; next-level-cache = <&L2>; qcom,acc = <&acc2>; + qcom,saw = <&saw2>; }; cpu at 3 {
@@ -48,6 +51,7 @@ reg = <3>; next-level-cache = <&L2>; qcom,acc = <&acc3>; + qcom,saw = <&saw3>; }; L2: l2-cache {
@@ -144,7 +148,27 @@ }; }; - saw_l2: regulator at f9012000 { + saw0: power-controller at f9089000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu"; + reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; + }; + + saw1: power-controller at f9099000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu"; + reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; + }; + + saw2: power-controller at f90a9000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu"; + reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; + }; + + saw3: power-controller at f90b9000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu"; + reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; + }; + + saw_l2: power-controller at f9012000 { compatible = "qcom,saw2"; reg = <0xf9012000 0x1000>; regulator;
Signature · 1 line
2.1.0
PATCH v16 6/11 ARM: dts: qcom: Add power-controller device node for 8084 Krait CPUs
In reply to Lina IyerEach Krait CPU in the QCOM 8084 SoC has an SAW power controller to regulate the power to the cpu and aide the core in entering idle states. Reference the SAW instance and associate the instance with the CPU core.
--- arch/arm/boot/dts/qcom-apq8084.dtsi | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-)
arch/arm/boot/dts/qcom-apq8084.dtsi +25 -1
@@ -21,6 +21,7 @@ enable-method = "qcom,kpss-acc-v2"; next-level-cache = <&L2>; qcom,acc = <&acc0>; + qcom,saw = <&saw0>; }; cpu at 1 {
@@ -30,6 +31,7 @@ enable-method = "qcom,kpss-acc-v2"; next-level-cache = <&L2>; qcom,acc = <&acc1>; + qcom,saw = <&saw1>; }; cpu at 2 {
@@ -39,6 +41,7 @@ enable-method = "qcom,kpss-acc-v2"; next-level-cache = <&L2>; qcom,acc = <&acc2>; + qcom,saw = <&saw2>; }; cpu at 3 {
@@ -48,6 +51,7 @@ enable-method = "qcom,kpss-acc-v2"; next-level-cache = <&L2>; qcom,acc = <&acc3>; + qcom,saw = <&saw3>; }; L2: l2-cache {
@@ -144,7 +148,27 @@ }; }; - saw_l2: regulator at f9012000 { + saw0: power-controller at f9089000 { + compatible = "qcom,apq8084-saw2-v2.1-cpu"; + reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; + }; + + saw1: power-controller at f9099000 { + compatible = "qcom,apq8084-saw2-v2.1-cpu"; + reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; + }; + + saw2: power-controller at f90a9000 { + compatible = "qcom,apq8084-saw2-v2.1-cpu"; + reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; + }; + + saw3: power-controller at f90b9000 { + compatible = "qcom,apq8084-saw2-v2.1-cpu"; + reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; + }; + + saw_l2: power-controller at f9012000 { compatible = "qcom,saw2"; reg = <0xf9012000 0x1000>; regulator;
Signature · 1 line
2.1.0
PATCH v16 7/11 ARM: dts: qcom: Update power-controller device node for 8064 Krait CPUs
In reply to Lina IyerUpdate the SAW2 DT bindings to add qcom,apq8064-saw2-v1.1-cpu compatible binding string to configure SPM registers and allow the SPM to put the core in deeper idle states when the core is idle.
--- arch/arm/boot/dts/qcom-apq8064.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)
arch/arm/boot/dts/qcom-apq8064.dtsi +8 -8
@@ -139,26 +139,26 @@ reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; }; - saw0: regulator at 2089000 { - compatible = "qcom,saw2"; + saw0: power-controller at 2089000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw1: regulator at 2099000 { - compatible = "qcom,saw2"; + saw1: power-controller at 2099000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw2: regulator at 20a9000 { - compatible = "qcom,saw2"; + saw2: power-controller at 20a9000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw3: regulator at 20b9000 { - compatible = "qcom,saw2"; + saw3: power-controller at 20b9000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; regulator; };
Signature · 1 line
2.1.0
PATCH v16 8/11 ARM: dts: qcom: Add idle states device nodes for 8974/8074
In reply to Lina IyerAdd ARM common idle states device bindings for cpuidle support for APQ 8974/8074.
Support Standalone power collapse (SPC) idle state (power down that does not affect any SoC idle states) for each cpu.
--- arch/arm/boot/dts/qcom-msm8974.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
arch/arm/boot/dts/qcom-msm8974.dtsi +14 -0
@@ -22,6 +22,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; + cpu-idle-states = <&CPU_SPC>; }; cpu at 1 {
@@ -32,6 +33,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; + cpu-idle-states = <&CPU_SPC>; }; cpu at 2 {
@@ -42,6 +44,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; + cpu-idle-states = <&CPU_SPC>; }; cpu at 3 {
@@ -52,6 +55,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; + cpu-idle-states = <&CPU_SPC>; }; L2: l2-cache {
@@ -59,6 +63,16 @@ cache-level = <2>; qcom,saw = <&saw_l2>; }; + + idle-states { + CPU_SPC: spc { + compatible = "qcom,idle-state-spc", + "arm,idle-state"; + entry-latency-us = <150>; + exit-latency-us = <200>; + min-residency-us = <2000>; + }; + }; }; cpu-pmu {
Signature · 1 line
2.1.0
PATCH v16 9/11 ARM: dts: qcom: Add idle states device nodes for 8084
In reply to Lina IyerAdd ARM common idle states device bindings for cpuidle support for APQ 8084.
Support Standalone power collapse (SPC) idle state (power down that does not affect any SoC idle states) for each cpu.
--- arch/arm/boot/dts/qcom-apq8084.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
arch/arm/boot/dts/qcom-apq8084.dtsi +14 -0
@@ -22,6 +22,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; + cpu-idle-states = <&CPU_SPC>; }; cpu at 1 {
@@ -32,6 +33,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; + cpu-idle-states = <&CPU_SPC>; }; cpu at 2 {
@@ -42,6 +44,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; + cpu-idle-states = <&CPU_SPC>; }; cpu at 3 {
@@ -52,6 +55,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; + cpu-idle-states = <&CPU_SPC>; }; L2: l2-cache {
@@ -59,6 +63,16 @@ cache-level = <2>; qcom,saw = <&saw_l2>; }; + + idle-states { + CPU_SPC: spc { + compatible = "qcom,idle-state-spc", + "arm,idle-state"; + entry-latency-us = <150>; + exit-latency-us = <200>; + min-residency-us = <2000>; + }; + }; }; cpu-pmu {
Signature · 1 line
2.1.0
PATCH v16 10/11 ARM: dts: qcom: Add idle state device nodes for 8064
In reply to Lina IyerAdd ARM common idle state device bindings for cpuidle support for APQ 8064.
Support Standalone power collapse (SPC) idle state (power down that does not affect any SoC idle states) for each cpu.
--- arch/arm/boot/dts/qcom-apq8064.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
arch/arm/boot/dts/qcom-apq8064.dtsi +14 -0
@@ -23,6 +23,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; + cpu-idle-states = <&CPU_SPC>; }; cpu at 1 {
@@ -33,6 +34,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; + cpu-idle-states = <&CPU_SPC>; }; cpu at 2 {
@@ -43,6 +45,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; + cpu-idle-states = <&CPU_SPC>; }; cpu at 3 {
@@ -53,12 +56,23 @@ next-level-cache = <&L2>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; + cpu-idle-states = <&CPU_SPC>; }; L2: l2-cache { compatible = "cache"; cache-level = <2>; }; + + idle-states { + CPU_SPC: spc { + compatible = "qcom,idle-state-spc", + "arm,idle-state"; + entry-latency-us = <400>; + exit-latency-us = <900>; + min-residency-us = <3000>; + }; + }; }; cpu-pmu {
Signature · 1 line
2.1.0
PATCH v16 11/11 ARM: qcom: Update defconfig to enable cpuidle
In reply to Lina IyerUpdate defconfig to allow cpuidle for QCOM cpus.
* Enable QCOM_PM
* Enable ARM_QCOM_CPUIDLE
--- arch/arm/configs/qcom_defconfig | 2 ++ 1 file changed, 2 insertions(+)
arch/arm/configs/qcom_defconfig +2 -0
@@ -30,6 +30,7 @@ CONFIG_CLEANCACHE=y CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_CPU_IDLE=y +CONFIG_ARM_QCOM_CPUIDLE=y CONFIG_VFP=y CONFIG_NEON=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
@@ -135,6 +136,7 @@ CONFIG_DMADEVICES=y CONFIG_QCOM_BAM_DMA=y CONFIG_STAGING=y CONFIG_QCOM_GSBI=y +CONFIG_QCOM_PM=y CONFIG_COMMON_CLK_QCOM=y CONFIG_APQ_MMCC_8084=y CONFIG_IPQ_GCC_806X=y
Signature · 1 line
2.1.0
v16 cover ARM: qcom: cpuidle support for 8064, 8074, 8084
In reply to Lina IyerOn Tue, Mar 17, 2015 at 04:33:40PM -0600, Lina Iyer wrote:
<snip>
Quoted 3 lines
Tested on: 8074, 8084.
These worked fine for me on IPQ8064 (ap148), however I did have to add my own DT entries for the idle states and saw changes.
Also tested on APQ8064 (ifc6410).
Signature · 3 lines
Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
v16 cover ARM: qcom: cpuidle support for 8064, 8074, 8084
Quoted 8 lines · Andy Gross
On Tue, Mar 17, 2015 at 04:33:40PM -0600, Lina Iyer wrote:
<snip>
Quoted 3 lines
Tested on: 8074, 8084.
Quoted 6 lines
These worked fine for me on IPQ8064 (ap148), however I did have to add my own DT entries for the idle states and saw changes.
Also tested on APQ8064 (ifc6410).
Tested-by Andy Gross <[email protected]>
Thanks Andy.
Quoted 5 lines
Signature · 4 lines
-- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project