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ARM: sunxi: SRAM mapping support

RFC PATCH Superseded Maxime Ripard 2 participants 6 messages Mar 12, 2015 – Mar 20, 2015

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#0 lore raw

cover ARM: sunxi: SRAM mapping support

Hi,

The Allwinner SoCs all have a bunch of SRAMs (the exact number depending on the SoC itself) that can all be mapped to the CPU or to a bunch of devices, each SRAM having different possible devices to be mapped to.

Since this SRAM setup is highly SoC dependant, relying on syscon would put to much duplicated logic to devices that are using these SRAMs, among which the USB OTG and EMAC controllers.

Here is an RFC to introduce a custom API to control the mapping of these SRAM, ideally in a SoC-independant way.

Let me know what you think,
Maxime

Maxime Ripard (3):
drivers: soc: sunxi: Introduce SoC driver to map SRAMs
ARM: sun7i: Add A20 SRAM and SRAM controller
net: allwinner: emac: Claim our SRAM

 arch/arm/boot/dts/sun7i-a20.dtsi            |  31 +++-
 drivers/net/ethernet/allwinner/sun4i-emac.c |  13 +-
 drivers/soc/Kconfig                         |   1 +
 drivers/soc/Makefile                        |   1 +
 drivers/soc/sunxi/Kconfig                   |  12 ++
 drivers/soc/sunxi/Makefile                  |   1 +
 drivers/soc/sunxi/sunxi_sram.c              | 234 ++++++++++++++++++++++++++++
 include/linux/soc/sunxi/sunxi_sram.h        |  24 +++
 8 files changed, 314 insertions(+), 3 deletions(-)
 create mode 100644 drivers/soc/sunxi/Kconfig
 create mode 100644 drivers/soc/sunxi/Makefile
 create mode 100644 drivers/soc/sunxi/sunxi_sram.c
 create mode 100644 include/linux/soc/sunxi/sunxi_sram.h
Signature · 1 line
2.3.1
#1 lore raw

RFC PATCH 1/3 drivers: soc: sunxi: Introduce SoC driver to map SRAMs

The Allwinner SoCs have a handful of SRAM that can be either mapped to be accessible by devices or the CPU.

That mapping is controlled by an SRAM controller, and that mapping might not be set by the bootloader, for example if the device wasn't used at all, or if we're using solutions like the U-Boot's Falcon Boot.

We could also imagine changing this at runtime for example to change the mapping of these SRAMs to use them for suspend/resume or runtime memory rate change, if that ever happens.

These use cases require some API in the kernel to control that mapping, exported through a drivers/soc driver.

This driver also implement a debugfs file that shows the SRAM found in the system, the current mapping and the SRAM that have been claimed by some drivers in the kernel.

---
 drivers/soc/Kconfig                  |   1 +
 drivers/soc/Makefile                 |   1 +
 drivers/soc/sunxi/Kconfig            |  12 ++
 drivers/soc/sunxi/Makefile           |   1 +
 drivers/soc/sunxi/sunxi_sram.c       | 234 +++++++++++++++++++++++++++++++++++
 include/linux/soc/sunxi/sunxi_sram.h |  24 ++++
 6 files changed, 273 insertions(+)
 create mode 100644 drivers/soc/sunxi/Kconfig
 create mode 100644 drivers/soc/sunxi/Makefile
 create mode 100644 drivers/soc/sunxi/sunxi_sram.c
 create mode 100644 include/linux/soc/sunxi/sunxi_sram.h
drivers/soc/Kconfig +1 -0
index 76d6bd4da138..5d0f55dc88c1 100644
@@ -1,6 +1,7 @@
 menu "SOC (System On Chip) specific Drivers"
 
 source "drivers/soc/qcom/Kconfig"
+source "drivers/soc/sunxi/Kconfig"
 source "drivers/soc/ti/Kconfig"
 source "drivers/soc/versatile/Kconfig"
 
drivers/soc/Makefile +1 -0
index 063113d0bd38..170bba37f092 100644
@@ -3,6 +3,7 @@
 #
 
 obj-$(CONFIG_ARCH_QCOM)		+= qcom/
+obj-$(CONFIG_ARCH_SUNXI)	+= sunxi/
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
 obj-$(CONFIG_SOC_TI)		+= ti/
 obj-$(CONFIG_PLAT_VERSATILE)	+= versatile/
drivers/soc/sunxi/Kconfig new file +12 -0
new file mode 100644
index 000000000000..212c6340097a
@@ -0,0 +1,12 @@
+#
+# Allwinner sunXi SoC drivers
+#
+config SUNXI_SRAM
+        tristate "Allwinner sunXi SRAM Controller"
+        depends on ARCH_SUNXI
+	default y
+        help
+          Say y here to enable the SRAM controller support. This
+          device is responsible on mapping the SRAM in the sunXi SoCs
+          wether to the CPU/DMA, or to the devices.
+
drivers/soc/sunxi/Makefile new file +1 -0
new file mode 100644
index 000000000000..4cf9dbdf346e
@@ -0,0 +1 @@
+obj-$(CONFIG_SUNXI_SRAM) +=	sunxi_sram.o
drivers/soc/sunxi/sunxi_sram.c new file +234 -0

234 lines not on this page · raw message

include/linux/soc/sunxi/sunxi_sram.h new file +24 -0
new file mode 100644
index 000000000000..351c31a105c8
@@ -0,0 +1,24 @@
+/*
+ * Allwinner SoCs SRAM Controller Driver
+ *
+ * Copyright (C) 2015 Maxime Ripard
+ *
+ * Author: Maxime Ripard <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef _SUNXI_SRAM_H_
+#define _SUNXI_SRAM_H_
+
+enum sunxi_sram_type {
+	SUNXI_SRAM_USB_OTG,
+	SUNXI_SRAM_EMAC,
+};
+
+int sunxi_sram_claim(enum sunxi_sram_type type, const char *function);
+int sunxi_sram_release(enum sunxi_sram_type type);
+
+#endif /* _SUNXI_SRAM_H_ */
Signature · 1 line
2.3.1
#2 lore raw

RFC PATCH 2/3 ARM: sun7i: Add A20 SRAM and SRAM controller

In reply to Maxime Ripard

The A20 has a few SRAM that can be mapped either to a device or to the CPU, with the mapping being controlled by an SRAM controller.

Since most of the time these SRAM won't be accessible by the CPU, we can't use the mmio-sram driver and compatible.

---
 arch/arm/boot/dts/sun7i-a20.dtsi | 31 ++++++++++++++++++++++++++++++-
 1 file changed, 30 insertions(+), 1 deletion(-)
arch/arm/boot/dts/sun7i-a20.dtsi +30 -1
index a1ebd80e6f24..a249828a1df5 100644
@@ -522,12 +522,41 @@
 		};
 	};
 
-	soc at 01c00000 {
+	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
 
+		sram at 00000000 {
+			compatible = "allwinner,sun4i-a10-sram";
+			reg = <0x00000000 0x4000>;
+			allwinner,sram-name = "A1";
+		};
+
+		sram at 00004000 {
+			compatible = "allwinner,sun4i-a10-sram";
+			reg = <0x00004000 0x4000>;
+			allwinner,sram-name = "A2";
+		};
+
+		sram at 00008000 {
+			compatible = "allwinner,sun4i-a10-sram";
+			reg = <0x00008000 0x4000>;
+			allwinner,sram-name = "A3-A4";
+		};
+
+		sram at 00010000 {
+			compatible = "allwinner,sun4i-a10-sram";
+			reg = <0x00010000 0x1000>;
+			allwinner,sram-name = "D";
+		};
+
+		sram-controller at 01c00000 {
+			compatible = "allwinner,sun7i-a20-sram-controller";
+			reg = <0x01c00000 0x30>;
+		};
+
 		nmi_intc: interrupt-controller at 01c00030 {
 			compatible = "allwinner,sun7i-a20-sc-nmi";
 			interrupt-controller;
Signature · 1 line
2.3.1
#3 lore raw

RFC PATCH 2/3 ARM: sun7i: Add A20 SRAM and SRAM controller

Hi,

Quoted 16 lines · Maxime Ripard

The A20 has a few SRAM that can be mapped either to a device or to the CPU, with the mapping being controlled by an SRAM controller.

Since most of the time these SRAM won't be accessible by the CPU, we can't use the mmio-sram driver and compatible.

---
  arch/arm/boot/dts/sun7i-a20.dtsi | 31 ++++++++++++++++++++++++++++++-
  1 file changed, 30 insertions(+), 1 deletion(-)
arch/arm/boot/dts/sun7i-a20.dtsi +0 -0
index a1ebd80e6f24..a249828a1df5 100644

arch/arm/boot/dts/sun7i-a20.dtsi line 525

Quoted 5 lines
arch/arm/boot/dts/sun7i-a20.dtsi +1 -1
@@ -522,12 +522,41 @@
  		};
  	};
 
-	soc at 01c00000 {
+	soc {

Please do not do this, this changes devicetree paths used by u-boot, see:

http://git.denx.de/?p=u-boot.git;a=blob;f=include/configs/sunxi-common.h#l232

Other then that this sets looks good to me, I'm giving it a test-spin now.

Regards,

Hans

Quoted 38 lines
arch/arm/boot/dts/sun7i-a20.dtsi +29 -0
  		compatible = "simple-bus";
  		#address-cells = <1>;
  		#size-cells = <1>;
  		ranges;
 
+		sram at 00000000 {
+			compatible = "allwinner,sun4i-a10-sram";
+			reg = <0x00000000 0x4000>;
+			allwinner,sram-name = "A1";
+		};
+
+		sram at 00004000 {
+			compatible = "allwinner,sun4i-a10-sram";
+			reg = <0x00004000 0x4000>;
+			allwinner,sram-name = "A2";
+		};
+
+		sram at 00008000 {
+			compatible = "allwinner,sun4i-a10-sram";
+			reg = <0x00008000 0x4000>;
+			allwinner,sram-name = "A3-A4";
+		};
+
+		sram at 00010000 {
+			compatible = "allwinner,sun4i-a10-sram";
+			reg = <0x00010000 0x1000>;
+			allwinner,sram-name = "D";
+		};
+
+		sram-controller at 01c00000 {
+			compatible = "allwinner,sun7i-a20-sram-controller";
+			reg = <0x01c00000 0x30>;
+		};
+
  		nmi_intc: interrupt-controller at 01c00030 {
  			compatible = "allwinner,sun7i-a20-sc-nmi";
  			interrupt-controller;
#4 lore raw

RFC PATCH 2/3 ARM: sun7i: Add A20 SRAM and SRAM controller

Quoted 22 lines · Hans de Goede

Hi,

Quoted 19 lines · Maxime Ripard

The A20 has a few SRAM that can be mapped either to a device or to the CPU, with the mapping being controlled by an SRAM controller.

Since most of the time these SRAM won't be accessible by the CPU, we can't use the mmio-sram driver and compatible.

---
 arch/arm/boot/dts/sun7i-a20.dtsi | 31 ++++++++++++++++++++++++++++++-
 1 file changed, 30 insertions(+), 1 deletion(-)
arch/arm/boot/dts/sun7i-a20.dtsi +0 -0
index a1ebd80e6f24..a249828a1df5 100644
@@ -522,12 +522,41 @@
 		};
 	};
 
Quoted 7 lines

arch/arm/boot/dts/sun7i-a20.dtsi line 525

Quoted 2 lines
arch/arm/boot/dts/sun7i-a20.dtsi +1 -1
-	soc at 01c00000 {
+	soc {

Please do not do this, this changes devicetree paths used by u-boot, see:

http://git.denx.de/?p=u-boot.git;a=blob;f=include/configs/sunxi-common.h#l232

Ah, I didn't think about that. That's unfortunate, since the SRAM start lower than this address, but I guess we'll have to live with that :)

Thanks!
Maxime

Signature · 10 lines
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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#5 lore raw

RFC PATCH 3/3 net: allwinner: emac: Claim our SRAM

In reply to Maxime Ripard

The SRAM the EMAC is using might not have been mapped accordingly by the bootloader, preventing the EMAC to work properly.

Ask for that SRAM to be mapped at probe time to make sure that this never happens.

---
 drivers/net/ethernet/allwinner/sun4i-emac.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)
drivers/net/ethernet/allwinner/sun4i-emac.c +11 -2
index f3470d96837a..9d0136b1fab8 100644
@@ -29,6 +29,8 @@
 #include <linux/platform_device.h>
 #include <linux/phy.h>
 
+#include <linux/soc/sunxi/sunxi_sram.h>
+
 #include "sun4i-emac.h"
 
 #define DRV_NAME		"sun4i-emac"
@@ -857,11 +859,15 @@ static int emac_probe(struct platform_device *pdev)
 
 	clk_prepare_enable(db->clk);
 
+	ret = sunxi_sram_claim(SUNXI_SRAM_EMAC, "emac");
+	if (ret)
+		dev_warn(&pdev->dev, "Couldn't map SRAM to device\n");
+
 	db->phy_node = of_parse_phandle(np, "phy", 0);
 	if (!db->phy_node) {
 		dev_err(&pdev->dev, "no associated PHY\n");
 		ret = -ENODEV;
-		goto out;
+		goto out_release_sram;
 	}
 
 	/* Read MAC-address from DT */
@@ -893,7 +899,7 @@ static int emac_probe(struct platform_device *pdev)
 	if (ret) {
 		dev_err(&pdev->dev, "Registering netdev failed!\n");
 		ret = -ENODEV;
-		goto out;
+		goto out_release_sram;
 	}
 
 	dev_info(&pdev->dev, "%s: at %p, IRQ %d MAC: %pM\n",
@@ -901,6 +907,8 @@ static int emac_probe(struct platform_device *pdev)
 
 	return 0;
 
+out_release_sram:
+	sunxi_sram_release(SUNXI_SRAM_EMAC);
 out:
 	dev_err(db->dev, "not found (%d).\n", ret);
 
@@ -914,6 +922,7 @@ static int emac_remove(struct platform_device *pdev)
 	struct net_device *ndev = platform_get_drvdata(pdev);
 
 	unregister_netdev(ndev);
+	sunxi_sram_release(SUNXI_SRAM_EMAC);
 	free_netdev(ndev);
 
 	dev_dbg(&pdev->dev, "released and freed device\n");
Signature · 1 line
2.3.1