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edac: Add APM X-Gene SoC EDAC driver

PATCH Superseded Loc Ho 3 participants 11 messages Mar 17, 2015 – Apr 24, 2015

Subsystems (5)
Device tree bindings arm64 EDAC-core Applied micro (apm) x-gene device tree support +1 more subsystems

v6 of 11 Superseded Latest is v11 →

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Loc Ho

author
#0 lore raw

v6 cover edac: Add APM X-Gene SoC EDAC driver

This patch adds support for the APM X-Gene SoC EDAC driver for DT.

v6:
* Rebase to 4.0.0-rc3
* Add memory scrub stub function and enable ARM64 EDAC support patch
* Add bit definition defines for L2RTOS registers
* Remove un-necessary clearing of all L1/L2 software generated registers
* Remove wrong notification of LSU un-correctable error
* Change L2 reporting of un-correcable error to correctable error
* Change clearing of the L2C L2RTO registers
* Add support for L2 HW version 1 and version 2 or above
* Add support for L3 HW version 1 and version 2 or above

v5:
* Rebase to 3.17.rc1 (next)
* Update binding documentation for additional SoC node binding resource
* Enable MCU correctable and uncorrectable interrupts if not enabled by firmware
* Enable top level interrupt only after all MCU registered. Otherwise, error interrupt will never get cleared by the corresponding MCU.
* Remove clearing of L1 and L2 errors during initialization time. Otherwise, they will not be captured between firmware booting and error configuration.
* Add capture and clearing SoC register bus errors
* Add register bus resource to SoC DT node

v4:
* Fix PMD l1/l2 error reading address due to wrong variable type
* Fix clearing of software generated and HW errors for l1/l2

v3:
* Update binding documentation for PMD DT node and exampples
* Add binding documentation for SoC DT node
* Change MC, PMD, and L3C driver error injection to use debugfs
* Add missing IRQ for MC correctable error (code and DT)
* Use true/false where appropriate instead 1/0
* Add bit definition for L1 MMUESR register and fully decode this error
* Remove the un-necessary dev variable from xgene_edac_pmd_ctx structure
* Add check for disabled PMD (code and DT)
* Switch to edac_printk instead pr_err
* Some minor comments update

v2:
* Add EDAC entry in MAINTAINERS for APM EDAC driver
* Remove the MC scrub patch
* Remove the word 'Caches' from Kconfig
* Change all MASK defines to use BIT(x)
* Update comment or remove them
* Wrap error injection code around CONFIG_EDAC_DEBUG
* Change function name xgene_edac_mc_hw_init to xgene_edac_mc_irq_ctl
* Change all function XXX_hw_init to XXX_hw_ctl
* Fix typo 'activie'
* Move calling function edac_mc_alloc after resource retrieval
* Check for NULL on platform_get_resource return if reference directly
* Add documentation for struct xgene_edac_pmd_ctx
* Move L1 and L2 check out of function xgene_edac_pmd_check to its own functions
* Use for loop for configure each CPU of an PMD
* Replace /2 by >> 1
* Remove unnecessary comment on edac_device_add_device failure
* Make mem_err_ip static const
* Unwind EDAC register correctly if failed
---
Loc Ho (5):
arm64: Enable EDAC on ARM64
MAINTAINERS: Add entry for APM X-Gene SoC EDAC driver
Documentation: Add documentation for the APM X-Gene SoC EDAC DTS
binding
edac: Add APM X-Gene SoC EDAC driver
arm64: Add APM X-Gene SoC EDAC DTS entries

 .../devicetree/bindings/edac/apm-xgene-edac.txt    |   82 +
 MAINTAINERS                                        |    8 +
 arch/arm64/Kconfig                                 |    1 +
 arch/arm64/boot/dts/apm/apm-storm.dtsi             |   98 +
 arch/arm64/include/asm/edac.h                      |   31 +
 drivers/edac/Kconfig                               |    9 +-
 drivers/edac/Makefile                              |    1 +
 drivers/edac/xgene_edac.c                          | 2183 ++++++++++++++++++++
 8 files changed, 2412 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/edac/apm-xgene-edac.txt
 create mode 100644 arch/arm64/include/asm/edac.h
 create mode 100644 drivers/edac/xgene_edac.c
author
#1 lore raw

PATCH v6 1/5 arm64: Enable EDAC on ARM64

Add an stub atomic_scrub and enable EDAC for arm64.

Signed-off-by Loc Ho <[email protected]>
---
 arch/arm64/Kconfig            |    1 +
 arch/arm64/include/asm/edac.h |   31 +++++++++++++++++++++++++++++++
 2 files changed, 32 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/edac.h
arch/arm64/Kconfig +1 -0
index e80cd74..d9c342a 100644
@@ -20,6 +20,7 @@ config ARM64
 	select BUILDTIME_EXTABLE_SORT
 	select CLONE_BACKWARDS
 	select COMMON_CLK
+	select EDAC_SUPPORT
 	select CPU_PM if (SUSPEND || CPU_IDLE)
 	select DCACHE_WORD_ACCESS
 	select GENERIC_ALLOCATOR
arch/arm64/include/asm/edac.h new file +31 -0
new file mode 100644
index 0000000..1cedba6
@@ -0,0 +1,31 @@
+/*
+ * ARM64 EDAC Header File
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef ASM_EDAC_H
+#define ASM_EDAC_H
+
+/*
+ * ECC atomic, DMA, SMP and interrupt safe scrub function.
+ * Implements the per arch atomic_scrub() that EDAC use for software
+ * ECC scrubbing.  It reads memory and then writes back the original
+ * value, allowing the hardware to detect and correct memory errors.
+ */
+static inline void atomic_scrub(void *va, u32 size)
+{
+	/* Stub function for now until an ARM64 HW has a way to test it. */
+}
+
+#endif
+

--
1.7.1

author
#2 lore raw

PATCH v6 2/5 MAINTAINERS: Add entry for APM X-Gene SoC EDAC driver

This patch adds a MAINTAINERS entry for APM X-Gene SoC EDAC driver.

Signed-off-by Loc Ho <[email protected]>
---
 MAINTAINERS |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)
MAINTAINERS +8 -0
index cd88eb6..d67ab7b 100644
@@ -3724,6 +3724,14 @@ W:	bluesmoke.sourceforge.net
 S:	Maintained
 F:	drivers/edac/sb_edac.c
 
+EDAC-XGENE
+APPLIED MICRO (APM) X-GENE SOC EDAC
+M:     Loc Ho <[email protected]>
+M:     Feng Kan <[email protected]>
+S:     Supported
+F:     drivers/edac/xgene_edac.c
+F:     Documentation/devicetree/bindings/edac/apm-xgene-edac.txt
+
 EDIROL UA-101/UA-1000 DRIVER
 M:	Clemens Ladisch <[email protected]>
 L:	alsa-devel at alsa-project.org (moderated for non-subscribers)

--
1.7.1

author
#3 lore raw

PATCH v6 3/5 Documentation: Add documentation for the APM X-Gene SoC EDAC DTS binding

This patch adds documentation for the APM X-Gene SoC EDAC DTS binding.

Signed-off-by Feng Kan <[email protected]>
Signed-off-by Loc Ho <[email protected]>
---
 .../devicetree/bindings/edac/apm-xgene-edac.txt    |   82 ++++++++++++++++++++
 1 files changed, 82 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/edac/apm-xgene-edac.txt
Documentation/devicetree/bindings/edac/apm-xgene-edac.txt new file +82 -0
new file mode 100644
index 0000000..db8c1c4
@@ -0,0 +1,82 @@
+* APM X-Gene SoC EDAC nodes
+
+EDAC nodes are defined to describe on-chip error detection and correction.
+There are four types of EDAC:
+
+  memory controller	- Memory controller
+  PMD (L1/L2)		- Processor module unit (PMD) L1/L2 cache
+  L3			- CPU L3 cache
+  SoC			- SoC IP such as SATA, Ethernet, and etc
+
+The following section describes the memory controller DT node binding.
+
+Required properties:
+- compatible		: Shall be "apm,xgene-edac-mc".
+- reg			: First resource shall be the PCP resource.
+			  Second resource shall be the CSW resource.
+			  Third resource shall be the MCB-A resource.
+			  Fourth resource shall be the MCB-B resource.
+			  Fifth resource shall be the MCU resource.
+- interrupts            : Interrupt-specifier for MCU error IRQ(s).
+
+The following section describes the L1/L2 DT node binding.
+
+- compatible		: Shall be "apm,xgene-edac-pmd".
+- reg			: First resource shall be the PCP resource.
+			  Second resource shall be the PMD resource.
+			  Third resource shall be the PMD efuse resource.
+- interrupts            : Interrupt-specifier for PMD error IRQ(s).
+
+The following section describes the L3 DT node binding.
+
+- compatible		: Shall be "apm,xgene-edac-l3".
+- reg			: First resource shall be the PCP resource.
+			  Second resource shall be the L3 resource.
+- interrupts            : Interrupt-specifier for L3 error IRQ(s).
+
+The following section describes the SoC DT node binding.
+
+- compatible		: Shall be "apm,xgene-edac-soc"".
+- reg			: First resource shall be the PCP resource.
+			  Second resource shall be the SoC resource.
+			  Third resource shall be the register bus resource.
+- interrupts		: Interrupt-specifier for SoC error IRQ(s).
+
+Example:
+	edacmc0: edacmc0 at 7e800000 {
+		compatible = "apm,xgene-edac-mc";
+		reg = <0x0 0x78800000 0x0 0x1000>,
+		      <0x0 0x7e200000 0x0 0x1000>,
+		      <0x0 0x7e700000 0x0 0x1000>,
+		      <0x0 0x7e720000 0x0 0x1000>,
+		      <0x0 0x7e800000 0x0 0x1000>;
+		interrupts = <0x0 0x20 0x4>,
+			     <0x0 0x21 0x4>;
+	};
+
+	edacl3: edacl3 at 7e600000 {
+		compatible = "apm,xgene-edac-l3";
+		reg = <0x0 0x78800000 0x0 0x1000>,
+		      <0x0 0x7e600000 0x0 0x1000>;
+		interrupts = <0x0 0x20 0x4>,
+			     <0x0 0x21 0x4>;
+	};
+
+	edacpmd0: edacpmd0 at 7c000000 {
+		compatible = "apm,xgene-edac-pmd";
+		reg = <0x0 0x78800000 0x0 0x1000>,
+		      <0x0 0x7c000000 0x0 0x200000>,
+		      <0x0 0x1054a000 0x0 0x10>;
+		interrupts = <0x0 0x20 0x4>,
+			     <0x0 0x21 0x4>;
+	};
+
+	edacsoc: edacsoc at 7e930000 {
+		compatible = "apm,xgene-edac-soc";
+		reg = <0x0 0x78800000 0x0 0x1000>,
+		      <0x0 0x7e930000 0x0 0x1000>,
+		      <0x0 0x7e000000 0x0 0x1000>;
+		interrupts = <0x0 0x20 0x4>,
+			     <0x0 0x21 0x4>,
+			     <0x0 0x27 0x4>;
+	};

--
1.7.1

author
#4 lore raw

PATCH v6 4/5 edac: Add APM X-Gene SoC EDAC driver

This patch adds support for the APM X-Gene SoC EDAC driver.

Signed-off-by Feng Kan <[email protected]>
Signed-off-by Loc Ho <[email protected]>
---
 drivers/edac/Kconfig      |    9 +-
 drivers/edac/Makefile     |    1 +
 drivers/edac/xgene_edac.c | 2183 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 2192 insertions(+), 1 deletions(-)
 create mode 100644 drivers/edac/xgene_edac.c
drivers/edac/Kconfig +8 -1
index cb59619..6289dd9 100644
@@ -10,7 +10,7 @@ config EDAC_SUPPORT
 menuconfig EDAC
 	bool "EDAC (Error Detection And Correction) reporting"
 	depends on HAS_IOMEM
-	depends on X86 || PPC || TILE || ARM || EDAC_SUPPORT
+	depends on X86 || PPC || TILE || ARM || ARM64 || EDAC_SUPPORT
 	help
 	  EDAC is designed to report errors in the core system.
 	  These are low-level errors that are reported in the CPU or

@@ -392,4 +392,11 @@ config EDAC_SYNOPSYS
 	  Support for error detection and correction on the Synopsys DDR
 	  memory controller.
 
+config EDAC_XGENE
+	tristate "APM X-Gene SoC"
+	depends on EDAC_MM_EDAC && ARM64
+	help
+	  Support for error detection and correction on the
+	  APM X-Gene family of SOCs.
+
 endif # EDAC
drivers/edac/Makefile +1 -0
index b255f36..28ef2a5 100644
@@ -68,3 +68,4 @@ obj-$(CONFIG_EDAC_OCTEON_PCI)		+= octeon_edac-pci.o
 
 obj-$(CONFIG_EDAC_ALTERA_MC)		+= altera_edac.o
 obj-$(CONFIG_EDAC_SYNOPSYS)		+= synopsys_edac.o
+obj-$(CONFIG_EDAC_XGENE)		+= xgene_edac.o
drivers/edac/xgene_edac.c new file +2183 -0

2,183 lines not on this page · raw message

--
1.7.1

author
#5 lore raw

PATCH v6 5/5 arm64: Add APM X-Gene SoC EDAC DTS entries

This patch adds APM X-Gene SoC EDAC DTS entries.

Signed-off-by Feng Kan <[email protected]>
Signed-off-by Loc Ho <[email protected]>
---
 arch/arm64/boot/dts/apm/apm-storm.dtsi |   98 ++++++++++++++++++++++++++++++++
 1 files changed, 98 insertions(+), 0 deletions(-)
arch/arm64/boot/dts/apm/apm-storm.dtsi +98 -0
index a857794..c7b028f 100644
@@ -354,6 +354,104 @@
 			};
 		};
 
+		edacmc0: edacmc0 at 7e800000 {
+			compatible = "apm,xgene-edac-mc";
+			reg = <0x0 0x78800000 0x0 0x1000>,
+			      <0x0 0x7e200000 0x0 0x1000>,
+			      <0x0 0x7e700000 0x0 0x1000>,
+			      <0x0 0x7e720000 0x0 0x1000>,
+			      <0x0 0x7e800000 0x0 0x1000>;
+			interrupts = <0x0 0x20 0x4>,
+				     <0x0 0x21 0x4>;
+		};
+
+		edacmc1: edacmc1 at 7e840000 {
+			compatible = "apm,xgene-edac-mc";
+			reg = <0x0 0x78800000 0x0 0x1000>,
+			      <0x0 0x7e200000 0x0 0x1000>,
+			      <0x0 0x7e700000 0x0 0x1000>,
+			      <0x0 0x7e720000 0x0 0x1000>,
+			      <0x0 0x7e840000 0x0 0x1000>;
+			interrupts = <0x0 0x20 0x4>,
+				     <0x0 0x21 0x4>;
+		};
+
+		edacmc2: edacmc2 at 7e880000 {
+			compatible = "apm,xgene-edac-mc";
+			reg = <0x0 0x78800000 0x0 0x1000>,
+			      <0x0 0x7e200000 0x0 0x1000>,
+			      <0x0 0x7e700000 0x0 0x1000>,
+			      <0x0 0x7e720000 0x0 0x1000>,
+			      <0x0 0x7e880000 0x0 0x1000>;
+			interrupts = <0x0 0x20 0x4>,
+				     <0x0 0x21 0x4>;
+		};
+
+		edacmc3: edacmc3 at 7e8c0000 {
+			compatible = "apm,xgene-edac-mc";
+			reg = <0x0 0x78800000 0x0 0x1000>,
+			      <0x0 0x7e200000 0x0 0x1000>,
+			      <0x0 0x7e700000 0x0 0x1000>,
+			      <0x0 0x7e720000 0x0 0x1000>,
+			      <0x0 0x7e8c0000 0x0 0x1000>;
+			interrupts = <0x0 0x20 0x4>,
+				     <0x0 0x21 0x4>;
+		};
+
+		edacpmd0: edacpmd0 at 7c000000 {
+			compatible = "apm,xgene-edac-pmd";
+			reg = <0x0 0x78800000 0x0 0x1000>,
+			      <0x0 0x7c000000 0x0 0x200000>,
+			      <0x0 0x1054a000 0x0 0x10>;
+			interrupts = <0x0 0x20 0x4>,
+				     <0x0 0x21 0x4>;
+		};
+
+		edacpmd1: edacpmd1 at 7c200000 {
+			compatible = "apm,xgene-edac-pmd";
+			reg = <0x0 0x78800000 0x0 0x1000>,
+			      <0x0 0x7c200000 0x0 0x200000>,
+			      <0x0 0x1054a000 0x0 0x10>;
+			interrupts = <0x0 0x20 0x4>,
+				     <0x0 0x21 0x4>;
+		};
+
+		edacpmd2: edacpmd2 at 7c400000 {
+			compatible = "apm,xgene-edac-pmd";
+			reg = <0x0 0x78800000 0x0 0x1000>,
+			      <0x0 0x7c400000 0x0 0x200000>,
+			      <0x0 0x1054a000 0x0 0x10>;
+			interrupts = <0x0 0x20 0x4>,
+				     <0x0 0x21 0x4>;
+		};
+
+		edacpmd3: edacpmd3 at 7c600000 {
+			compatible = "apm,xgene-edac-pmd";
+			reg = <0x0 0x78800000 0x0 0x1000>,
+			      <0x0 0x7c600000 0x0 0x200000>,
+			      <0x0 0x1054a000 0x0 0x10>;
+			interrupts = <0x0 0x20 0x4>,
+				     <0x0 0x21 0x4>;
+		};
+
+		edacl3: edacl3 at 7e600000 {
+			compatible = "apm,xgene-edac-l3";
+			reg = <0x0 0x78800000 0x0 0x1000>,
+			      <0x0 0x7e600000 0x0 0x1000>;
+			interrupts = <0x0 0x20 0x4>,
+				     <0x0 0x21 0x4>;
+		};
+
+		edacsoc: edacsoc at 7e930000 {
+			compatible = "apm,xgene-edac-soc";
+			reg = <0x0 0x78800000 0x0 0x1000>,
+			      <0x0 0x7e930000 0x0 0x1000>,
+			      <0x0 0x7e000000 0x0 0x1000>;
+			interrupts = <0x0 0x20 0x4>,
+				     <0x0 0x21 0x4>,
+				     <0x0 0x27 0x4>;
+		};
+
 		pcie0: pcie at 1f2b0000 {
 			status = "disabled";
 			device_type = "pci";

--
1.7.1

#6 lore raw

PATCH v6 3/5 Documentation: Add documentation for the APM X-Gene SoC EDAC DTS binding

In reply to Loc Ho
Quoted 64 lines · Loc Ho

This patch adds documentation for the APM X-Gene SoC EDAC DTS binding.

Signed-off-by Feng Kan <[email protected]>
Signed-off-by Loc Ho <[email protected]>
---
 .../devicetree/bindings/edac/apm-xgene-edac.txt    |   82 ++++++++++++++++++++
 1 files changed, 82 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/edac/apm-xgene-edac.txt
Documentation/devicetree/bindings/edac/apm-xgene-edac.txt new file +49 -0
new file mode 100644
index 0000000..db8c1c4
@@ -0,0 +1,82 @@
+* APM X-Gene SoC EDAC nodes
+
+EDAC nodes are defined to describe on-chip error detection and correction.
+There are four types of EDAC:
+
+  memory controller    - Memory controller
+  PMD (L1/L2)          - Processor module unit (PMD) L1/L2 cache
+  L3                   - CPU L3 cache
+  SoC                  - SoC IP such as SATA, Ethernet, and etc
+
+The following section describes the memory controller DT node binding.
+
+Required properties:
+- compatible           : Shall be "apm,xgene-edac-mc".
+- reg                  : First resource shall be the PCP resource.
+                         Second resource shall be the CSW resource.
+                         Third resource shall be the MCB-A resource.
+                         Fourth resource shall be the MCB-B resource.
+                         Fifth resource shall be the MCU resource.
+- interrupts            : Interrupt-specifier for MCU error IRQ(s).
+
+The following section describes the L1/L2 DT node binding.
+
+- compatible           : Shall be "apm,xgene-edac-pmd".
+- reg                  : First resource shall be the PCP resource.
+                         Second resource shall be the PMD resource.
+                         Third resource shall be the PMD efuse resource.
+- interrupts            : Interrupt-specifier for PMD error IRQ(s).
+
+The following section describes the L3 DT node binding.
+
+- compatible           : Shall be "apm,xgene-edac-l3".
+- reg                  : First resource shall be the PCP resource.
+                         Second resource shall be the L3 resource.
+- interrupts            : Interrupt-specifier for L3 error IRQ(s).
+
+The following section describes the SoC DT node binding.
+
+- compatible           : Shall be "apm,xgene-edac-soc"".
+- reg                  : First resource shall be the PCP resource.
+                         Second resource shall be the SoC resource.
+                         Third resource shall be the register bus resource.
+- interrupts           : Interrupt-specifier for SoC error IRQ(s).
+
+Example:
+       edacmc0: edacmc0 at 7e800000 {
+               compatible = "apm,xgene-edac-mc";
+               reg = <0x0 0x78800000 0x0 0x1000>,
+                     <0x0 0x7e200000 0x0 0x1000>,

Documentation/devicetree/bindings/edac/apm-xgene-edac.txt line 59

Quoted 10 lines
Documentation/devicetree/bindings/edac/apm-xgene-edac.txt new file +10 -0
+                     <0x0 0x7e700000 0x0 0x1000>,
+                     <0x0 0x7e720000 0x0 0x1000>,
+                     <0x0 0x7e800000 0x0 0x1000>;
+               interrupts = <0x0 0x20 0x4>,
+                            <0x0 0x21 0x4>;
+       };
+
+       edacl3: edacl3 at 7e600000 {
+               compatible = "apm,xgene-edac-l3";
+               reg = <0x0 0x78800000 0x0 0x1000>,

You are defining overlapping resources. Don't do that.

It looks to me like you are creating nodes based on driver functions, not h/w blocks. I would expect to see a memory controller node which contains ECC related registers. If you have blocks with multiple unrelated functions, then you should be using syscon to divide up the functions to different subsystems like EDAC.

Rob

author
#7 lore raw

PATCH v6 3/5 Documentation: Add documentation for the APM X-Gene SoC EDAC DTS binding

Hi Rob,

Quoted 77 lines
Quoted 64 lines

This patch adds documentation for the APM X-Gene SoC EDAC DTS binding.

Signed-off-by Feng Kan <[email protected]>
Signed-off-by Loc Ho <[email protected]>
---
 .../devicetree/bindings/edac/apm-xgene-edac.txt    |   82 ++++++++++++++++++++
 1 files changed, 82 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/edac/apm-xgene-edac.txt
Documentation/devicetree/bindings/edac/apm-xgene-edac.txt new file +49 -0
new file mode 100644
index 0000000..db8c1c4
@@ -0,0 +1,82 @@
+* APM X-Gene SoC EDAC nodes
+
+EDAC nodes are defined to describe on-chip error detection and correction.
+There are four types of EDAC:
+
+  memory controller    - Memory controller
+  PMD (L1/L2)          - Processor module unit (PMD) L1/L2 cache
+  L3                   - CPU L3 cache
+  SoC                  - SoC IP such as SATA, Ethernet, and etc
+
+The following section describes the memory controller DT node binding.
+
+Required properties:
+- compatible           : Shall be "apm,xgene-edac-mc".
+- reg                  : First resource shall be the PCP resource.
+                         Second resource shall be the CSW resource.
+                         Third resource shall be the MCB-A resource.
+                         Fourth resource shall be the MCB-B resource.
+                         Fifth resource shall be the MCU resource.
+- interrupts            : Interrupt-specifier for MCU error IRQ(s).
+
+The following section describes the L1/L2 DT node binding.
+
+- compatible           : Shall be "apm,xgene-edac-pmd".
+- reg                  : First resource shall be the PCP resource.
+                         Second resource shall be the PMD resource.
+                         Third resource shall be the PMD efuse resource.
+- interrupts            : Interrupt-specifier for PMD error IRQ(s).
+
+The following section describes the L3 DT node binding.
+
+- compatible           : Shall be "apm,xgene-edac-l3".
+- reg                  : First resource shall be the PCP resource.
+                         Second resource shall be the L3 resource.
+- interrupts            : Interrupt-specifier for L3 error IRQ(s).
+
+The following section describes the SoC DT node binding.
+
+- compatible           : Shall be "apm,xgene-edac-soc"".
+- reg                  : First resource shall be the PCP resource.
+                         Second resource shall be the SoC resource.
+                         Third resource shall be the register bus resource.
+- interrupts           : Interrupt-specifier for SoC error IRQ(s).
+
+Example:
+       edacmc0: edacmc0 at 7e800000 {
+               compatible = "apm,xgene-edac-mc";
+               reg = <0x0 0x78800000 0x0 0x1000>,
+                     <0x0 0x7e200000 0x0 0x1000>,

Documentation/devicetree/bindings/edac/apm-xgene-edac.txt line 59

Quoted 10 lines
Documentation/devicetree/bindings/edac/apm-xgene-edac.txt new file +10 -0
+                     <0x0 0x7e700000 0x0 0x1000>,
+                     <0x0 0x7e720000 0x0 0x1000>,
+                     <0x0 0x7e800000 0x0 0x1000>;
+               interrupts = <0x0 0x20 0x4>,
+                            <0x0 0x21 0x4>;
+       };
+
+       edacl3: edacl3 at 7e600000 {
+               compatible = "apm,xgene-edac-l3";
+               reg = <0x0 0x78800000 0x0 0x1000>,

You are defining overlapping resources. Don't do that.

Quoted 6 lines

It looks to me like you are creating nodes based on driver functions, not h/w blocks. I would expect to see a memory controller node which contains ECC related registers. If you have blocks with multiple unrelated functions, then you should be using syscon to divide up the functions to different subsystems like EDAC.

How about these bindings:

efuse: efuse at 1054a000 {
        compatible = "syscon";
        reg = <0x0 0x1054a000 0x0 0x20>;
};
pcperror: pcperror at 78800000 {
        compatible = "syscon";
        reg = <0x0 0x78800000 0x0 0x100>;
};
csw: csw at 7e200000 {
        compatible = "syscon";
        reg = <0x0 0x7e200000 0x0 0x1000>;
};
mcba: mcba at 7e700000 {
        compatible = "syscon";
        reg = <0x0 0x7e700000 0x0 0x1000>;
}
mcbb: mcbb at 7e720000 {
        compatible = "syscon";
        reg = <0x0 0x7e720000 0x0 0x1000>;
}
edacmc0: edacmc0 at 7e800000 {
        compatible = "apm,xgene-edac-mc";
        pcpmap = <&pcperror>;
        cswmap = <&csw>;
        mcbamap = <&mcba>;
        mcbbmap = <&mcbb>;
        reg = <0x0 0x7e800000 0x0 0x1000>;
        interrupts = <0x0 0x20 0x4>,
                         <0x0 0x21 0x4>;
};
edacpmd0: edacpmd0 at 7c000000 {
        compatible = "apm,xgene-edac-pmd";
        regmap = <&pcperror>;
        efusemap = <&efuse>;
        reg = <0x0 0x7c000000 0x0 0x200000>;
        interrupts = <0x0 0x20 0x4>,
                         <0x0 0x21 0x4>;
};
edacl3: edacl3 at 7e600000 {
        compatible = "apm,xgene-edac-l3";
        pcpmap = <&pcperror>;
        reg = <0x0 0x7e600000 0x0 0x1000>;
        interrupts = <0x0 0x20 0x4>,
                         <0x0 0x21 0x4>;
};
edacsoc: edacsoc at 7e930000 {
        compatible = "apm,xgene-edac-soc";
        pcpmap = <&pcperror>;
        reg = <0x0 0x7e930000 0x0 0x1000>,
                 <0x0 0x7e000000 0x0 0x1000>;
        interrupts = <0x0 0x20 0x4>,
                         <0x0 0x21 0x4>,
                         <0x0 0x27 0x4>;
};

-Loc

author
#8 lore raw

v6 cover edac: Add APM X-Gene SoC EDAC driver

In reply to Loc Ho

Hi Doug,

Any comment with v6 of the APM EDAC driver?

-Loc

Quoted 83 lines · Loc Ho

This patch adds support for the APM X-Gene SoC EDAC driver for DT.

v6:
* Rebase to 4.0.0-rc3
* Add memory scrub stub function and enable ARM64 EDAC support patch
* Add bit definition defines for L2RTOS registers
* Remove un-necessary clearing of all L1/L2 software generated registers
* Remove wrong notification of LSU un-correctable error
* Change L2 reporting of un-correcable error to correctable error
* Change clearing of the L2C L2RTO registers
* Add support for L2 HW version 1 and version 2 or above
* Add support for L3 HW version 1 and version 2 or above

v5:
* Rebase to 3.17.rc1 (next)
* Update binding documentation for additional SoC node binding resource
* Enable MCU correctable and uncorrectable interrupts if not enabled by firmware
* Enable top level interrupt only after all MCU registered. Otherwise, error interrupt will never get cleared by the corresponding MCU.
* Remove clearing of L1 and L2 errors during initialization time. Otherwise, they will not be captured between firmware booting and error configuration.
* Add capture and clearing SoC register bus errors
* Add register bus resource to SoC DT node

v4:
* Fix PMD l1/l2 error reading address due to wrong variable type
* Fix clearing of software generated and HW errors for l1/l2

v3:
* Update binding documentation for PMD DT node and exampples
* Add binding documentation for SoC DT node
* Change MC, PMD, and L3C driver error injection to use debugfs
* Add missing IRQ for MC correctable error (code and DT)
* Use true/false where appropriate instead 1/0
* Add bit definition for L1 MMUESR register and fully decode this error
* Remove the un-necessary dev variable from xgene_edac_pmd_ctx structure
* Add check for disabled PMD (code and DT)
* Switch to edac_printk instead pr_err
* Some minor comments update

v2:
* Add EDAC entry in MAINTAINERS for APM EDAC driver
* Remove the MC scrub patch
* Remove the word 'Caches' from Kconfig
* Change all MASK defines to use BIT(x)
* Update comment or remove them
* Wrap error injection code around CONFIG_EDAC_DEBUG
* Change function name xgene_edac_mc_hw_init to xgene_edac_mc_irq_ctl
* Change all function XXX_hw_init to XXX_hw_ctl
* Fix typo 'activie'
* Move calling function edac_mc_alloc after resource retrieval
* Check for NULL on platform_get_resource return if reference directly
* Add documentation for struct xgene_edac_pmd_ctx
* Move L1 and L2 check out of function xgene_edac_pmd_check to its own functions
* Use for loop for configure each CPU of an PMD
* Replace /2 by >> 1
* Remove unnecessary comment on edac_device_add_device failure
* Make mem_err_ip static const
* Unwind EDAC register correctly if failed
---
Loc Ho (5):
arm64: Enable EDAC on ARM64
MAINTAINERS: Add entry for APM X-Gene SoC EDAC driver
Documentation: Add documentation for the APM X-Gene SoC EDAC DTS
binding
edac: Add APM X-Gene SoC EDAC driver
arm64: Add APM X-Gene SoC EDAC DTS entries

 .../devicetree/bindings/edac/apm-xgene-edac.txt    |   82 +
 MAINTAINERS                                        |    8 +
 arch/arm64/Kconfig                                 |    1 +
 arch/arm64/boot/dts/apm/apm-storm.dtsi             |   98 +
 arch/arm64/include/asm/edac.h                      |   31 +
 drivers/edac/Kconfig                               |    9 +-
 drivers/edac/Makefile                              |    1 +
 drivers/edac/xgene_edac.c                          | 2183 ++++++++++++++++++++
 8 files changed, 2412 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/edac/apm-xgene-edac.txt
 create mode 100644 arch/arm64/include/asm/edac.h
 create mode 100644 drivers/edac/xgene_edac.c
maintainer
#9 lore raw

v6 cover edac: Add APM X-Gene SoC EDAC driver

Quoted 3 lines · Loc Ho

Hi Doug,

Any comment with v6 of the APM EDAC driver?

So this thing is being delayed only due to the device tree stuff AFAICT.

Can someone of the DT people on To: please have a look already so that I can queue this?

Thanks.

Signature · 5 lines
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.
--
author
#10 lore raw

v6 cover edac: Add APM X-Gene SoC EDAC driver

Hi,

Quoted 7 lines
Quoted 2 lines

Any comment with v6 of the APM EDAC driver?

So this thing is being delayed only due to the device tree stuff AFAICT.

Can someone of the DT people on To: please have a look already so that I can queue this?

I would really appreciate if someone from the DT community can review/approve the DT changes.

-Loc