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socfpga: socdk and socrates share SPI flash config, move it to shared place

U-Boot New Pavel Machek 3 participants 11 messages Apr 20, 2015 – Apr 27, 2015 Arm (32-bit)

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Pavel Machek

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#0 lore raw

Both Socrates and SocDK share same QSPI and SPI flash configuration. Move the common configuration into common place.

Signed-off-by Pavel Machek <[email protected]>
arch/arm/dts/socfpga_cyclone5.dtsi +26 -0
index 234a901..c40ade5 100644
@@ -37,4 +37,30 @@
 			cpu1-start-addr = <0xffd080c4>;
 		};
 	};
+
+	aliases {
+		spi0 = "/spi at ff705000";		/* QSPI */
+		spi1 = "/spi at fff00000";
+		spi2 = "/spi at fff01000";
+	};
+};
+
+&qspi {
+	status = "okay";
+
+	flash0: n25q00 at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "n25q00";
+		reg = <0>;      /* chip select */
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+		page-size = <256>;
+		block-size = <16>; /* 2^16, 64KB */
+		read-delay = <4>;  /* delay value in read data capture register */
+		tshsl-ns = <50>;
+		tsd2d-ns = <50>;
+		tchsh-ns = <4>;
+		tslch-ns = <4>;
+	};
 };
arch/arm/dts/socfpga_cyclone5_socrates.dts +0 -25
index ea30483..2a64b3c 100644
@@ -14,12 +14,6 @@
 		bootargs = "console=ttyS0,115200";
 	};
 
- 	aliases {
-		spi0 = "/spi at ff705000";		/* QSPI */
-		spi1 = "/spi at fff00000";
-		spi2 = "/spi at fff01000";
- 	};
-
 	memory {
 		name = "memory";
 		device_type = "memory";

@@ -44,22 +38,3 @@
 	status = "okay";
 };
 
-&qspi {
-	status = "okay";
-
-	flash0: n25q00 at 0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "n25q00";
-		reg = <0>;      /* chip select */
-		spi-max-frequency = <50000000>;
-		m25p,fast-read;
-		page-size = <256>;
-		block-size = <16>; /* 2^16, 64KB */
-		read-delay = <4>;  /* delay value in read data capture register */
-		tshsl-ns = <50>;
-		tsd2d-ns = <50>;
-		tchsh-ns = <4>;
-		tslch-ns = <4>;
-	};
-};
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(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
#1 lore raw
Quoted 4 lines · Pavel Machek

Both Socrates and SocDK share same QSPI and SPI flash configuration. Move the common configuration into common place.

Signed-off-by Pavel Machek <[email protected]>

Is my understanding correct that now all SoCFPGA CV boards will be forced to have this SPI flash ? I believe this is incorrect.

Best regards,
Marek Vasut

#2 lore raw
Quoted 8 lines · Marek Vasut
Quoted 4 lines · Pavel Machek

Both Socrates and SocDK share same QSPI and SPI flash configuration. Move the common configuration into common place.

Signed-off-by Pavel Machek <[email protected]>

Is my understanding correct that now all SoCFPGA CV boards will be forced to have this SPI flash ? I believe this is incorrect.

Yes. Defining such a SPI flash is board specific and shouldn't be moved to the common dtsi file.

Thanks,
Stefan

author
#3 lore raw

PATCH 1/1 socfpga: implement socdk SPI flash config in dts

SocDK has same QSPI and SPI flash configuration as Socrates. Add support for it.

Signed-off-by Pavel Machek <[email protected]>
arch/arm/dts/socfpga_cyclone5_socdk.dts +24 -0
index 8e1f88c..70701f0 100644
@@ -25,6 +25,10 @@
 		 * to be added to the gmac1 device tree blob.
 		 */
 		ethernet0 = &gmac1;
+
+		spi0 = "/spi at ff705000";		/* QSPI */
+		spi1 = "/spi at fff00000";
+		spi2 = "/spi at fff01000";
 	};
 
 	regulator_3_3v: 3-3-v-regulator {

@@ -77,3 +81,23 @@
 &usb1 {
 	status = "okay";
 };
+
+&qspi {
+	status = "okay";
+
+	flash0: n25q00 at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "n25q00";
+		reg = <0>;      /* chip select */
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+		page-size = <256>;
+		block-size = <16>; /* 2^16, 64KB */
+		read-delay = <4>;  /* delay value in read data capture register */
+		tshsl-ns = <50>;
+		tsd2d-ns = <50>;
+		tchsh-ns = <4>;
+		tslch-ns = <4>;
+	};
+};
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
Applied
#4 lore raw

PATCH 1/1 socfpga: implement socdk SPI flash config in dts

Quoted 4 lines · Pavel Machek

SocDK has same QSPI and SPI flash configuration as Socrates. Add support for it.

Signed-off-by Pavel Machek <[email protected]>

Applied, thanks.

Can you please cook one for Arria V too while at it, so we're consistent ?

Best regards,
Marek Vasut

author
#5 lore raw

PATCH 1/1 socfpga: implement socdk SPI flash config in dts

Quoted 9 lines · Marek Vasut
Quoted 4 lines · Pavel Machek

SocDK has same QSPI and SPI flash configuration as Socrates. Add support for it.

Signed-off-by Pavel Machek <[email protected]>

Applied, thanks.

Can you please cook one for Arria V too while at it, so we're consistent ?

Ok (if you are sure it has same hardware?). Should something like socfpga_devel_board.dtsi be created so we don't have to copy same piece of dts 3 times?
Pavel

Signature · 2 lines
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(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
#6 lore raw

PATCH 1/1 socfpga: implement socdk SPI flash config in dts

Quoted 5 lines · Pavel Machek
Quoted 4 lines · Marek Vasut
Quoted 3 lines · Pavel Machek

SocDK has same QSPI and SPI flash configuration as Socrates. Add support for it.

Quoted 8 lines
Quoted 6 lines
Quoted 1 line
Signed-off-by Pavel Machek <[email protected]>

Applied, thanks.

Can you please cook one for Arria V too while at it, so we're consistent ?

Ok (if you are sure it has same hardware?).

Yeah, from this point of view, CV and AV are almost identical. Basically, it's the FPGA which differs, AV is closer to stratix in my opinion.

Quoted 3 lines

Should something like
socfpga_devel_board.dtsi be created so we don't have to copy same piece of dts 3 times?

No, this is board specific. I have a feeling we'll have to just deal with three copies in this case.

Best regards,
Marek Vasut

author
#7 lore raw

PATCH 1/1 socfpga: implement arria V socdk SPI flash config in dts

Arria V SocDK has same QSPI and SPI flash configuration as Socrates. Add support for it.

Signed-off-by Pavel Machek <[email protected]>
arch/arm/dts/socfpga_arria5_socdk.dts +24 -0
index 4e529a1..1b86897 100644
@@ -25,6 +25,10 @@
 		* to be added to the gmac1 device tree blob.
 		*/
 		ethernet0 = &gmac1;
+
+		spi0 = "/spi at ff705000";		/* QSPI */
+		spi1 = "/spi at fff00000";
+		spi2 = "/spi at fff01000";
 	};
 
 	regulator_3_3v: 3-3-v-regulator {

@@ -72,3 +76,23 @@
 &usb1 {
 	status = "okay";
 };
+
+&qspi {
+	status = "okay";
+
+	flash0: n25q00 at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "n25q00";
+		reg = <0>;      /* chip select */
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+		page-size = <256>;
+		block-size = <16>; /* 2^16, 64KB */
+		read-delay = <4>;  /* delay value in read data capture register */
+		tshsl-ns = <50>;
+		tsd2d-ns = <50>;
+		tchsh-ns = <4>;
+		tslch-ns = <4>;
+	};
+};
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
#8 lore raw

PATCH 1/1 socfpga: implement arria V socdk SPI flash config in dts

arch/arm/dts/socfpga_arria5_socdk.dts

Quoted 9 lines · Pavel Machek

Arria V SocDK has same QSPI and SPI flash configuration as Socrates. Add support for it.

Signed-off-by Pavel Machek <[email protected]>
(quoted diff) +0 -0

b/arch/arm/dts/socfpga_arria5_socdk.dts index 4e529a1..1b86897 100644

arch/arm/dts/socfpga_arria5_socdk.dts +0 -0

I was just curious about this, but why are your patches missing diffstat ?

btw. I presume that there is no opposition to this patch, in my opinion it's perfectly OK.

Best regards,
Marek Vasut

author
#9 lore raw

PATCH 1/1 socfpga: implement arria V socdk SPI flash config in dts

Quoted 4 lines · Marek Vasut
Quoted 3 lines · Pavel Machek

Arria V SocDK has same QSPI and SPI flash configuration as Socrates. Add support for it.

Quoted 8 lines

arch/arm/dts/socfpga_arria5_socdk.dts

Quoted 6 lines
Signed-off-by Pavel Machek <[email protected]>
(quoted diff) +0 -0

b/arch/arm/dts/socfpga_arria5_socdk.dts index 4e529a1..1b86897 100644

arch/arm/dts/socfpga_arria5_socdk.dts +0 -0

I was just curious about this, but why are your patches missing diffstat ?

diffstat was never required part of a patch.

Quoted 2 lines

btw. I presume that there is no opposition to this patch, in my opinion it's perfectly OK.

So this means "thank you, applied"?
Pavel

Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
#10 lore raw

PATCH 1/1 socfpga: implement arria V socdk SPI flash config in dts

Quoted 15 lines · Pavel Machek
Quoted 6 lines · Marek Vasut
Quoted 5 lines · Pavel Machek

Arria V SocDK has same QSPI and SPI flash configuration as Socrates. Add support for it.

Signed-off-by Pavel Machek <[email protected]>
Quoted 7 lines

arch/arm/dts/socfpga_arria5_socdk.dts

Quoted 4 lines
(quoted diff) +0 -0

b/arch/arm/dts/socfpga_arria5_socdk.dts index 4e529a1..1b86897 100644

arch/arm/dts/socfpga_arria5_socdk.dts +0 -0

I was just curious about this, but why are your patches missing diffstat ?

Quoted 1 line

diffstat was never required part of a patch.

Would be nice to have though.

Quoted 4 lines
Quoted 2 lines

btw. I presume that there is no opposition to this patch, in my opinion it's perfectly OK.

So this means "thank you, applied"?

No, that's "applied, thanks" ;-)

Best regards,
Marek Vasut