Introduce BIT and GENMASK

PATCH Superseded Jagan Teki 5 participants 13 messages May 10, 2015 – May 15, 2015

Subsystems (8)

Arm i.MX and Layerscape Memory technology devices (MTD) SPI Arm Samsung Exynos +4 more subsystems

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Jagan Teki

author

2015-05-10 15:22 UTC #0 lore raw

v2 cover Introduce BIT and GENMASK

I have sent one v1 for BIT macro change for entire u-boot, but this time I'm just introduce by changing this with spi/sf code, will send more in changes in future.

Along with BIT and also introduces GENMASK with spi/sf code.

Changes for v2:
- break the BIT macro patch only for spi/sf code.

thanks!
Jagan.

Jagan Teki (5):
spi/sf: Add BIT macro in linux/bitops.h
spi: Remove #define BIT in local file
spi/sf: Use BIT macro from linux/bitops.h
linux/bitops.h: GENMASK copy from linux
spi: Use GENMASK instead of numeric hexcodes

 drivers/mtd/spi/sandbox.c      |  4 +--
 drivers/mtd/spi/sf_internal.h  | 36 ++++++++++----------
 drivers/spi/altera_spi.c       | 26 +++++++--------
 drivers/spi/atmel_spi.h        | 54 +++++++++++++++---------------
 drivers/spi/bfin_spi6xx.c      |  8 ++---
 drivers/spi/cadence_qspi_apb.c | 76 +++++++++++++++++++++---------------------
 drivers/spi/davinci_spi.c      |  2 --
 drivers/spi/designware_spi.c   | 16 ++++-----
 drivers/spi/ep93xx_spi.c       |  6 +---
 drivers/spi/exynos_spi.c       |  4 +--
 drivers/spi/fsl_dspi.c         |  2 +-
 drivers/spi/fsl_espi.c         | 20 +++++------
 drivers/spi/fsl_qspi.c         |  6 ++--
 drivers/spi/ich.c              |  4 +--
 drivers/spi/mpc8xxx_spi.c      |  2 +-
 drivers/spi/mxs_spi.c          |  2 +-
 drivers/spi/omap3_spi.h        | 64 +++++++++++++++++------------------
 drivers/spi/sh_qspi.c          | 16 ++++-----
 drivers/spi/tegra114_spi.c     | 76 +++++++++++++++++++++---------------------
 drivers/spi/tegra20_sflash.c   | 54 +++++++++++++++---------------
 drivers/spi/tegra20_slink.c    | 60 ++++++++++++++++-----------------
 drivers/spi/ti_qspi.c          | 10 +++---
 drivers/spi/xilinx_spi.c       | 46 ++++++++++++-------------
 drivers/spi/zynq_spi.c         | 22 ++++++------
 include/linux/bitops.h         | 12 +++++++
 include/spi.h                  | 46 ++++++++++++-------------
 26 files changed, 340 insertions(+), 334 deletions(-)

Signature · 1 line

1.9.1

Jagan Teki

author

2015-05-10 15:22 UTC #1 lore raw

PATCH v2 1/5 spi/sf: Add BIT macro in linux/bitops.h

Replace (1 << nr) to BIT(nr) where nr = 0, 1, 2 .... 31

Signed-off-by Jagan Teki <[email protected]>

Cc Tom Rini <[email protected]>

Cc Simon Glass <[email protected]>

Cc Masahiro Yamada <[email protected]>

---
 drivers/mtd/spi/sandbox.c      |  4 +--
 drivers/mtd/spi/sf_internal.h  |  8 +++---
 drivers/spi/altera_spi.c       | 26 ++++++++---------
 drivers/spi/atmel_spi.h        | 52 +++++++++++++++++-----------------
 drivers/spi/bfin_spi6xx.c      |  8 +++---
 drivers/spi/cadence_qspi_apb.c | 28 +++++++++---------
 drivers/spi/designware_spi.c   | 14 ++++-----
 drivers/spi/exynos_spi.c       |  4 +--
 drivers/spi/fsl_dspi.c         |  2 +-
 drivers/spi/fsl_espi.c         | 20 ++++++-------
 drivers/spi/fsl_qspi.c         |  4 +--
 drivers/spi/ich.c              |  4 +--
 drivers/spi/mpc8xxx_spi.c      |  2 +-
 drivers/spi/omap3_spi.h        | 48 +++++++++++++++----------------
 drivers/spi/sh_qspi.c          | 16 +++++------
 drivers/spi/tegra114_spi.c     | 64 +++++++++++++++++++++---------------------
 drivers/spi/tegra20_sflash.c   | 50 ++++++++++++++++-----------------
 drivers/spi/tegra20_slink.c    | 56 ++++++++++++++++++------------------
 drivers/spi/ti_qspi.c          | 10 +++----
 drivers/spi/xilinx_spi.c       | 32 ++++++++++-----------
 drivers/spi/zynq_spi.c         | 16 +++++------
 include/linux/bitops.h         |  1 +
 include/spi.h                  | 22 +++++++--------
 23 files changed, 246 insertions(+), 245 deletions(-)

drivers/mtd/spi/sandbox.c +2 -2

index d576d31..54baa42 100644
@@ -53,8 +53,8 @@ static const char *sandbox_sf_state_name(enum sandbox_sf_state state)
 }
 
 /* Bits for the status register */
-#define STAT_WIP	(1 << 0)
-#define STAT_WEL	(1 << 1)
+#define STAT_WIP	BIT(0)
+#define STAT_WEL	BIT(1)
 
 /* Assume all SPI flashes have 3 byte addresses since they do atm */
 #define SF_ADDR_LEN	3

drivers/mtd/spi/sf_internal.h +4 -4

index 98436dc..02015d7 100644
@@ -92,10 +92,10 @@ enum {
 #endif
 
 /* Common status */
-#define STATUS_WIP			(1 << 0)
-#define STATUS_QEB_WINSPAN		(1 << 1)
-#define STATUS_QEB_MXIC		(1 << 6)
-#define STATUS_PEC			(1 << 7)
+#define STATUS_WIP			BIT(0)
+#define STATUS_QEB_WINSPAN		BIT(1)
+#define STATUS_QEB_MXIC		BIT(6)
+#define STATUS_PEC			BIT(7)
 
 /* Flash timeout values */
 #define SPI_FLASH_PROG_TIMEOUT		(2 * CONFIG_SYS_HZ)

drivers/spi/altera_spi.c +13 ~~-13~~

index a4d03d9..2302117 100644
@@ -29,19 +29,19 @@ struct altera_spi_regs {
 	u32	slave_sel;
 };
 
-#define ALTERA_SPI_STATUS_ROE_MSK	(1 << 3)
-#define ALTERA_SPI_STATUS_TOE_MSK	(1 << 4)
-#define ALTERA_SPI_STATUS_TMT_MSK	(1 << 5)
-#define ALTERA_SPI_STATUS_TRDY_MSK	(1 << 6)
-#define ALTERA_SPI_STATUS_RRDY_MSK	(1 << 7)
-#define ALTERA_SPI_STATUS_E_MSK		(1 << 8)
-
-#define ALTERA_SPI_CONTROL_IROE_MSK	(1 << 3)
-#define ALTERA_SPI_CONTROL_ITOE_MSK	(1 << 4)
-#define ALTERA_SPI_CONTROL_ITRDY_MSK	(1 << 6)
-#define ALTERA_SPI_CONTROL_IRRDY_MSK	(1 << 7)
-#define ALTERA_SPI_CONTROL_IE_MSK	(1 << 8)
-#define ALTERA_SPI_CONTROL_SSO_MSK	(1 << 10)
+#define ALTERA_SPI_STATUS_ROE_MSK	BIT(3)
+#define ALTERA_SPI_STATUS_TOE_MSK	BIT(4)
+#define ALTERA_SPI_STATUS_TMT_MSK	BIT(5)
+#define ALTERA_SPI_STATUS_TRDY_MSK	BIT(6)
+#define ALTERA_SPI_STATUS_RRDY_MSK	BIT(7)
+#define ALTERA_SPI_STATUS_E_MSK		BIT(8)
+
+#define ALTERA_SPI_CONTROL_IROE_MSK	BIT(3)
+#define ALTERA_SPI_CONTROL_ITOE_MSK	BIT(4)
+#define ALTERA_SPI_CONTROL_ITRDY_MSK	BIT(6)
+#define ALTERA_SPI_CONTROL_IRRDY_MSK	BIT(7)
+#define ALTERA_SPI_CONTROL_IE_MSK	BIT(8)
+#define ALTERA_SPI_CONTROL_SSO_MSK	BIT(10)
 
 static ulong altera_spi_base_list[] = CONFIG_SYS_ALTERA_SPI_LIST;

drivers/spi/atmel_spi.h +26 ~~-26~~

70 lines not on this page · raw message

drivers/spi/bfin_spi6xx.c +4 -4

index eba01d1..8359d76 100644
@@ -63,9 +63,9 @@ void spi_cs_activate(struct spi_slave *slave)
 		ssel = bfin_read32(&bss->regs->ssel);
 		ssel |= 1 << slave->cs;
 		if (bss->cs_pol)
-			ssel |= (1 << 8) << slave->cs;
+			ssel |= BIT(8) << slave->cs;
 		else
-			ssel &= ~((1 << 8) << slave->cs);
+			ssel &= ~(BIT(8) << slave->cs);
 		bfin_write32(&bss->regs->ssel, ssel);
 	}

@@ -83,9 +83,9 @@ void spi_cs_deactivate(struct spi_slave *slave)
 		u32 ssel;
 		ssel = bfin_read32(&bss->regs->ssel);
 		if (bss->cs_pol)
-			ssel &= ~((1 << 8) << slave->cs);
+			ssel &= ~(BIT(8) << slave->cs);
 		else
-			ssel |= (1 << 8) << slave->cs;
+			ssel |= BIT(8) << slave->cs;
 		/* deassert cs */
 		bfin_write32(&bss->regs->ssel, ssel);
 		SSYNC();

drivers/spi/cadence_qspi_apb.c +14 ~~-14~~

index 00a115f..ff375e5 100644
@@ -64,10 +64,10 @@
 #define	CQSPI_REG_CONFIG			0x00
 #define	CQSPI_REG_CONFIG_CLK_POL_LSB		1
 #define	CQSPI_REG_CONFIG_CLK_PHA_LSB		2
-#define	CQSPI_REG_CONFIG_ENABLE_MASK		(1 << 0)
-#define	CQSPI_REG_CONFIG_DIRECT_MASK		(1 << 7)
-#define	CQSPI_REG_CONFIG_DECODE_MASK		(1 << 9)
-#define	CQSPI_REG_CONFIG_XIP_IMM_MASK		(1 << 18)
+#define	CQSPI_REG_CONFIG_ENABLE_MASK		BIT(0)
+#define	CQSPI_REG_CONFIG_DIRECT_MASK		BIT(7)
+#define	CQSPI_REG_CONFIG_DECODE_MASK		BIT(9)
+#define	CQSPI_REG_CONFIG_XIP_IMM_MASK		BIT(18)
 #define	CQSPI_REG_CONFIG_CHIPSELECT_LSB		10
 #define	CQSPI_REG_CONFIG_BAUD_LSB		19
 #define	CQSPI_REG_CONFIG_IDLE_LSB		31

@@ -128,18 +128,18 @@
 #define	CQSPI_REG_IRQMASK			0x44
 
 #define	CQSPI_REG_INDIRECTRD			0x60
-#define	CQSPI_REG_INDIRECTRD_START_MASK		(1 << 0)
-#define	CQSPI_REG_INDIRECTRD_CANCEL_MASK	(1 << 1)
-#define	CQSPI_REG_INDIRECTRD_INPROGRESS_MASK	(1 << 2)
-#define	CQSPI_REG_INDIRECTRD_DONE_MASK		(1 << 5)
+#define	CQSPI_REG_INDIRECTRD_START_MASK		BIT(0)
+#define	CQSPI_REG_INDIRECTRD_CANCEL_MASK	BIT(1)
+#define	CQSPI_REG_INDIRECTRD_INPROGRESS_MASK	BIT(2)
+#define	CQSPI_REG_INDIRECTRD_DONE_MASK		BIT(5)
 
 #define	CQSPI_REG_INDIRECTRDWATERMARK		0x64
 #define	CQSPI_REG_INDIRECTRDSTARTADDR		0x68
 #define	CQSPI_REG_INDIRECTRDBYTES		0x6C
 
 #define	CQSPI_REG_CMDCTRL			0x90
-#define	CQSPI_REG_CMDCTRL_EXECUTE_MASK		(1 << 0)
-#define	CQSPI_REG_CMDCTRL_INPROGRESS_MASK	(1 << 1)
+#define	CQSPI_REG_CMDCTRL_EXECUTE_MASK		BIT(0)
+#define	CQSPI_REG_CMDCTRL_INPROGRESS_MASK	BIT(1)
 #define	CQSPI_REG_CMDCTRL_DUMMY_LSB		7
 #define	CQSPI_REG_CMDCTRL_WR_BYTES_LSB		12
 #define	CQSPI_REG_CMDCTRL_WR_EN_LSB		15

@@ -155,10 +155,10 @@
 #define	CQSPI_REG_CMDCTRL_OPCODE_MASK		0xFF
 
 #define	CQSPI_REG_INDIRECTWR			0x70
-#define	CQSPI_REG_INDIRECTWR_START_MASK		(1 << 0)
-#define	CQSPI_REG_INDIRECTWR_CANCEL_MASK	(1 << 1)
-#define	CQSPI_REG_INDIRECTWR_INPROGRESS_MASK	(1 << 2)
-#define	CQSPI_REG_INDIRECTWR_DONE_MASK		(1 << 5)
+#define	CQSPI_REG_INDIRECTWR_START_MASK		BIT(0)
+#define	CQSPI_REG_INDIRECTWR_CANCEL_MASK	BIT(1)
+#define	CQSPI_REG_INDIRECTWR_INPROGRESS_MASK	BIT(2)
+#define	CQSPI_REG_INDIRECTWR_DONE_MASK		BIT(5)
 
 #define	CQSPI_REG_INDIRECTWRWATERMARK		0x74
 #define	CQSPI_REG_INDIRECTWRSTARTADDR		0x78

drivers/spi/designware_spi.c +7 -7

index 8f5c0fc..18f9786 100644
@@ -75,13 +75,13 @@ DECLARE_GLOBAL_DATA_PTR;
 
 /* Bit fields in SR, 7 bits */
 #define SR_MASK				0x7f		/* cover 7 bits */
-#define SR_BUSY				(1 << 0)
-#define SR_TF_NOT_FULL			(1 << 1)
-#define SR_TF_EMPT			(1 << 2)
-#define SR_RF_NOT_EMPT			(1 << 3)
-#define SR_RF_FULL			(1 << 4)
-#define SR_TX_ERR			(1 << 5)
-#define SR_DCOL				(1 << 6)
+#define SR_BUSY				BIT(0)
+#define SR_TF_NOT_FULL			BIT(1)
+#define SR_TF_EMPT			BIT(2)
+#define SR_RF_NOT_EMPT			BIT(3)
+#define SR_RF_FULL			BIT(4)
+#define SR_TX_ERR			BIT(5)
+#define SR_DCOL				BIT(6)
 
 #define RX_TIMEOUT			1000		/* timeout in ms */

drivers/spi/exynos_spi.c +2 -2

index 67f6b2d..4703f10 100644
@@ -86,7 +86,7 @@ static void spi_request_bytes(struct exynos_spi *regs, int count, int step)
 		writel(0, &regs->swap_cfg);
 	}
 
-	assert(count && count < (1 << 16));
+	assert(count && count < BIT(16));
 	setbits_le32(&regs->ch_cfg, SPI_CH_RST);
 	clrbits_le32(&regs->ch_cfg, SPI_CH_RST);

@@ -345,7 +345,7 @@ static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	 */
 	bytelen = bitlen / 8;
 	for (upto = 0; !ret && upto < bytelen; upto += todo) {
-		todo = min(bytelen - upto, (1 << 16) - 4);
+		todo = min(bytelen - upto, BIT(16) - 4);
 		ret = spi_rx_tx(priv, todo, &din, &dout, flags);
 		if (ret)
 			break;

drivers/spi/fsl_dspi.c +1 -1

index 6476f91..924a730 100644
@@ -24,7 +24,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* fsl_dspi_platdata flags */
-#define DSPI_FLAG_REGMAP_ENDIAN_BIG	(1 << 0)
+#define DSPI_FLAG_REGMAP_ENDIAN_BIG	BIT(0)
 
 /* idle data value */
 #define DSPI_IDLE_VAL			0x0

drivers/spi/fsl_espi.c +10 ~~-10~~

index 375dc07..b1586d1 100644
@@ -32,26 +32,26 @@ struct fsl_spi_slave {
 #define ESPI_MAX_CS_NUM		4
 #define ESPI_FIFO_WIDTH_BIT	32
 
-#define ESPI_EV_RNE		(1 << 9)
-#define ESPI_EV_TNF		(1 << 8)
-#define ESPI_EV_DON		(1 << 14)
-#define ESPI_EV_TXE		(1 << 15)
+#define ESPI_EV_RNE		BIT(9)
+#define ESPI_EV_TNF		BIT(8)
+#define ESPI_EV_DON		BIT(14)
+#define ESPI_EV_TXE		BIT(15)
 #define ESPI_EV_RFCNT_SHIFT	24
 #define ESPI_EV_RFCNT_MASK	(0x3f << ESPI_EV_RFCNT_SHIFT)
 
-#define ESPI_MODE_EN		(1 << 31)	/* Enable interface */
+#define ESPI_MODE_EN		BIT(31)	/* Enable interface */
 #define ESPI_MODE_TXTHR(x)	((x) << 8)	/* Tx FIFO threshold */
 #define ESPI_MODE_RXTHR(x)	((x) << 0)	/* Rx FIFO threshold */
 
 #define ESPI_COM_CS(x)		((x) << 30)
 #define ESPI_COM_TRANLEN(x)	((x) << 0)
 
-#define ESPI_CSMODE_CI_INACTIVEHIGH	(1 << 31)
-#define ESPI_CSMODE_CP_BEGIN_EDGCLK	(1 << 30)
-#define ESPI_CSMODE_REV_MSB_FIRST	(1 << 29)
-#define ESPI_CSMODE_DIV16		(1 << 28)
+#define ESPI_CSMODE_CI_INACTIVEHIGH	BIT(31)
+#define ESPI_CSMODE_CP_BEGIN_EDGCLK	BIT(30)
+#define ESPI_CSMODE_REV_MSB_FIRST	BIT(29)
+#define ESPI_CSMODE_DIV16		BIT(28)
 #define ESPI_CSMODE_PM(x)		((x) << 24)
-#define ESPI_CSMODE_POL_ASSERTED_LOW	(1 << 20)
+#define ESPI_CSMODE_POL_ASSERTED_LOW	BIT(20)
 #define ESPI_CSMODE_LEN(x)		((x) << 16)
 #define ESPI_CSMODE_CSBEF(x)		((x) << 12)
 #define ESPI_CSMODE_CSAFT(x)		((x) << 8)

drivers/spi/fsl_qspi.c +2 -2

index 868df5f..e1a0ec9 100644
@@ -68,7 +68,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define QSPI_CMD_SE_4B		0xdc    /* Sector erase (usually 64KiB) */
 
 /* fsl_qspi_platdata flags */
-#define QSPI_FLAG_REGMAP_ENDIAN_BIG	(1 << 0)
+#define QSPI_FLAG_REGMAP_ENDIAN_BIG	BIT(0)
 
 /* default SCK frequency, unit: HZ */
 #define FSL_QSPI_DEFAULT_SCK_FREQ	50000000

@@ -383,7 +383,7 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
 	/* Enable the module again (enable the DDR too) */
 	reg |= QSPI_MCR_DDR_EN_MASK;
 	/* Enable bit 29 for imx6sx */
-	reg |= (1 << 29);
+	reg |= BIT(29);
 
 	qspi_write32(priv->flags, &regs->mcr, reg);
 }

drivers/spi/ich.c +2 -2

index 50354fd..feffb08 100644
@@ -689,13 +689,13 @@ static int ich_spi_probe(struct udevice *bus)
 
 		ich9_spi = priv->base;
 		bios_cntl = ich_readb(priv, ich9_spi->bcr);
-		bios_cntl &= ~(1 << 5);	/* clear Enable InSMM_STS (EISS) */
+		bios_cntl &= ~BIT(5);	/* clear Enable InSMM_STS (EISS) */
 		bios_cntl |= 1;		/* Write Protect Disable (WPD) */
 		ich_writeb(priv, bios_cntl, ich9_spi->bcr);
 	} else {
 		pci_read_config_byte(plat->dev, 0xdc, &bios_cntl);
 		if (plat->ich_version == 9)
-			bios_cntl &= ~(1 << 5);
+			bios_cntl &= ~BIT(5);
 		pci_write_config_byte(plat->dev, 0xdc, bios_cntl | 0x1);
 	}

drivers/spi/mpc8xxx_spi.c +1 -1

index 0d59c36..00cbcbf 100644
@@ -55,7 +55,7 @@ void spi_init(void)
 	 * some registers
 	 */
 	spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN;
-	spi->mode = (spi->mode & 0xfff0ffff) | (1 << 16); /* Use SYSCLK / 8
+	spi->mode = (spi->mode & 0xfff0ffff) | BIT(16); /* Use SYSCLK / 8
 							     (16.67MHz typ.) */
 	spi->event = 0xffffffff;	/* Clear all SPI events */
 	spi->mask = 0x00000000;	/* Mask  all SPI interrupts */

drivers/spi/omap3_spi.h +24 ~~-24~~

64 lines not on this page · raw message

drivers/spi/sh_qspi.c +8 -8

index 77ede6b..7209e1d 100644
@@ -21,19 +21,19 @@
 #define SPPCR_IO3FV	0x04
 #define SPPCR_IO2FV	0x02
 #define SPPCR_IO1FV	0x01
-#define SPBDCR_RXBC0	(1 << 0)
-#define SPCMD_SCKDEN	(1 << 15)
-#define SPCMD_SLNDEN	(1 << 14)
-#define SPCMD_SPNDEN	(1 << 13)
-#define SPCMD_SSLKP	(1 << 7)
-#define SPCMD_BRDV0	(1 << 2)
+#define SPBDCR_RXBC0	BIT(0)
+#define SPCMD_SCKDEN	BIT(15)
+#define SPCMD_SLNDEN	BIT(14)
+#define SPCMD_SPNDEN	BIT(13)
+#define SPCMD_SSLKP	BIT(7)
+#define SPCMD_BRDV0	BIT(2)
 #define SPCMD_INIT1	SPCMD_SCKDEN | SPCMD_SLNDEN | \
 			SPCMD_SPNDEN | SPCMD_SSLKP | \
 			SPCMD_BRDV0
 #define SPCMD_INIT2	SPCMD_SPNDEN | SPCMD_SSLKP | \
 			SPCMD_BRDV0
-#define SPBFCR_TXRST	(1 << 7)
-#define SPBFCR_RXRST	(1 << 6)
+#define SPBFCR_TXRST	BIT(7)
+#define SPBFCR_RXRST	BIT(6)
 
 /* SH QSPI register set */
 struct sh_qspi_regs {

drivers/spi/tegra114_spi.c +32 ~~-32~~

86 lines not on this page · raw message

drivers/spi/tegra20_sflash.c +25 ~~-25~~

62 lines not on this page · raw message

drivers/spi/tegra20_slink.c +28 ~~-28~~

68 lines not on this page · raw message

drivers/spi/ti_qspi.c +5 -5

index 3356c0f..ca3acfd 100644
@@ -18,13 +18,13 @@
 #define QSPI_TIMEOUT                    2000000
 #define QSPI_FCLK                       192000000
 /* clock control */
-#define QSPI_CLK_EN                     (1 << 31)
+#define QSPI_CLK_EN                     BIT(31)
 #define QSPI_CLK_DIV_MAX                0xffff
 /* command */
 #define QSPI_EN_CS(n)                   (n << 28)
 #define QSPI_WLEN(n)                    ((n-1) << 19)
-#define QSPI_3_PIN                      (1 << 18)
-#define QSPI_RD_SNGL                    (1 << 16)
+#define QSPI_3_PIN                      BIT(18)
+#define QSPI_RD_SNGL                    BIT(16)
 #define QSPI_WR_SNGL                    (2 << 16)
 #define QSPI_INVAL                      (4 << 16)
 #define QSPI_RD_QUAD                    (7 << 16)

@@ -34,8 +34,8 @@
 #define QSPI_CSPOL(n)                   (1 << (1 + n*8))
 #define QSPI_CKPOL(n)                   (1 << (n*8))
 /* status */
-#define QSPI_WC                         (1 << 1)
-#define QSPI_BUSY                       (1 << 0)
+#define QSPI_WC                         BIT(1)
+#define QSPI_BUSY                       BIT(0)
 #define QSPI_WC_BUSY                    (QSPI_WC | QSPI_BUSY)
 #define QSPI_XFER_DONE                  QSPI_WC
 #define MM_SWITCH                       0x01

drivers/spi/xilinx_spi.c +16 ~~-16~~

index e9bf497..992a95a 100644
@@ -32,24 +32,24 @@
  */
 
 /* SPI Control Register (spicr), [1] p9, [2] p8 */
-#define SPICR_LSB_FIRST		(1 << 9)
-#define SPICR_MASTER_INHIBIT	(1 << 8)
-#define SPICR_MANUAL_SS		(1 << 7)
-#define SPICR_RXFIFO_RESEST	(1 << 6)
-#define SPICR_TXFIFO_RESEST	(1 << 5)
-#define SPICR_CPHA		(1 << 4)
-#define SPICR_CPOL		(1 << 3)
-#define SPICR_MASTER_MODE	(1 << 2)
-#define SPICR_SPE		(1 << 1)
-#define SPICR_LOOP		(1 << 0)
+#define SPICR_LSB_FIRST		BIT(9)
+#define SPICR_MASTER_INHIBIT	BIT(8)
+#define SPICR_MANUAL_SS		BIT(7)
+#define SPICR_RXFIFO_RESEST	BIT(6)
+#define SPICR_TXFIFO_RESEST	BIT(5)
+#define SPICR_CPHA		BIT(4)
+#define SPICR_CPOL		BIT(3)
+#define SPICR_MASTER_MODE	BIT(2)
+#define SPICR_SPE		BIT(1)
+#define SPICR_LOOP		BIT(0)
 
 /* SPI Status Register (spisr), [1] p11, [2] p10 */
-#define SPISR_SLAVE_MODE_SELECT	(1 << 5)
-#define SPISR_MODF		(1 << 4)
-#define SPISR_TX_FULL		(1 << 3)
-#define SPISR_TX_EMPTY		(1 << 2)
-#define SPISR_RX_FULL		(1 << 1)
-#define SPISR_RX_EMPTY		(1 << 0)
+#define SPISR_SLAVE_MODE_SELECT	BIT(5)
+#define SPISR_MODF		BIT(4)
+#define SPISR_TX_FULL		BIT(3)
+#define SPISR_TX_EMPTY		BIT(2)
+#define SPISR_RX_FULL		BIT(1)
+#define SPISR_RX_EMPTY		BIT(0)
 
 /* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
 #define SPIDTR_8BIT_MASK	(0xff << 0)

drivers/spi/zynq_spi.c +8 -8

index 4691ad5..9e48770 100644
@@ -20,17 +20,17 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
-#define ZYNQ_SPI_CR_MSA_MASK		(1 << 15)	/* Manual start enb */
-#define ZYNQ_SPI_CR_MCS_MASK		(1 << 14)	/* Manual chip select */
+#define ZYNQ_SPI_CR_MSA_MASK		BIT(15)	/* Manual start enb */
+#define ZYNQ_SPI_CR_MCS_MASK		BIT(14)	/* Manual chip select */
 #define ZYNQ_SPI_CR_CS_MASK		(0xF << 10)	/* Chip select */
 #define ZYNQ_SPI_CR_BRD_MASK		(0x7 << 3)	/* Baud rate div */
-#define ZYNQ_SPI_CR_CPHA_MASK		(1 << 2)	/* Clock phase */
-#define ZYNQ_SPI_CR_CPOL_MASK		(1 << 1)	/* Clock polarity */
-#define ZYNQ_SPI_CR_MSTREN_MASK		(1 << 0)	/* Mode select */
-#define ZYNQ_SPI_IXR_RXNEMPTY_MASK	(1 << 4)	/* RX_FIFO_not_empty */
-#define ZYNQ_SPI_IXR_TXOW_MASK		(1 << 2)	/* TX_FIFO_not_full */
+#define ZYNQ_SPI_CR_CPHA_MASK		BIT(2)	/* Clock phase */
+#define ZYNQ_SPI_CR_CPOL_MASK		BIT(1)	/* Clock polarity */
+#define ZYNQ_SPI_CR_MSTREN_MASK		BIT(0)	/* Mode select */
+#define ZYNQ_SPI_IXR_RXNEMPTY_MASK	BIT(4)	/* RX_FIFO_not_empty */
+#define ZYNQ_SPI_IXR_TXOW_MASK		BIT(2)	/* TX_FIFO_not_full */
 #define ZYNQ_SPI_IXR_ALL_MASK		0x7F		/* All IXR bits */
-#define ZYNQ_SPI_ENR_SPI_EN_MASK	(1 << 0)	/* SPI Enable */
+#define ZYNQ_SPI_ENR_SPI_EN_MASK	BIT(0)	/* SPI Enable */
 
 #define ZYNQ_SPI_FIFO_DEPTH		128
 #ifndef CONFIG_SYS_ZYNQ_SPI_WAIT

include/linux/bitops.h +1 -0

index e724310..c098c9a 100644
@@ -104,6 +104,7 @@ static inline unsigned int generic_hweight8(unsigned int w)
 	return (res & 0x0F) + ((res >> 4) & 0x0F);
 }
 
+#define BIT(nr)			(1UL << (nr))
 #define BIT_MASK(nr)		(1UL << ((nr) % BITS_PER_LONG))
 #define BIT_WORD(nr)		((nr) / BITS_PER_LONG)

include/spi.h +11 ~~-11~~

index ffc7162..7e42647 100644
@@ -30,26 +30,26 @@
 #define SPI_XFER_MMAP		0x08	/* Memory Mapped start */
 #define SPI_XFER_MMAP_END	0x10	/* Memory Mapped End */
 #define SPI_XFER_ONCE		(SPI_XFER_BEGIN | SPI_XFER_END)
-#define SPI_XFER_U_PAGE	(1 << 5)
+#define SPI_XFER_U_PAGE	BIT(5)
 
 /* SPI TX operation modes */
-#define SPI_OPM_TX_QPP		(1 << 0)
-#define SPI_OPM_TX_BP		(1 << 1)
+#define SPI_OPM_TX_QPP		BIT(0)
+#define SPI_OPM_TX_BP		BIT(1)
 
 /* SPI RX operation modes */
-#define SPI_OPM_RX_AS		(1 << 0)
-#define SPI_OPM_RX_AF		(1 << 1)
-#define SPI_OPM_RX_DOUT		(1 << 2)
-#define SPI_OPM_RX_DIO		(1 << 3)
-#define SPI_OPM_RX_QOF		(1 << 4)
-#define SPI_OPM_RX_QIOF		(1 << 5)
+#define SPI_OPM_RX_AS		BIT(0)
+#define SPI_OPM_RX_AF		BIT(1)
+#define SPI_OPM_RX_DOUT		BIT(2)
+#define SPI_OPM_RX_DIO		BIT(3)
+#define SPI_OPM_RX_QOF		BIT(4)
+#define SPI_OPM_RX_QIOF		BIT(5)
 #define SPI_OPM_RX_EXTN	(SPI_OPM_RX_AS | SPI_OPM_RX_AF | SPI_OPM_RX_DOUT | \
 				SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \
 				SPI_OPM_RX_QIOF)
 
 /* SPI bus connection options - see enum spi_dual_flash */
-#define SPI_CONN_DUAL_SHARED		(1 << 0)
-#define SPI_CONN_DUAL_SEPARATED	(1 << 1)
+#define SPI_CONN_DUAL_SHARED		BIT(0)
+#define SPI_CONN_DUAL_SEPARATED	BIT(1)
 
 /* Header byte that marks the start of the message */
 #define SPI_PREAMBLE_END_BYTE	0xec

Signature · 1 line

1.9.1

Jagan Teki

author

2015-05-10 15:22 UTC #2 lore raw

PATCH v2 2/5 spi: Remove #define BIT in local file

In reply to Jagan Teki

Since BIT macro is visiable to include/common.h there is no need to define again it on local headers hence removed.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/spi/davinci_spi.c | 2 --
 drivers/spi/ep93xx_spi.c  | 6 +-----
 2 files changed, 1 insertion(+), 7 deletions(-)

drivers/spi/davinci_spi.c +0 -2

index 0a036cc..0bd4f88 100644
@@ -15,8 +15,6 @@
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 
-#define BIT(x)			(1 << (x))
-
 /* SPIGCR0 */
 #define SPIGCR0_SPIENA_MASK	0x1
 #define SPIGCR0_SPIRST_MASK	0x0

drivers/spi/ep93xx_spi.c +1 -5

index 235557e..cdf30bb 100644
@@ -9,15 +9,11 @@
  */
 
 #include <common.h>
-#include <spi.h>
 #include <malloc.h>
-
+#include <spi.h>
 #include <asm/io.h>
-
 #include <asm/arch/ep93xx.h>
 
-
-#define BIT(x)			(1<<(x))
 #define SSPBASE			SPI_BASE
 
 #define SSPCR0			0x0000

Signature · 1 line

1.9.1

Jagan Teki

author

2015-05-10 15:22 UTC #3 lore raw

PATCH v2 3/5 spi/sf: Use BIT macro from linux/bitops.h

In reply to Jagan Teki

Updated few places in spi/sf code.

Signed-off-by Jagan Teki <[email protected]>

Cc Tom Rini <[email protected]>

Cc Simon Glass <[email protected]>

Cc Masahiro Yamada <[email protected]>

---
 drivers/mtd/spi/sf_internal.h | 28 ++++++++++++++--------------
 include/spi.h                 | 24 ++++++++++++------------
 2 files changed, 26 insertions(+), 26 deletions(-)

drivers/mtd/spi/sf_internal.h +14 ~~-14~~

index 02015d7..11f04c6 100644
@@ -16,18 +16,18 @@
 /* Dual SPI flash memories - see SPI_COMM_DUAL_... */
 enum spi_dual_flash {
 	SF_SINGLE_FLASH	= 0,
-	SF_DUAL_STACKED_FLASH	= 1 << 0,
-	SF_DUAL_PARALLEL_FLASH	= 1 << 1,
+	SF_DUAL_STACKED_FLASH	= BIT(0),
+	SF_DUAL_PARALLEL_FLASH	= BIT(1),
 };
 
 /* Enum list - Full read commands */
 enum spi_read_cmds {
-	ARRAY_SLOW		= 1 << 0,
-	ARRAY_FAST		= 1 << 1,
-	DUAL_OUTPUT_FAST	= 1 << 2,
-	DUAL_IO_FAST		= 1 << 3,
-	QUAD_OUTPUT_FAST	= 1 << 4,
-	QUAD_IO_FAST		= 1 << 5,
+	ARRAY_SLOW		= BIT(0),
+	ARRAY_FAST		= BIT(1),
+	DUAL_OUTPUT_FAST	= BIT(2),
+	DUAL_IO_FAST		= BIT(3),
+	QUAD_OUTPUT_FAST	= BIT(4),
+	QUAD_IO_FAST		= BIT(5),
 };
 
 /* Normal - Extended - Full command set */

@@ -37,12 +37,12 @@ enum spi_read_cmds {
 
 /* sf param flags */
 enum {
-	SECT_4K		= 1 << 0,
-	SECT_32K	= 1 << 1,
-	E_FSR		= 1 << 2,
-	SST_BP		= 1 << 3,
-	SST_WP		= 1 << 4,
-	WR_QPP		= 1 << 5,
+	SECT_4K		= BIT(0),
+	SECT_32K	= BIT(1),
+	E_FSR		= BIT(2),
+	SST_BP		= BIT(3),
+	SST_WP		= BIT(4),
+	WR_QPP		= BIT(5),
 };
 
 #define SST_WR		(SST_BP | SST_WP)

include/spi.h +12 ~~-12~~

index 7e42647..c8cf01b 100644
@@ -11,24 +11,24 @@
 #define _SPI_H_
 
 /* SPI mode flags */
-#define	SPI_CPHA	0x01			/* clock phase */
-#define	SPI_CPOL	0x02			/* clock polarity */
+#define	SPI_CPHA	BIT(0)			/* clock phase */
+#define	SPI_CPOL	BIT(1)			/* clock polarity */
 #define	SPI_MODE_0	(0|0)			/* (original MicroWire) */
 #define	SPI_MODE_1	(0|SPI_CPHA)
 #define	SPI_MODE_2	(SPI_CPOL|0)
 #define	SPI_MODE_3	(SPI_CPOL|SPI_CPHA)
-#define	SPI_CS_HIGH	0x04			/* CS active high */
-#define	SPI_LSB_FIRST	0x08			/* per-word bits-on-wire */
-#define	SPI_3WIRE	0x10			/* SI/SO signals shared */
-#define	SPI_LOOP	0x20			/* loopback mode */
-#define	SPI_SLAVE	0x40			/* slave mode */
-#define	SPI_PREAMBLE	0x80			/* Skip preamble bytes */
+#define	SPI_CS_HIGH	BIT(2)			/* CS active high */
+#define	SPI_LSB_FIRST	BIT(3)			/* per-word bits-on-wire */
+#define	SPI_3WIRE	BIT(4)			/* SI/SO signals shared */
+#define	SPI_LOOP	BIT(5)			/* loopback mode */
+#define	SPI_SLAVE	BIT(6)			/* slave mode */
+#define	SPI_PREAMBLE	BIT(7)			/* Skip preamble bytes */
 
 /* SPI transfer flags */
-#define SPI_XFER_BEGIN		0x01	/* Assert CS before transfer */
-#define SPI_XFER_END		0x02	/* Deassert CS after transfer */
-#define SPI_XFER_MMAP		0x08	/* Memory Mapped start */
-#define SPI_XFER_MMAP_END	0x10	/* Memory Mapped End */
+#define SPI_XFER_BEGIN		BIT(0)	/* Assert CS before transfer */
+#define SPI_XFER_END		BIT(1)	/* Deassert CS after transfer */
+#define SPI_XFER_MMAP		BIT(3)	/* Memory Mapped start */
+#define SPI_XFER_MMAP_END	BIT(4)	/* Memory Mapped End */
 #define SPI_XFER_ONCE		(SPI_XFER_BEGIN | SPI_XFER_END)
 #define SPI_XFER_U_PAGE	BIT(5)

Signature · 1 line

1.9.1

Jagan Teki

author

2015-05-10 15:22 UTC #4 lore raw

PATCH v2 4/5 linux/bitops.h: GENMASK copy from linux

In reply to Jagan Teki

GENMASK is used to create a contiguous bitmask([hi:lo]).

Signed-off-by Jagan Teki <[email protected]>

Cc Tom Rini <[email protected]>

Cc Simon Glass <[email protected]>

Cc Masahiro Yamada <[email protected]>

---
 include/linux/bitops.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

include/linux/bitops.h +11 -0

index c098c9a..08db119 100644
@@ -108,6 +108,17 @@ static inline unsigned int generic_hweight8(unsigned int w)
 #define BIT_MASK(nr)		(1UL << ((nr) % BITS_PER_LONG))
 #define BIT_WORD(nr)		((nr) / BITS_PER_LONG)
 
+/*
+ * Create a contiguous bitmask starting@bit position @l and ending at
+ * position @h. For example
+ * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000.
+ */
+#define GENMASK(h, l) \
+	(((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
+
+#define GENMASK_ULL(h, l) \
+	(((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
+
 #include <asm/bitops.h>
 
 /* linux/include/asm-generic/bitops/non-atomic.h */

Signature · 1 line

1.9.1

Jagan Teki

author

2015-05-10 15:22 UTC #5 lore raw

PATCH v2 5/5 spi: Use GENMASK instead of numeric hexcodes

In reply to Jagan Teki

Updated numeric hexcodes with GENMASK macro in few spi drivers.

Signed-off-by Jagan Teki <[email protected]>

Cc Tom Rini <[email protected]>

Cc Simon Glass <[email protected]>

Cc Masahiro Yamada <[email protected]>

Cc Peng Fan <[email protected]>

Cc Stefan Roese <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stephen Warren <[email protected]>

Cc Tom Warren <[email protected]>

Cc Michal Simek <[email protected]>

Cc Siva Durga Prasad Paladugu <[email protected]>

---
 drivers/spi/atmel_spi.h        |  2 +-
 drivers/spi/cadence_qspi_apb.c | 48 +++++++++++++++++++++---------------------
 drivers/spi/designware_spi.c   |  2 +-
 drivers/spi/fsl_qspi.c         |  2 +-
 drivers/spi/mxs_spi.c          |  2 +-
 drivers/spi/omap3_spi.h        | 10 ++++-----
 drivers/spi/tegra114_spi.c     | 12 +++++------
 drivers/spi/tegra20_sflash.c   |  2 +-
 drivers/spi/tegra20_slink.c    |  4 ++--
 drivers/spi/xilinx_spi.c       | 14 ++++++------
 drivers/spi/zynq_spi.c         |  6 +++---
 11 files changed, 52 insertions(+), 52 deletions(-)

drivers/spi/atmel_spi.h +1 -1

index 5b892d2..76b8556 100644
@@ -59,7 +59,7 @@
 #define ATMEL_SPI_CSRx_CSAAT		BIT(3)
 #define ATMEL_SPI_CSRx_BITS(x)		((x) << 4)
 #define ATMEL_SPI_CSRx_SCBR(x)		((x) << 8)
-#define ATMEL_SPI_CSRx_SCBR_MAX		0xff
+#define ATMEL_SPI_CSRx_SCBR_MAX		GENMASK(7, 0)
 #define ATMEL_SPI_CSRx_DLYBS(x)		((x) << 16)
 #define ATMEL_SPI_CSRx_DLYBCT(x)	((x) << 24)

drivers/spi/cadence_qspi_apb.c +24 ~~-24~~

105 lines not on this page · raw message

drivers/spi/designware_spi.c +1 -1

index 18f9786..d0733ee 100644
@@ -74,7 +74,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_CFS_OFFSET			12
 
 /* Bit fields in SR, 7 bits */
-#define SR_MASK				0x7f		/* cover 7 bits */
+#define SR_MASK				GENMASK(6, 0)	/* cover 7 bits */
 #define SR_BUSY				BIT(0)
 #define SR_TF_NOT_FULL			BIT(1)
 #define SR_TF_EMPT			BIT(2)

drivers/spi/fsl_qspi.c +1 -1

index e1a0ec9..10733df 100644
@@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define TX_BUFFER_SIZE		0x40
 #endif
 
-#define OFFSET_BITS_MASK	0x00ffffff
+#define OFFSET_BITS_MASK	GENMASK(24, 0)
 
 #define FLASH_STATUS_WEL	0x02

drivers/spi/mxs_spi.c +1 -1

index 2b9f395..270d0e6 100644
@@ -22,7 +22,7 @@
 
 #define	MXS_SPI_MAX_TIMEOUT	1000000
 #define	MXS_SPI_PORT_OFFSET	0x2000
-#define MXS_SSP_CHIPSELECT_MASK		0x00300000
+#define MXS_SSP_CHIPSELECT_MASK		GENMASK(21, 20)
 #define MXS_SSP_CHIPSELECT_SHIFT	20
 
 #define MXSSSP_SMALL_TRANSFER	512

drivers/spi/omap3_spi.h +5 -5

index 269a5c7..20276b7 100644
@@ -64,12 +64,12 @@ struct mcspi {
 
 #define OMAP3_MCSPI_CHCONF_PHA		BIT(0)
 #define OMAP3_MCSPI_CHCONF_POL		BIT(1)
-#define OMAP3_MCSPI_CHCONF_CLKD_MASK	(0x0f << 2)
+#define OMAP3_MCSPI_CHCONF_CLKD_MASK	GENMASK(5, 2)
 #define OMAP3_MCSPI_CHCONF_EPOL		BIT(6)
-#define OMAP3_MCSPI_CHCONF_WL_MASK	(0x1f << 7)
-#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY	(0x01 << 12)
-#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY	(0x02 << 12)
-#define OMAP3_MCSPI_CHCONF_TRM_MASK	(0x03 << 12)
+#define OMAP3_MCSPI_CHCONF_WL_MASK	GENMASK(11, 7)
+#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY	BIT(12)
+#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY	BIT(13)
+#define OMAP3_MCSPI_CHCONF_TRM_MASK	GENMASK(13, 12)
 #define OMAP3_MCSPI_CHCONF_DMAW		BIT(14)
 #define OMAP3_MCSPI_CHCONF_DMAR		BIT(15)
 #define OMAP3_MCSPI_CHCONF_DPE0		BIT(16)

drivers/spi/tegra114_spi.c +6 -6

index 61a0ecf..48877c3 100644
@@ -35,9 +35,9 @@ DECLARE_GLOBAL_DATA_PTR;
 /* COMMAND1 */
 #define SPI_CMD1_GO			BIT(31)
 #define SPI_CMD1_M_S			BIT(30)
-#define SPI_CMD1_MODE_MASK		0x3
+#define SPI_CMD1_MODE_MASK		GENMASK(1, 0)
 #define SPI_CMD1_MODE_SHIFT		28
-#define SPI_CMD1_CS_SEL_MASK		0x3
+#define SPI_CMD1_CS_SEL_MASK		GENMASK(1, 0)
 #define SPI_CMD1_CS_SEL_SHIFT		26
 #define SPI_CMD1_CS_POL_INACTIVE3	BIT(25)
 #define SPI_CMD1_CS_POL_INACTIVE2	BIT(24)

@@ -45,7 +45,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_CMD1_CS_POL_INACTIVE0	BIT(22)
 #define SPI_CMD1_CS_SW_HW		BIT(21)
 #define SPI_CMD1_CS_SW_VAL		BIT(20)
-#define SPI_CMD1_IDLE_SDA_MASK		0x3
+#define SPI_CMD1_IDLE_SDA_MASK		GENMASK(1, 0)
 #define SPI_CMD1_IDLE_SDA_SHIFT		18
 #define SPI_CMD1_BIDIR			BIT(17)
 #define SPI_CMD1_LSBI_FE		BIT(16)

@@ -55,14 +55,14 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_CMD1_RX_EN			BIT(12)
 #define SPI_CMD1_TX_EN			BIT(11)
 #define SPI_CMD1_PACKED			BIT(5)
-#define SPI_CMD1_BIT_LEN_MASK		0x1F
+#define SPI_CMD1_BIT_LEN_MASK		GENMASK(4, 0)
 #define SPI_CMD1_BIT_LEN_SHIFT		0
 
 /* COMMAND2 */
 #define SPI_CMD2_TX_CLK_TAP_DELAY	BIT(6)
-#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK	(0x3F << 6)
+#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK	GENMASK(11, 6)
 #define SPI_CMD2_RX_CLK_TAP_DELAY	BIT(0)
-#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK	(0x3F << 0)
+#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK	GENMASK(5, 0)
 
 /* TRANSFER STATUS */
 #define SPI_XFER_STS_RDY		BIT(30)

drivers/spi/tegra20_sflash.c +1 -1

index 4d3f1e4..77d638b 100644
@@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_CMD_CS1_EN			BIT(6)
 #define SPI_CMD_CS0_EN			BIT(5)
 #define SPI_CMD_BIT_LENGTH		BIT(4)
-#define SPI_CMD_BIT_LENGTH_MASK		0x0000001F
+#define SPI_CMD_BIT_LENGTH_MASK		GENMASK(4, 0)
 
 #define SPI_STAT_BSY			BIT(31)
 #define SPI_STAT_RDY			BIT(30)

drivers/spi/tegra20_slink.c +2 -2

index 674c7ab..427a2d6 100644
@@ -41,13 +41,13 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SLINK_CMD_CS_VAL		BIT(12)
 #define SLINK_CMD_CS_SOFT		BIT(11)
 #define SLINK_CMD_BIT_LENGTH		BIT(4)
-#define SLINK_CMD_BIT_LENGTH_MASK	0x0000001F
+#define SLINK_CMD_BIT_LENGTH_MASK	GENMASK(4, 0)
 /* COMMAND2 */
 #define SLINK_CMD2_TXEN			BIT(30)
 #define SLINK_CMD2_RXEN			BIT(31)
 #define SLINK_CMD2_SS_EN		BIT(18)
 #define SLINK_CMD2_SS_EN_SHIFT		18
-#define SLINK_CMD2_SS_EN_MASK		0x000C0000
+#define SLINK_CMD2_SS_EN_MASK		GENMASK(19, 18)
 #define SLINK_CMD2_CS_ACTIVE_BETWEEN	BIT(17)
 /* STATUS */
 #define SLINK_STAT_BSY			BIT(31)

drivers/spi/xilinx_spi.c +7 -7

index 992a95a..58ef1fa 100644
@@ -52,14 +52,14 @@
 #define SPISR_RX_EMPTY		BIT(0)
 
 /* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
-#define SPIDTR_8BIT_MASK	(0xff << 0)
-#define SPIDTR_16BIT_MASK	(0xffff << 0)
-#define SPIDTR_32BIT_MASK	(0xffffffff << 0)
+#define SPIDTR_8BIT_MASK	GENMASK(7, 0)
+#define SPIDTR_16BIT_MASK	GENMASK(15, 0)
+#define SPIDTR_32BIT_MASK	GENMASK(31, 0)
 
 /* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */
-#define SPIDRR_8BIT_MASK	(0xff << 0)
-#define SPIDRR_16BIT_MASK	(0xffff << 0)
-#define SPIDRR_32BIT_MASK	(0xffffffff << 0)
+#define SPIDRR_8BIT_MASK	GENMASK(7, 0)
+#define SPIDRR_16BIT_MASK	GENMASK(15, 0)
+#define SPIDRR_32BIT_MASK	GENMASK(31, 0)
 
 /* SPI Slave Select Register (spissr), [1] p13, [2] p13 */
 #define SPISSR_MASK(cs)		(1 << (cs))

@@ -75,7 +75,7 @@
 #define XILSPI_SPICR_DFLT_OFF	(SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
 
 #ifndef CONFIG_XILINX_SPI_IDLE_VAL
-#define CONFIG_XILINX_SPI_IDLE_VAL	0xff
+#define CONFIG_XILINX_SPI_IDLE_VAL	GENMASK(7, 0)
 #endif
 
 #ifndef CONFIG_SYS_XILINX_SPI_LIST

drivers/spi/zynq_spi.c +3 -3

index 9e48770..861125e 100644
@@ -22,14 +22,14 @@ DECLARE_GLOBAL_DATA_PTR;
 /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
 #define ZYNQ_SPI_CR_MSA_MASK		BIT(15)	/* Manual start enb */
 #define ZYNQ_SPI_CR_MCS_MASK		BIT(14)	/* Manual chip select */
-#define ZYNQ_SPI_CR_CS_MASK		(0xF << 10)	/* Chip select */
-#define ZYNQ_SPI_CR_BRD_MASK		(0x7 << 3)	/* Baud rate div */
+#define ZYNQ_SPI_CR_CS_MASK		GENMASK(13, 10)	/* Chip select */
+#define ZYNQ_SPI_CR_BRD_MASK		GENMASK(5, 3)	/* Baud rate div */
 #define ZYNQ_SPI_CR_CPHA_MASK		BIT(2)	/* Clock phase */
 #define ZYNQ_SPI_CR_CPOL_MASK		BIT(1)	/* Clock polarity */
 #define ZYNQ_SPI_CR_MSTREN_MASK		BIT(0)	/* Mode select */
 #define ZYNQ_SPI_IXR_RXNEMPTY_MASK	BIT(4)	/* RX_FIFO_not_empty */
 #define ZYNQ_SPI_IXR_TXOW_MASK		BIT(2)	/* TX_FIFO_not_full */
-#define ZYNQ_SPI_IXR_ALL_MASK		0x7F		/* All IXR bits */
+#define ZYNQ_SPI_IXR_ALL_MASK		GENMASK(6, 0)	/* All IXR bits */
 #define ZYNQ_SPI_ENR_SPI_EN_MASK	BIT(0)	/* SPI Enable */
 
 #define ZYNQ_SPI_FIFO_DEPTH		128

Signature · 1 line

1.9.1

Jagan Teki

author

2015-05-12 11:25 UTC #6 lore raw

v2 cover Introduce BIT and GENMASK

In reply to Jagan Teki

Quoted 12 lines · Jagan Teki

I have sent one v1 for BIT macro change for entire u-boot, but this time I'm just introduce by changing this with spi/sf code, will send more in changes in future.
Along with BIT and also introduces GENMASK with spi/sf code.
Changes for v2:
- break the BIT macro patch only for spi/sf code.
thanks!
Jagan.

Quoted 6 lines

Jagan Teki (5):
spi/sf: Add BIT macro in linux/bitops.h
spi: Remove #define BIT in local file
spi/sf: Use BIT macro from linux/bitops.h
linux/bitops.h: GENMASK copy from linux
spi: Use GENMASK instead of numeric hexcodes

Any comments on this series - early push will have enough time to test and I have more patches that need to use these macros.

Quoted 29 lines

 drivers/mtd/spi/sandbox.c      |  4 +--
 drivers/mtd/spi/sf_internal.h  | 36 ++++++++++----------
 drivers/spi/altera_spi.c       | 26 +++++++--------
 drivers/spi/atmel_spi.h        | 54 +++++++++++++++---------------
 drivers/spi/bfin_spi6xx.c      |  8 ++---
 drivers/spi/cadence_qspi_apb.c | 76 +++++++++++++++++++++---------------------
 drivers/spi/davinci_spi.c      |  2 --
 drivers/spi/designware_spi.c   | 16 ++++-----
 drivers/spi/ep93xx_spi.c       |  6 +---
 drivers/spi/exynos_spi.c       |  4 +--
 drivers/spi/fsl_dspi.c         |  2 +-
 drivers/spi/fsl_espi.c         | 20 +++++------
 drivers/spi/fsl_qspi.c         |  6 ++--
 drivers/spi/ich.c              |  4 +--
 drivers/spi/mpc8xxx_spi.c      |  2 +-
 drivers/spi/mxs_spi.c          |  2 +-
 drivers/spi/omap3_spi.h        | 64 +++++++++++++++++------------------
 drivers/spi/sh_qspi.c          | 16 ++++-----
 drivers/spi/tegra114_spi.c     | 76 +++++++++++++++++++++---------------------
 drivers/spi/tegra20_sflash.c   | 54 +++++++++++++++---------------
 drivers/spi/tegra20_slink.c    | 60 ++++++++++++++++-----------------
 drivers/spi/ti_qspi.c          | 10 +++---
 drivers/spi/xilinx_spi.c       | 46 ++++++++++++-------------
 drivers/spi/zynq_spi.c         | 22 ++++++------
 include/linux/bitops.h         | 12 +++++++
 include/spi.h                  | 46 ++++++++++++-------------
 26 files changed, 340 insertions(+), 334 deletions(-)

Quoted 2 lines

--
1.9.1

thanks!

Signature · 2 lines

Jagan Teki,
Openedev.

Marek Vasut

2015-05-12 11:33 UTC #7 lore raw

v2 cover Introduce BIT and GENMASK

Quoted 20 lines · Jagan Teki

Quoted 12 lines · Jagan Teki
I have sent one v1 for BIT macro change for entire u-boot, but this time I'm just introduce by changing this with spi/sf code, will send more in changes in future.
Along with BIT and also introduces GENMASK with spi/sf code.
Changes for v2:
- break the BIT macro patch only for spi/sf code.
thanks!
Jagan.
Quoted 6 lines
Jagan Teki (5):
spi/sf: Add BIT macro in linux/bitops.h
spi: Remove #define BIT in local file
spi/sf: Use BIT macro from linux/bitops.h
linux/bitops.h: GENMASK copy from linux
spi: Use GENMASK instead of numeric hexcodes

Quoted 2 lines

Any comments on this series - early push will have enough time to test and I have more patches that need to use these macros.

I'm not very fond of this macro, it makes the code more cryptic .

Best regards,
Marek Vasut

Tom Rini

2015-05-12 15:02 UTC #8 lore raw

v2 cover Introduce BIT and GENMASK

Quoted 21 lines · Marek Vasut

Quoted 20 lines · Jagan Teki
Quoted 18 lines · Jagan Teki
I have sent one v1 for BIT macro change for entire u-boot, but this time I'm just introduce by changing this with spi/sf code, will send more in changes in future.
Along with BIT and also introduces GENMASK with spi/sf code.
Changes for v2:
- break the BIT macro patch only for spi/sf code.
thanks!
Jagan.
Jagan Teki (5):
spi/sf: Add BIT macro in linux/bitops.h
spi: Remove #define BIT in local file
spi/sf: Use BIT macro from linux/bitops.h
linux/bitops.h: GENMASK copy from linux
spi: Use GENMASK instead of numeric hexcodes

Quoted 4 lines

Quoted 2 lines
Any comments on this series - early push will have enough time to test and I have more patches that need to use these macros.
I'm not very fond of this macro, it makes the code more cryptic .

BIT/GENMASK are (growing in usage) kernel macros, so I think it'll help us in the long run.

Signature · 8 lines

Tom
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Marek Vasut

2015-05-12 15:23 UTC #9 lore raw

v2 cover Introduce BIT and GENMASK

Quoted 22 lines · Tom Rini

Quoted 21 lines · Marek Vasut
Quoted 20 lines · Jagan Teki
Quoted 18 lines · Jagan Teki
I have sent one v1 for BIT macro change for entire u-boot, but this time I'm just introduce by changing this with spi/sf code, will send more in changes in future.
Along with BIT and also introduces GENMASK with spi/sf code.
Changes for v2:
- break the BIT macro patch only for spi/sf code.
thanks!
Jagan.
Jagan Teki (5):
spi/sf: Add BIT macro in linux/bitops.h
spi: Remove #define BIT in local file
spi/sf: Use BIT macro from linux/bitops.h
linux/bitops.h: GENMASK copy from linux
spi: Use GENMASK instead of numeric hexcodes

Quoted 7 lines

Quoted 4 lines
Quoted 2 lines
Any comments on this series - early push will have enough time to test and I have more patches that need to use these macros.
I'm not very fond of this macro, it makes the code more cryptic .
BIT/GENMASK are (growing in usage) kernel macros, so I think it'll help us in the long run.

I won't block this, but I'm not very fond of such cryptic stuff.

Best regards,
Marek Vasut

Simon Glass

2015-05-13 01:48 UTC #10 lore raw

v2 cover Introduce BIT and GENMASK

Hi,

Quoted 26 lines · Marek Vasut

Quoted 25 lines · Tom Rini
Quoted 24 lines · Marek Vasut
Quoted 22 lines · Jagan Teki
Quoted 12 lines · Jagan Teki
I have sent one v1 for BIT macro change for entire u-boot, but this time I'm just introduce by changing this with spi/sf code, will send more in changes in future.
Along with BIT and also introduces GENMASK with spi/sf code.
Changes for v2:
- break the BIT macro patch only for spi/sf code.
thanks!
Jagan.
Quoted 6 lines
Jagan Teki (5):
spi/sf: Add BIT macro in linux/bitops.h
spi: Remove #define BIT in local file
spi/sf: Use BIT macro from linux/bitops.h
linux/bitops.h: GENMASK copy from linux
spi: Use GENMASK instead of numeric hexcodes
Any comments on this series - early push will have enough time to test and I have more patches that need to use these macros.

Quoted 6 lines

Quoted 4 lines
Quoted 1 line
I'm not very fond of this macro, it makes the code more cryptic .
BIT/GENMASK are (growing in usage) kernel macros, so I think it'll help us in the long run.
I won't block this, but I'm not very fond of such cryptic stuff.

Not thrilled either, but I agree it makes sense to follow kernel practice here as elsewhere.

Regards,
Simon

Jagan Teki

author

2015-05-15 19:19 UTC #11 lore raw

v2 cover Introduce BIT and GENMASK

Quoted 31 lines · Simon Glass

Hi,
Quoted 28 lines · Marek Vasut
Quoted 27 lines · Tom Rini
Quoted 25 lines · Marek Vasut
Quoted 20 lines · Jagan Teki
Quoted 12 lines · Jagan Teki
I have sent one v1 for BIT macro change for entire u-boot, but this time I'm just introduce by changing this with spi/sf code, will send more in changes in future.
Along with BIT and also introduces GENMASK with spi/sf code.
Changes for v2:
- break the BIT macro patch only for spi/sf code.
thanks!
Jagan.
Quoted 6 lines
Jagan Teki (5):
spi/sf: Add BIT macro in linux/bitops.h
spi: Remove #define BIT in local file
spi/sf: Use BIT macro from linux/bitops.h
linux/bitops.h: GENMASK copy from linux
spi: Use GENMASK instead of numeric hexcodes
Quoted 2 lines
Any comments on this series - early push will have enough time to test and I have more patches that need to use these macros.
I'm not very fond of this macro, it makes the code more cryptic .

Quoted 7 lines

Quoted 4 lines
Quoted 2 lines
BIT/GENMASK are (growing in usage) kernel macros, so I think it'll help us in the long run.
I won't block this, but I'm not very fond of such cryptic stuff.
Not thrilled either, but I agree it makes sense to follow kernel practice here as elsewhere.

OK, then I will push these changes and probably start more updates on remaining code as well.

Any comments/reviews - pleas share.

thanks!

Signature · 2 lines

Jagan Teki,
Openedev.

Wolfgang Denk

2015-05-15 19:46 UTC #12 lore raw

v2 cover Introduce BIT and GENMASK

In reply to Tom Rini

Dear Tom,

Quoted 8 lines · In message <20150512150237.GB5267@bill-the-cat> you wrote:

Quoted 5 lines
Quoted 3 lines
Any comments on this series - early push will have enough time to test and I have more patches that need to use these macros.
I'm not very fond of this macro, it makes the code more cryptic .
BIT/GENMASK are (growing in usage) kernel macros, so I think it'll help us in the long run.

When I was U-Boot maintainer (and for quite some time after) I consequently tried to block all attempts to add such stuff. My main concern is that this stuff is inherently unportable and confusing.

For anyone fluent in programming (and others should not be allowed to contrinute code to U-Boot ;-) the phrase "(1 << 6)" cannot be misunderstood. Most programmers I know would actually prefer a direct mask, i. e. 0x40 , which can be parsed and understood even faster, but this is probably mostly a matter of taste.

But what exactly is BIT(6) ? Please keep in mind, that BIT(6) (if interpreted correctly) can be any of the following numbers:

	             0x02 - in a 8 bit data type on Power Architecture
	            0x200 - in a 16 bit data type on Power Architecture
	        0x2000000 - in a 32 bit data type on Power Architecture
	0x200000000000000 - in a 64 bit data type on Power Architecture
	             0x40 - on many other systems

Keep in mind, that on Power Architecture bit 0 is defined to be the MSB in the data type!!

My feeling is that we should prefer clarity of code and portability over temporary fashions; not many people working n more generic parts of the kernel ever care about (now) exostic architectures like PPC. Very few actually know that there are systems where bit 0 is the MSB - don't ask me how many boards I have seen where not even the hardware designers were aware of this :-(

So, in the past I would have vehemently protested against any such patches, especially when they change good code to the worse. I must admit, that currently I have neither the time nor the nerves to engage in such a semi-religious war.

But I would like to raise this concern: this code is inherently unportable and misleading! It does not help understanding of the code, but makes it more diffcult. I consider it not an improvement, on contrary.

I vote _against_ any such macros. But this is just a comment. I do not intend to formally NAK thiese patches. Thanks.

Best regards,

Wolfgang Denk

Signature · 4 lines

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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