Extend Microblaze Properties

PATCH Superseded Alistair Francis 2 participants 22 messages Jun 3, 2015 – Jun 5, 2015

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Alistair Francis

author

2015-06-03 06:57 UTC #0 lore raw

cover Extend Microblaze Properties

This patch series extends the MicroBlaze properties that I have been working on. It applies on top of my original work:
'Add Microblaze configuration options'.

This patch series converts various MicroBlaze PVR registers to properties. This then allows the individual Microblaze machine reset functions to be removed as well as some other dead code.

Alistair Francis (8):
target-microblaze: Convert use-mmu to a CPU property
target-microblaze: Convert dcache-writeback to a CPU property
target-microblaze: Convert endi to a CPU property
target-microblaze: Convert version_mask to a CPU property
target-microblaze: Convert pvr-full to a CPU property
ml605_mmu: Move the hardcoded values to the init function
s3adsp1800: Remove the hardcoded values from the reset
target-microblaze: Remove dead code

 hw/microblaze/petalogix_ml605_mmu.c      |   25 +++++++++++--------------
 hw/microblaze/petalogix_s3adsp1800_mmu.c |    9 +--------
 target-microblaze/cpu-qom.h              |    5 +++++
 target-microblaze/cpu.c                  |   23 +++++++++++++++--------
 target-microblaze/cpu.h                  |    4 ++--
 target-microblaze/helper.c               |    6 +++---
 6 files changed, 37 insertions(+), 35 deletions(-)

Alistair Francis

author

2015-06-05 00:28 UTC #1 lore raw

PATCH RESEND 2/8 target-microblaze: Convert dcache-writeback to a CPU property

Originally the dcache-writeback PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties.

Signed-off-by Alistair Francis <[email protected]>

---
 hw/microblaze/petalogix_ml605_mmu.c |    3 ++-
 target-microblaze/cpu-qom.h         |    1 +
 target-microblaze/cpu.c             |    5 +++++
 3 files changed, 8 insertions(+), 1 deletions(-)

hw/microblaze/petalogix_ml605_mmu.c +2 -1

index 05c120a..995a579 100644
@@ -70,7 +70,6 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
 
     env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
     /* setup pvr to match kernel setting */
-    env->pvr.regs[5] |= PVR5_DCACHE_WRITEBACK_MASK;
     env->pvr.regs[0] |= PVR0_ENDI;
     env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
     env->pvr.regs[4] = 0xc56b8000;

@@ -98,6 +97,8 @@ petalogix_ml605_init(MachineState *machine)
      * root instructions
      */
     object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort);
+    object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
+                             &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
 
     /* Attach emulated BRAM through the LMB.  */

target-microblaze/cpu-qom.h +1 -0

index dd37a5c..af6739f 100644
@@ -65,6 +65,7 @@ typedef struct MicroBlazeCPU {
         uint32_t base_vectors;
         uint8_t usefpu;
         bool usemmu;
+        bool dcache_writeback;
     } cfg;
 
     CPUMBState env;

target-microblaze/cpu.c +5 -0

index 37dc0fb..2a1ff64 100644
@@ -119,6 +119,9 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
     env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) |
                         (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0);
 
+    env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
+                                        PVR5_DCACHE_WRITEBACK_MASK : 0;
+
     env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family.  */
     env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);

@@ -169,6 +172,8 @@ static Property mb_properties[] = {
      */
     DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.usefpu, 2),
     DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.usemmu, true),
+    DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
+                     false),
     DEFINE_PROP_END_OF_LIST(),
 };

Signature · 1 line

1.7.1

Alistair Francis

author

2015-06-03 06:59 UTC #2 lore raw

PATCH 3/8 target-microblaze: Convert endi to a CPU property

In reply to Alistair Francis

Originally the endi PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties.

Signed-off-by Alistair Francis <[email protected]>

---
 hw/microblaze/petalogix_ml605_mmu.c |    2 +-
 target-microblaze/cpu-qom.h         |    1 +
 target-microblaze/cpu.c             |    4 +++-
 target-microblaze/cpu.h             |    2 +-
 4 files changed, 6 insertions(+), 3 deletions(-)

hw/microblaze/petalogix_ml605_mmu.c +1 -1

index 995a579..5f341c4 100644
@@ -70,7 +70,6 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
 
     env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
     /* setup pvr to match kernel setting */
-    env->pvr.regs[0] |= PVR0_ENDI;
     env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
     env->pvr.regs[4] = 0xc56b8000;
     env->pvr.regs[5] = 0xc56be000;

@@ -99,6 +98,7 @@ petalogix_ml605_init(MachineState *machine)
     object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
                              &error_abort);
+    object_property_set_bool(OBJECT(cpu), true, "endi", &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
 
     /* Attach emulated BRAM through the LMB.  */

target-microblaze/cpu-qom.h +1 -0

index af6739f..85b8f75 100644
@@ -66,6 +66,7 @@ typedef struct MicroBlazeCPU {
         uint8_t usefpu;
         bool usemmu;
         bool dcache_writeback;
+        bool endi;
     } cfg;
 
     CPUMBState env;

target-microblaze/cpu.c +3 -1

index 2a1ff64..f40df43 100644
@@ -114,7 +114,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 
     env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
                         (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0) |
-                        (cpu->cfg.usemmu ? PVR0_USE_MMU_MASK : 0);
+                        (cpu->cfg.usemmu ? PVR0_USE_MMU_MASK : 0) |
+                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0);
 
     env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) |
                         (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0);

@@ -174,6 +175,7 @@ static Property mb_properties[] = {
     DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.usemmu, true),
     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
                      false),
+    DEFINE_PROP_BOOL("endi", MicroBlazeCPU, cfg.endi, false),
     DEFINE_PROP_END_OF_LIST(),
 };

target-microblaze/cpu.h +1 -1

index 36d5120..88e6a2a 100644
@@ -124,7 +124,7 @@ typedef struct CPUMBState CPUMBState;
 #define PVR0_USE_DCACHE_MASK            0x01000000
 #define PVR0_USE_MMU_MASK               0x00800000
 #define PVR0_USE_BTC			0x00400000
-#define PVR0_ENDI			0x00200000
+#define PVR0_ENDI_MASK                  0x00200000
 #define PVR0_FAULT			0x00100000
 #define PVR0_VERSION_MASK               0x0000FF00
 #define PVR0_USER1_MASK                 0x000000FF

Signature · 1 line

1.7.1

Edgar E. Iglesias

Reviewed-by on v1 3/8

2015-06-05 00:42 UTC #3 lore raw

Re: [Qemu-devel] [PATCH RESEND v1 3/8] target-microblaze: Convert endi to a CPU property

Quoted 5 lines · Alistair Francis

Originally the endi PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties.
Signed-off-by Alistair Francis <[email protected]>

Reviewed-by Edgar E. Iglesias <[email protected]>

Quoted 77 lines

---
 hw/microblaze/petalogix_ml605_mmu.c |    2 +-
 target-microblaze/cpu-qom.h         |    1 +
 target-microblaze/cpu.c             |    4 +++-
 target-microblaze/cpu.h             |    2 +-
 4 files changed, 6 insertions(+), 3 deletions(-)

hw/microblaze/petalogix_ml605_mmu.c +1 -1

index 995a579..5f341c4 100644
@@ -70,7 +70,6 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
 
     env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
     /* setup pvr to match kernel setting */
-    env->pvr.regs[0] |= PVR0_ENDI;
     env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
     env->pvr.regs[4] = 0xc56b8000;
     env->pvr.regs[5] = 0xc56be000;

@@ -99,6 +98,7 @@ petalogix_ml605_init(MachineState *machine)
     object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
                              &error_abort);
+    object_property_set_bool(OBJECT(cpu), true, "endi", &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
 
     /* Attach emulated BRAM through the LMB.  */

target-microblaze/cpu-qom.h +1 -0

index af6739f..85b8f75 100644
@@ -66,6 +66,7 @@ typedef struct MicroBlazeCPU {
         uint8_t usefpu;
         bool usemmu;
         bool dcache_writeback;
+        bool endi;
     } cfg;
 
     CPUMBState env;

target-microblaze/cpu.c +3 -1

index 2a1ff64..f40df43 100644
@@ -114,7 +114,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 
     env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
                         (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0) |
-                        (cpu->cfg.usemmu ? PVR0_USE_MMU_MASK : 0);
+                        (cpu->cfg.usemmu ? PVR0_USE_MMU_MASK : 0) |
+                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0);
 
     env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) |
                         (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0);

@@ -174,6 +175,7 @@ static Property mb_properties[] = {
     DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.usemmu, true),
     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
                      false),
+    DEFINE_PROP_BOOL("endi", MicroBlazeCPU, cfg.endi, false),
     DEFINE_PROP_END_OF_LIST(),
 };

target-microblaze/cpu.h +1 -1

index 36d5120..88e6a2a 100644
@@ -124,7 +124,7 @@ typedef struct CPUMBState CPUMBState;
 #define PVR0_USE_DCACHE_MASK            0x01000000
 #define PVR0_USE_MMU_MASK               0x00800000
 #define PVR0_USE_BTC			0x00400000
-#define PVR0_ENDI			0x00200000
+#define PVR0_ENDI_MASK                  0x00200000
 #define PVR0_FAULT			0x00100000
 #define PVR0_VERSION_MASK               0x0000FF00
 #define PVR0_USER1_MASK                 0x000000FF

Signature · 1 line

1.7.1

Edgar E. Iglesias

2015-06-05 00:44 UTC #4 lore raw

Re: [Qemu-devel] [PATCH RESEND v1 3/8] target-microblaze: Convert endi to a CPU property

In reply to Alistair Francis

Quoted 59 lines · Alistair Francis

Originally the endi PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties.

Signed-off-by Alistair Francis <[email protected]>

---
 hw/microblaze/petalogix_ml605_mmu.c |    2 +-
 target-microblaze/cpu-qom.h         |    1 +
 target-microblaze/cpu.c             |    4 +++-
 target-microblaze/cpu.h             |    2 +-
 4 files changed, 6 insertions(+), 3 deletions(-)

hw/microblaze/petalogix_ml605_mmu.c +1 -1

index 995a579..5f341c4 100644
@@ -70,7 +70,6 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
 
     env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
     /* setup pvr to match kernel setting */
-    env->pvr.regs[0] |= PVR0_ENDI;
     env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
     env->pvr.regs[4] = 0xc56b8000;
     env->pvr.regs[5] = 0xc56be000;

@@ -99,6 +98,7 @@ petalogix_ml605_init(MachineState *machine)
     object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
                              &error_abort);
+    object_property_set_bool(OBJECT(cpu), true, "endi", &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
 
     /* Attach emulated BRAM through the LMB.  */

target-microblaze/cpu-qom.h +1 -0

index af6739f..85b8f75 100644
@@ -66,6 +66,7 @@ typedef struct MicroBlazeCPU {
         uint8_t usefpu;
         bool usemmu;
         bool dcache_writeback;
+        bool endi;
     } cfg;
 
     CPUMBState env;

target-microblaze/cpu.c +2 -1

index 2a1ff64..f40df43 100644
@@ -114,7 +114,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 
     env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
                         (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0) |
-                        (cpu->cfg.usemmu ? PVR0_USE_MMU_MASK : 0);
+                        (cpu->cfg.usemmu ? PVR0_USE_MMU_MASK : 0) |
+                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0);
 
     env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) |
                         (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0);

target-microblaze/cpu.c static Property mb_properties[] = { · line 178

Quoted 4 lines

target-microblaze/cpu.c +1 -0

@@ -174,6 +175,7 @@ static Property mb_properties[] = {
     DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.usemmu, true),
     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
                      false),
+    DEFINE_PROP_BOOL("endi", MicroBlazeCPU, cfg.endi, false),

Oh BTW, this should be endianness to match the dts bindings...

Quoted 19 lines

target-microblaze/cpu.c +0 -0

     DEFINE_PROP_END_OF_LIST(),
 };

target-microblaze/cpu.h +1 -1

index 36d5120..88e6a2a 100644
@@ -124,7 +124,7 @@ typedef struct CPUMBState CPUMBState;
 #define PVR0_USE_DCACHE_MASK            0x01000000
 #define PVR0_USE_MMU_MASK               0x00800000
 #define PVR0_USE_BTC			0x00400000
-#define PVR0_ENDI			0x00200000
+#define PVR0_ENDI_MASK                  0x00200000
 #define PVR0_FAULT			0x00100000
 #define PVR0_VERSION_MASK               0x0000FF00
 #define PVR0_USER1_MASK                 0x000000FF

Signature · 1 line

1.7.1

Alistair Francis

author

2015-06-05 02:22 UTC #5 lore raw

Re: [Qemu-devel] [PATCH RESEND v1 3/8] target-microblaze: Convert endi to a CPU property

Quoted 57 lines · Edgar E. Iglesias

Quoted 56 lines · Alistair Francis

Originally the endi PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties.

Signed-off-by Alistair Francis <[email protected]>

---
 hw/microblaze/petalogix_ml605_mmu.c |    2 +-
 target-microblaze/cpu-qom.h         |    1 +
 target-microblaze/cpu.c             |    4 +++-
 target-microblaze/cpu.h             |    2 +-
 4 files changed, 6 insertions(+), 3 deletions(-)

hw/microblaze/petalogix_ml605_mmu.c +1 -1

index 995a579..5f341c4 100644
@@ -70,7 +70,6 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
 
     env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
     /* setup pvr to match kernel setting */
-    env->pvr.regs[0] |= PVR0_ENDI;
     env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
     env->pvr.regs[4] = 0xc56b8000;
     env->pvr.regs[5] = 0xc56be000;

@@ -99,6 +98,7 @@ petalogix_ml605_init(MachineState *machine)
     object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
                              &error_abort);
+    object_property_set_bool(OBJECT(cpu), true, "endi", &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
 
     /* Attach emulated BRAM through the LMB.  */

target-microblaze/cpu-qom.h +1 -0

index af6739f..85b8f75 100644
@@ -66,6 +66,7 @@ typedef struct MicroBlazeCPU {
         uint8_t usefpu;
         bool usemmu;
         bool dcache_writeback;
+        bool endi;
     } cfg;
 
     CPUMBState env;

target-microblaze/cpu.c +2 -1

index 2a1ff64..f40df43 100644
@@ -114,7 +114,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 
     env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
                         (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0) |
-                        (cpu->cfg.usemmu ? PVR0_USE_MMU_MASK : 0);
+                        (cpu->cfg.usemmu ? PVR0_USE_MMU_MASK : 0) |
+                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0);

Quoted 10 lines

target-microblaze/cpu.c static Property mb_properties[] = { · line 178

Quoted 7 lines

target-microblaze/cpu.c +1 -0

     env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) |
                         (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0);

@@ -174,6 +175,7 @@ static Property mb_properties[] = {
     DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.usemmu, true),
     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
                      false),
+    DEFINE_PROP_BOOL("endi", MicroBlazeCPU, cfg.endi, false),

Oh BTW, this should be endianness to match the dts bindings...

Thanks Edgar,

I'll update the name

Thanks,

Alistair

Quoted 23 lines

Quoted 22 lines

target-microblaze/cpu.c +0 -0

     DEFINE_PROP_END_OF_LIST(),
 };

target-microblaze/cpu.h +1 -2

index 36d5120..88e6a2a 100644
@@ -124,7 +124,7 @@ typedef struct CPUMBState CPUMBState;
 #define PVR0_USE_DCACHE_MASK            0x01000000
 #define PVR0_USE_MMU_MASK               0x00800000
 #define PVR0_USE_BTC                 0x00400000
-#define PVR0_ENDI                    0x00200000
+#define PVR0_ENDI_MASK                  0x00200000
 #define PVR0_FAULT                   0x00100000
 #define PVR0_VERSION_MASK               0x0000FF00
 #define PVR0_USER1_MASK                 0x000000FF
--

1.7.1

Alistair Francis

author

2015-06-03 06:59 UTC #6 lore raw

PATCH 4/8 target-microblaze: Convert version_mask to a CPU property

In reply to Alistair Francis

Originally the version_mask PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties.

Signed-off-by Alistair Francis <[email protected]>

---
 hw/microblaze/petalogix_ml605_mmu.c |    3 ++-
 target-microblaze/cpu-qom.h         |    1 +
 target-microblaze/cpu.c             |    4 +++-
 3 files changed, 6 insertions(+), 2 deletions(-)

hw/microblaze/petalogix_ml605_mmu.c +2 -1

index 5f341c4..f52654c 100644
@@ -70,7 +70,7 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
 
     env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
     /* setup pvr to match kernel setting */
-    env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
+    env->pvr.regs[0] |= (0x14 << 8);
     env->pvr.regs[4] = 0xc56b8000;
     env->pvr.regs[5] = 0xc56be000;
 }

@@ -99,6 +99,7 @@ petalogix_ml605_init(MachineState *machine)
     object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
                              &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "endi", &error_abort);
+    object_property_set_bool(OBJECT(cpu), true, "version_mask", &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
 
     /* Attach emulated BRAM through the LMB.  */

target-microblaze/cpu-qom.h +1 -0

index 85b8f75..b6c6374 100644
@@ -67,6 +67,7 @@ typedef struct MicroBlazeCPU {
         bool usemmu;
         bool dcache_writeback;
         bool endi;
+        bool version_mask;
     } cfg;
 
     CPUMBState env;

target-microblaze/cpu.c +3 -1

index f40df43..849c737 100644
@@ -115,7 +115,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
     env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
                         (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0) |
                         (cpu->cfg.usemmu ? PVR0_USE_MMU_MASK : 0) |
-                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0);
+                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
+                        (cpu->cfg.endi ? ~PVR0_VERSION_MASK : 0);
 
     env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) |
                         (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0);

@@ -176,6 +177,7 @@ static Property mb_properties[] = {
     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
                      false),
     DEFINE_PROP_BOOL("endi", MicroBlazeCPU, cfg.endi, false),
+    DEFINE_PROP_BOOL("version-mask", MicroBlazeCPU, cfg.version_mask, false),
     DEFINE_PROP_END_OF_LIST(),
 };

Signature · 1 line

1.7.1

Edgar E. Iglesias

2015-06-05 00:46 UTC #7 lore raw

Re: [Qemu-devel] [PATCH RESEND v1 4/8] target-microblaze: Convert version_mask to a CPU property

Quoted 49 lines · Alistair Francis

Originally the version_mask PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties.

Signed-off-by Alistair Francis <[email protected]>

---
 hw/microblaze/petalogix_ml605_mmu.c |    3 ++-
 target-microblaze/cpu-qom.h         |    1 +
 target-microblaze/cpu.c             |    4 +++-
 3 files changed, 6 insertions(+), 2 deletions(-)

hw/microblaze/petalogix_ml605_mmu.c +2 -1

index 5f341c4..f52654c 100644
@@ -70,7 +70,7 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
 
     env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
     /* setup pvr to match kernel setting */
-    env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
+    env->pvr.regs[0] |= (0x14 << 8);
     env->pvr.regs[4] = 0xc56b8000;
     env->pvr.regs[5] = 0xc56be000;
 }

@@ -99,6 +99,7 @@ petalogix_ml605_init(MachineState *machine)
     object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
                              &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "endi", &error_abort);
+    object_property_set_bool(OBJECT(cpu), true, "version_mask", &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
 
     /* Attach emulated BRAM through the LMB.  */

target-microblaze/cpu-qom.h +1 -0

index 85b8f75..b6c6374 100644
@@ -67,6 +67,7 @@ typedef struct MicroBlazeCPU {
         bool usemmu;
         bool dcache_writeback;
         bool endi;
+        bool version_mask;
     } cfg;
 
     CPUMBState env;

target-microblaze/cpu.c +0 -0

index f40df43..849c737 100644

target-microblaze/cpu.c static void mb_cpu_realizefn(DeviceState *dev, Error **errp) · line 119

Quoted 6 lines

target-microblaze/cpu.c +2 -1

@@ -115,7 +115,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
     env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
                         (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0) |
                         (cpu->cfg.usemmu ? PVR0_USE_MMU_MASK : 0) |
-                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0);
+                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
+                        (cpu->cfg.endi ? ~PVR0_VERSION_MASK : 0);

This looks wrong...

My guess is that this should be:
cpu->cfg.version_mask ? PVR0_VERSION_MASK : 0

and that maybe the ml605_mmu board is trying to disable the version mask, e.g setting it to false.

Can you double check that it matches with dts and specs?

Quoted 14 lines

target-microblaze/cpu.c +1 -0

     env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) |
                         (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0);

@@ -176,6 +177,7 @@ static Property mb_properties[] = {
     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
                      false),
     DEFINE_PROP_BOOL("endi", MicroBlazeCPU, cfg.endi, false),
+    DEFINE_PROP_BOOL("version-mask", MicroBlazeCPU, cfg.version_mask, false),
     DEFINE_PROP_END_OF_LIST(),
 };

Signature · 1 line

1.7.1

Alistair Francis

author

2015-06-05 02:52 UTC #8 lore raw

Re: [Qemu-devel] [PATCH RESEND v1 4/8] target-microblaze: Convert version_mask to a CPU property

Quoted 59 lines · Edgar E. Iglesias

Quoted 49 lines · Alistair Francis

Originally the version_mask PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties.

Signed-off-by Alistair Francis <[email protected]>

---
 hw/microblaze/petalogix_ml605_mmu.c |    3 ++-
 target-microblaze/cpu-qom.h         |    1 +
 target-microblaze/cpu.c             |    4 +++-
 3 files changed, 6 insertions(+), 2 deletions(-)

hw/microblaze/petalogix_ml605_mmu.c +2 -1

index 5f341c4..f52654c 100644
@@ -70,7 +70,7 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
 
     env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
     /* setup pvr to match kernel setting */
-    env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
+    env->pvr.regs[0] |= (0x14 << 8);
     env->pvr.regs[4] = 0xc56b8000;
     env->pvr.regs[5] = 0xc56be000;
 }

@@ -99,6 +99,7 @@ petalogix_ml605_init(MachineState *machine)
     object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
                              &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "endi", &error_abort);
+    object_property_set_bool(OBJECT(cpu), true, "version_mask", &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
 
     /* Attach emulated BRAM through the LMB.  */

target-microblaze/cpu-qom.h +1 -0

index 85b8f75..b6c6374 100644
@@ -67,6 +67,7 @@ typedef struct MicroBlazeCPU {
         bool usemmu;
         bool dcache_writeback;
         bool endi;
+        bool version_mask;
     } cfg;
 
     CPUMBState env;

target-microblaze/cpu.c +0 -0

index f40df43..849c737 100644

target-microblaze/cpu.c static void mb_cpu_realizefn(DeviceState *dev, Error **errp) · line 119

Quoted 6 lines

target-microblaze/cpu.c +2 -1

@@ -115,7 +115,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
     env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
                         (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0) |
                         (cpu->cfg.usemmu ? PVR0_USE_MMU_MASK : 0) |
-                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0);
+                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
+                        (cpu->cfg.endi ? ~PVR0_VERSION_MASK : 0);

This looks wrong...

Quoted 2 lines

My guess is that this should be:
cpu->cfg.version_mask ? PVR0_VERSION_MASK : 0

So looking at the spec more the version mask should be a two byte number that indicated the version. I can't see it in the DTS, so I think it should be a settable number, not a bool.

I'm not sure why it zeroes it out though,

Thanks,

Alistair

Quoted 22 lines

and that maybe the ml605_mmu board is trying to disable the version mask, e.g setting it to false.

Can you double check that it matches with dts and specs?

Quoted 14 lines

target-microblaze/cpu.c +1 -1

     env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) |
                         (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0);

@@ -176,6 +177,7 @@ static Property mb_properties[] = {
     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
                      false),
     DEFINE_PROP_BOOL("endi", MicroBlazeCPU, cfg.endi, false),
+    DEFINE_PROP_BOOL("version-mask", MicroBlazeCPU, cfg.version_mask, false),
     DEFINE_PROP_END_OF_LIST(),
 };
 
--

1.7.1

Alistair Francis

author

2015-06-05 02:53 UTC #9 lore raw

Re: [Qemu-devel] [PATCH RESEND v1 4/8] target-microblaze: Convert version_mask to a CPU property

Quoted 61 lines · Alistair Francis

Quoted 59 lines · Edgar E. Iglesias

Quoted 49 lines · Alistair Francis

Originally the version_mask PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties.

Signed-off-by Alistair Francis <[email protected]>

---
 hw/microblaze/petalogix_ml605_mmu.c |    3 ++-
 target-microblaze/cpu-qom.h         |    1 +
 target-microblaze/cpu.c             |    4 +++-
 3 files changed, 6 insertions(+), 2 deletions(-)

hw/microblaze/petalogix_ml605_mmu.c +2 -1

index 5f341c4..f52654c 100644
@@ -70,7 +70,7 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
 
     env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
     /* setup pvr to match kernel setting */
-    env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
+    env->pvr.regs[0] |= (0x14 << 8);
     env->pvr.regs[4] = 0xc56b8000;
     env->pvr.regs[5] = 0xc56be000;
 }

@@ -99,6 +99,7 @@ petalogix_ml605_init(MachineState *machine)
     object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
                              &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "endi", &error_abort);
+    object_property_set_bool(OBJECT(cpu), true, "version_mask", &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
 
     /* Attach emulated BRAM through the LMB.  */

target-microblaze/cpu-qom.h +1 -0

index 85b8f75..b6c6374 100644
@@ -67,6 +67,7 @@ typedef struct MicroBlazeCPU {
         bool usemmu;
         bool dcache_writeback;
         bool endi;
+        bool version_mask;
     } cfg;
 
     CPUMBState env;

target-microblaze/cpu.c +0 -0

index f40df43..849c737 100644

target-microblaze/cpu.c static void mb_cpu_realizefn(DeviceState *dev, Error **errp) · line 119

Quoted 6 lines

target-microblaze/cpu.c +2 -1

@@ -115,7 +115,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
     env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
                         (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0) |
                         (cpu->cfg.usemmu ? PVR0_USE_MMU_MASK : 0) |
-                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0);
+                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
+                        (cpu->cfg.endi ? ~PVR0_VERSION_MASK : 0);

This looks wrong...

Quoted 4 lines

Quoted 2 lines
My guess is that this should be:
cpu->cfg.version_mask ? PVR0_VERSION_MASK : 0
So looking at the spec more the version mask should be a two byte

Woops, I meant one byte number.

Thanks,

Alistair

Quoted 31 lines

number that indicated the version. I can't see it in the DTS, so I think it should be a settable number, not a bool.
I'm not sure why it zeroes it out though,
Thanks,
Alistair
Quoted 22 lines
and that maybe the ml605_mmu board is trying to disable the version mask, e.g setting it to false.
Can you double check that it matches with dts and specs?
Quoted 14 lines
target-microblaze/cpu.c +1 -1
     env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) |
                         (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0);
@@ -176,6 +177,7 @@ static Property mb_properties[] = {
     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
                      false),
     DEFINE_PROP_BOOL("endi", MicroBlazeCPU, cfg.endi, false),
+    DEFINE_PROP_BOOL("version-mask", MicroBlazeCPU, cfg.version_mask, false),
     DEFINE_PROP_END_OF_LIST(),
 };
 
--
1.7.1

Edgar E. Iglesias

2015-06-05 02:59 UTC #10 lore raw

Re: [Qemu-devel] [PATCH RESEND v1 4/8] target-microblaze: Convert version_mask to a CPU property

Quoted 66 lines · Alistair Francis

Quoted 64 lines · Alistair Francis

Quoted 61 lines · Edgar E. Iglesias

Quoted 49 lines · Alistair Francis

Originally the version_mask PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties.

Signed-off-by Alistair Francis <[email protected]>

---
 hw/microblaze/petalogix_ml605_mmu.c |    3 ++-
 target-microblaze/cpu-qom.h         |    1 +
 target-microblaze/cpu.c             |    4 +++-
 3 files changed, 6 insertions(+), 2 deletions(-)

hw/microblaze/petalogix_ml605_mmu.c +2 -1

index 5f341c4..f52654c 100644
@@ -70,7 +70,7 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
 
     env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
     /* setup pvr to match kernel setting */
-    env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
+    env->pvr.regs[0] |= (0x14 << 8);
     env->pvr.regs[4] = 0xc56b8000;
     env->pvr.regs[5] = 0xc56be000;
 }

@@ -99,6 +99,7 @@ petalogix_ml605_init(MachineState *machine)
     object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
                              &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "endi", &error_abort);
+    object_property_set_bool(OBJECT(cpu), true, "version_mask", &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
 
     /* Attach emulated BRAM through the LMB.  */

target-microblaze/cpu-qom.h +1 -0

index 85b8f75..b6c6374 100644
@@ -67,6 +67,7 @@ typedef struct MicroBlazeCPU {
         bool usemmu;
         bool dcache_writeback;
         bool endi;
+        bool version_mask;
     } cfg;
 
     CPUMBState env;

target-microblaze/cpu.c +0 -0

index f40df43..849c737 100644

target-microblaze/cpu.c static void mb_cpu_realizefn(DeviceState *dev, Error **errp) · line 119

Quoted 6 lines

target-microblaze/cpu.c +2 -1

@@ -115,7 +115,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
     env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
                         (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0) |
                         (cpu->cfg.usemmu ? PVR0_USE_MMU_MASK : 0) |
-                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0);
+                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
+                        (cpu->cfg.endi ? ~PVR0_VERSION_MASK : 0);

This looks wrong...

My guess is that this should be:
cpu->cfg.version_mask ? PVR0_VERSION_MASK : 0

Quoted 12 lines

Quoted 1 line
So looking at the spec more the version mask should be a two byte
Woops, I meant one byte number.
Thanks,
Alistair
Quoted 4 lines
number that indicated the version. I can't see it in the DTS, so I think it should be a settable number, not a bool.
I'm not sure why it zeroes it out though,

Aha I see now, the ml605 is forcing the CPU version to "8.00.b".

Shouldn't this prop just be a string with the re-encoding to version field done by the CPU model?

Cheers,
Edgar

Quoted 27 lines

Thanks,

Alistair

Quoted 22 lines

and that maybe the ml605_mmu board is trying to disable the version mask, e.g setting it to false.

Can you double check that it matches with dts and specs?

Quoted 14 lines

target-microblaze/cpu.c +1 -1

     env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) |
                         (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0);

@@ -176,6 +177,7 @@ static Property mb_properties[] = {
     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
                      false),
     DEFINE_PROP_BOOL("endi", MicroBlazeCPU, cfg.endi, false),
+    DEFINE_PROP_BOOL("version-mask", MicroBlazeCPU, cfg.version_mask, false),
     DEFINE_PROP_END_OF_LIST(),
 };
 
--

1.7.1

Alistair Francis

author

2015-06-05 03:20 UTC #11 lore raw

Re: [Qemu-devel] [PATCH RESEND v1 4/8] target-microblaze: Convert version_mask to a CPU property

Quoted 78 lines · Edgar E. Iglesias

Quoted 77 lines · Alistair Francis

Quoted 61 lines · Alistair Francis

Quoted 59 lines · Edgar E. Iglesias

Quoted 49 lines · Alistair Francis

Originally the version_mask PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties.

Signed-off-by Alistair Francis <[email protected]>

---
 hw/microblaze/petalogix_ml605_mmu.c |    3 ++-
 target-microblaze/cpu-qom.h         |    1 +
 target-microblaze/cpu.c             |    4 +++-
 3 files changed, 6 insertions(+), 2 deletions(-)

hw/microblaze/petalogix_ml605_mmu.c +2 -1

index 5f341c4..f52654c 100644
@@ -70,7 +70,7 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
 
     env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
     /* setup pvr to match kernel setting */
-    env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
+    env->pvr.regs[0] |= (0x14 << 8);
     env->pvr.regs[4] = 0xc56b8000;
     env->pvr.regs[5] = 0xc56be000;
 }

@@ -99,6 +99,7 @@ petalogix_ml605_init(MachineState *machine)
     object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
                              &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "endi", &error_abort);
+    object_property_set_bool(OBJECT(cpu), true, "version_mask", &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
 
     /* Attach emulated BRAM through the LMB.  */

target-microblaze/cpu-qom.h +1 -0

index 85b8f75..b6c6374 100644
@@ -67,6 +67,7 @@ typedef struct MicroBlazeCPU {
         bool usemmu;
         bool dcache_writeback;
         bool endi;
+        bool version_mask;
     } cfg;
 
     CPUMBState env;

target-microblaze/cpu.c +0 -0

index f40df43..849c737 100644

target-microblaze/cpu.c static void mb_cpu_realizefn(DeviceState *dev, Error **errp) · line 119

Quoted 6 lines

target-microblaze/cpu.c +2 -1

@@ -115,7 +115,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
     env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
                         (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0) |
                         (cpu->cfg.usemmu ? PVR0_USE_MMU_MASK : 0) |
-                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0);
+                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
+                        (cpu->cfg.endi ? ~PVR0_VERSION_MASK : 0);

This looks wrong...

Quoted 4 lines

Quoted 2 lines
My guess is that this should be:
cpu->cfg.version_mask ? PVR0_VERSION_MASK : 0
So looking at the spec more the version mask should be a two byte

Woops, I meant one byte number.

Thanks,

Alistair

Quoted 3 lines

number that indicated the version. I can't see it in the DTS, so I think it should be a settable number, not a bool.

Quoted 6 lines

Quoted 1 line
Quoted 1 line
I'm not sure why it zeroes it out though,
Aha I see now, the ml605 is forcing the CPU version to "8.00.b".
Shouldn't this prop just be a string with the re-encoding to version field done by the CPU model?

Yeah, you are right. That is a much better idea

Thanks,

Alistair

Quoted 33 lines

Cheers,
Edgar

Quoted 27 lines

Thanks,

Alistair

Quoted 22 lines

and that maybe the ml605_mmu board is trying to disable the version mask, e.g setting it to false.

Can you double check that it matches with dts and specs?

Quoted 14 lines

target-microblaze/cpu.c +1 -1

     env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) |
                         (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0);

@@ -176,6 +177,7 @@ static Property mb_properties[] = {
     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
                      false),
     DEFINE_PROP_BOOL("endi", MicroBlazeCPU, cfg.endi, false),
+    DEFINE_PROP_BOOL("version-mask", MicroBlazeCPU, cfg.version_mask, false),
     DEFINE_PROP_END_OF_LIST(),
 };
 
--

1.7.1

Alistair Francis

author

2015-06-03 07:00 UTC #12 lore raw

PATCH 5/8 target-microblaze: Convert pvr-full to a CPU property

In reply to Alistair Francis

Originally the pvr-full PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties.

Signed-off-by Alistair Francis <[email protected]>

---
 target-microblaze/cpu-qom.h |    1 +
 target-microblaze/cpu.c     |    7 ++++---
 target-microblaze/helper.c  |    4 ++--
 3 files changed, 7 insertions(+), 5 deletions(-)

target-microblaze/cpu-qom.h +1 -0

index b6c6374..799f5b8 100644
@@ -68,6 +68,7 @@ typedef struct MicroBlazeCPU {
         bool dcache_writeback;
         bool endi;
         bool version_mask;
+        bool pvr_full;
     } cfg;
 
     CPUMBState env;

target-microblaze/cpu.c +4 -3

index 849c737..329d4d5 100644
@@ -91,8 +91,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 
     qemu_init_vcpu(cs);
 
-    env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
-                       | PVR0_USE_BARREL_MASK \
+    env->pvr.regs[0] = PVR0_USE_BARREL_MASK \
                        | PVR0_USE_DIV_MASK \
                        | PVR0_USE_HW_MUL_MASK \
                        | PVR0_USE_EXC_MASK \

@@ -116,7 +115,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
                         (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0) |
                         (cpu->cfg.usemmu ? PVR0_USE_MMU_MASK : 0) |
                         (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
-                        (cpu->cfg.endi ? ~PVR0_VERSION_MASK : 0);
+                        (cpu->cfg.endi ? ~PVR0_VERSION_MASK : 0) |
+                        (cpu->cfg.pvr_full ? PVR0_PVR_FULL_MASK : 0);
 
     env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) |
                         (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0);

@@ -178,6 +178,7 @@ static Property mb_properties[] = {
                      false),
     DEFINE_PROP_BOOL("endi", MicroBlazeCPU, cfg.endi, false),
     DEFINE_PROP_BOOL("version-mask", MicroBlazeCPU, cfg.version_mask, false),
+    DEFINE_PROP_BOOL("pvr-full", MicroBlazeCPU, cfg.pvr_full, true),
     DEFINE_PROP_END_OF_LIST(),
 };

target-microblaze/helper.c +2 -2

index b310c2b..55b92e2 100644
@@ -58,8 +58,8 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
     mmu_available = 0;
     if (cpu->cfg.usemmu) {
         mmu_available = 1;
-        if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
-            && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
+        if (cpu->cfg.pvr_full &&
+            (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
             mmu_available = 0;
         }
     }

Signature · 1 line

1.7.1

Edgar E. Iglesias

2015-06-05 00:48 UTC #13 lore raw

Re: [Qemu-devel] [PATCH RESEND v1 5/8] target-microblaze: Convert pvr-full to a CPU property

Quoted 48 lines · Alistair Francis

Originally the pvr-full PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties.

Signed-off-by Alistair Francis <[email protected]>

---
 target-microblaze/cpu-qom.h |    1 +
 target-microblaze/cpu.c     |    7 ++++---
 target-microblaze/helper.c  |    4 ++--
 3 files changed, 7 insertions(+), 5 deletions(-)

target-microblaze/cpu-qom.h +1 -0

index b6c6374..799f5b8 100644
@@ -68,6 +68,7 @@ typedef struct MicroBlazeCPU {
         bool dcache_writeback;
         bool endi;
         bool version_mask;
+        bool pvr_full;
     } cfg;
 
     CPUMBState env;

target-microblaze/cpu.c +3 -3

index 849c737..329d4d5 100644
@@ -91,8 +91,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 
     qemu_init_vcpu(cs);
 
-    env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
-                       | PVR0_USE_BARREL_MASK \
+    env->pvr.regs[0] = PVR0_USE_BARREL_MASK \
                        | PVR0_USE_DIV_MASK \
                        | PVR0_USE_HW_MUL_MASK \
                        | PVR0_USE_EXC_MASK \

@@ -116,7 +115,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
                         (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0) |
                         (cpu->cfg.usemmu ? PVR0_USE_MMU_MASK : 0) |
                         (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
-                        (cpu->cfg.endi ? ~PVR0_VERSION_MASK : 0);
+                        (cpu->cfg.endi ? ~PVR0_VERSION_MASK : 0) |
+                        (cpu->cfg.pvr_full ? PVR0_PVR_FULL_MASK : 0);
 
     env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) |
                         (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0);

target-microblaze/cpu.c static Property mb_properties[] = { · line 181

Quoted 4 lines

target-microblaze/cpu.c +1 -0

@@ -178,6 +178,7 @@ static Property mb_properties[] = {
                      false),
     DEFINE_PROP_BOOL("endi", MicroBlazeCPU, cfg.endi, false),
     DEFINE_PROP_BOOL("version-mask", MicroBlazeCPU, cfg.version_mask, false),
+    DEFINE_PROP_BOOL("pvr-full", MicroBlazeCPU, cfg.pvr_full, true),

This is another one with wierdo dts mapping.

You can look our tree hw/microblaze/microblaze_generic_fdt.c to figure it out.

Quoted 21 lines

target-microblaze/cpu.c +0 -0

     DEFINE_PROP_END_OF_LIST(),
 };

target-microblaze/helper.c +2 -2

index b310c2b..55b92e2 100644
@@ -58,8 +58,8 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
     mmu_available = 0;
     if (cpu->cfg.usemmu) {
         mmu_available = 1;
-        if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
-            && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
+        if (cpu->cfg.pvr_full &&
+            (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
             mmu_available = 0;
         }
     }

Signature · 1 line

1.7.1

Alistair Francis

author

2015-06-05 03:01 UTC #14 lore raw

Re: [Qemu-devel] [PATCH RESEND v1 5/8] target-microblaze: Convert pvr-full to a CPU property

Quoted 56 lines · Edgar E. Iglesias

Quoted 48 lines · Alistair Francis

Originally the pvr-full PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties.

Signed-off-by Alistair Francis <[email protected]>

---
 target-microblaze/cpu-qom.h |    1 +
 target-microblaze/cpu.c     |    7 ++++---
 target-microblaze/helper.c  |    4 ++--
 3 files changed, 7 insertions(+), 5 deletions(-)

target-microblaze/cpu-qom.h +1 -0

index b6c6374..799f5b8 100644
@@ -68,6 +68,7 @@ typedef struct MicroBlazeCPU {
         bool dcache_writeback;
         bool endi;
         bool version_mask;
+        bool pvr_full;
     } cfg;
 
     CPUMBState env;

target-microblaze/cpu.c +3 -3

index 849c737..329d4d5 100644
@@ -91,8 +91,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 
     qemu_init_vcpu(cs);
 
-    env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
-                       | PVR0_USE_BARREL_MASK \
+    env->pvr.regs[0] = PVR0_USE_BARREL_MASK \
                        | PVR0_USE_DIV_MASK \
                        | PVR0_USE_HW_MUL_MASK \
                        | PVR0_USE_EXC_MASK \

@@ -116,7 +115,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
                         (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0) |
                         (cpu->cfg.usemmu ? PVR0_USE_MMU_MASK : 0) |
                         (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
-                        (cpu->cfg.endi ? ~PVR0_VERSION_MASK : 0);
+                        (cpu->cfg.endi ? ~PVR0_VERSION_MASK : 0) |
+                        (cpu->cfg.pvr_full ? PVR0_PVR_FULL_MASK : 0);
 
     env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) |
                         (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0);

target-microblaze/cpu.c static Property mb_properties[] = { · line 181

Quoted 4 lines

target-microblaze/cpu.c +1 -0

@@ -178,6 +178,7 @@ static Property mb_properties[] = {
                      false),
     DEFINE_PROP_BOOL("endi", MicroBlazeCPU, cfg.endi, false),
     DEFINE_PROP_BOOL("version-mask", MicroBlazeCPU, cfg.version_mask, false),
+    DEFINE_PROP_BOOL("pvr-full", MicroBlazeCPU, cfg.pvr_full, true),

This is another one with wierdo dts mapping.

Quoted 1 line

You can look our tree hw/microblaze/microblaze_generic_fdt.c to figure it out.

Thanks Edgar

Alistair

Quoted 23 lines

Quoted 22 lines

target-microblaze/cpu.c +0 -0

     DEFINE_PROP_END_OF_LIST(),
 };

target-microblaze/helper.c +2 -3

index b310c2b..55b92e2 100644
@@ -58,8 +58,8 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
     mmu_available = 0;
     if (cpu->cfg.usemmu) {
         mmu_available = 1;
-        if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
-            && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
+        if (cpu->cfg.pvr_full &&
+            (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
             mmu_available = 0;
         }
     }
--

1.7.1

Alistair Francis

author

2015-06-03 07:01 UTC #15 lore raw

PATCH 6/8 ml605_mmu: Move the hardcoded values to the init function

In reply to Alistair Francis

Move the hard coded register values to the init function. This also allows the entire reset function to be deleted, as PVR registers are now preserved on reset.

Signed-off-by Alistair Francis <[email protected]>

---
 hw/microblaze/petalogix_ml605_mmu.c |   19 +++++++------------
 1 files changed, 7 insertions(+), 12 deletions(-)

hw/microblaze/petalogix_ml605_mmu.c +7 ~~-12~~

index f52654c..140a9d9 100644
@@ -64,17 +64,6 @@
 #define SPI_IRQ             4
 #define UART16550_IRQ       5
 
-static void machine_cpu_reset(MicroBlazeCPU *cpu)
-{
-    CPUMBState *env = &cpu->env;
-
-    env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
-    /* setup pvr to match kernel setting */
-    env->pvr.regs[0] |= (0x14 << 8);
-    env->pvr.regs[4] = 0xc56b8000;
-    env->pvr.regs[5] = 0xc56be000;
-}
-
 static void
 petalogix_ml605_init(MachineState *machine)
 {

@@ -206,10 +195,16 @@ petalogix_ml605_init(MachineState *machine)
         }
     }
 
+    /* setup PVR to match kernel settings */
+    cpu->env.pvr.regs[0] |= (0x14 << 8);
+    cpu->env.pvr.regs[4] = 0xc56b8000;
+    cpu->env.pvr.regs[5] = 0xc56be000;
+    cpu->env.pvr.regs[10] = 0x0e000000; /* virtex 6 */
+
     microblaze_load_kernel(cpu, MEMORY_BASEADDR, ram_size,
                            machine->initrd_filename,
                            BINARY_DEVICE_TREE_FILE,
-                           machine_cpu_reset);
+                           NULL);
 
 }

Signature · 1 line

1.7.1

Edgar E. Iglesias

2015-06-05 00:51 UTC #16 lore raw

Re: [Qemu-devel] [PATCH RESEND v1 6/8] ml605_mmu: Move the hardcoded values to the init function

Quoted 3 lines · Alistair Francis

Move the hard coded register values to the init function. This also allows the entire reset function to be deleted, as PVR registers are now preserved on reset.

This looks OK but I assume that the remaining pvr settings will gradually move towards props?

Quoted 49 lines

Signed-off-by Alistair Francis <[email protected]>

---
 hw/microblaze/petalogix_ml605_mmu.c |   19 +++++++------------
 1 files changed, 7 insertions(+), 12 deletions(-)

hw/microblaze/petalogix_ml605_mmu.c +7 ~~-12~~

index f52654c..140a9d9 100644
@@ -64,17 +64,6 @@
 #define SPI_IRQ             4
 #define UART16550_IRQ       5
 
-static void machine_cpu_reset(MicroBlazeCPU *cpu)
-{
-    CPUMBState *env = &cpu->env;
-
-    env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
-    /* setup pvr to match kernel setting */
-    env->pvr.regs[0] |= (0x14 << 8);
-    env->pvr.regs[4] = 0xc56b8000;
-    env->pvr.regs[5] = 0xc56be000;
-}
-
 static void
 petalogix_ml605_init(MachineState *machine)
 {

@@ -206,10 +195,16 @@ petalogix_ml605_init(MachineState *machine)
         }
     }
 
+    /* setup PVR to match kernel settings */
+    cpu->env.pvr.regs[0] |= (0x14 << 8);
+    cpu->env.pvr.regs[4] = 0xc56b8000;
+    cpu->env.pvr.regs[5] = 0xc56be000;
+    cpu->env.pvr.regs[10] = 0x0e000000; /* virtex 6 */
+
     microblaze_load_kernel(cpu, MEMORY_BASEADDR, ram_size,
                            machine->initrd_filename,
                            BINARY_DEVICE_TREE_FILE,
-                           machine_cpu_reset);
+                           NULL);
 
 }

Signature · 1 line

1.7.1

Alistair Francis

author

2015-06-05 04:54 UTC #17 lore raw

Re: [Qemu-devel] [PATCH RESEND v1 6/8] ml605_mmu: Move the hardcoded values to the init function

Quoted 7 lines · Edgar E. Iglesias

Quoted 3 lines · Alistair Francis
Move the hard coded register values to the init function. This also allows the entire reset function to be deleted, as PVR registers are now preserved on reset.
This looks OK but I assume that the remaining pvr settings will gradually move towards props?

That's the plan. I removed one more in version 2

Thanks,

Alistair

Quoted 54 lines

Quoted 53 lines

Signed-off-by Alistair Francis <[email protected]>

---
 hw/microblaze/petalogix_ml605_mmu.c |   19 +++++++------------
 1 files changed, 7 insertions(+), 12 deletions(-)

hw/microblaze/petalogix_ml605_mmu.c +7 ~~-13~~

index f52654c..140a9d9 100644
@@ -64,17 +64,6 @@
 #define SPI_IRQ             4
 #define UART16550_IRQ       5
 
-static void machine_cpu_reset(MicroBlazeCPU *cpu)
-{
-    CPUMBState *env = &cpu->env;
-
-    env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
-    /* setup pvr to match kernel setting */
-    env->pvr.regs[0] |= (0x14 << 8);
-    env->pvr.regs[4] = 0xc56b8000;
-    env->pvr.regs[5] = 0xc56be000;
-}
-
 static void
 petalogix_ml605_init(MachineState *machine)
 {

@@ -206,10 +195,16 @@ petalogix_ml605_init(MachineState *machine)
         }
     }
 
+    /* setup PVR to match kernel settings */
+    cpu->env.pvr.regs[0] |= (0x14 << 8);
+    cpu->env.pvr.regs[4] = 0xc56b8000;
+    cpu->env.pvr.regs[5] = 0xc56be000;
+    cpu->env.pvr.regs[10] = 0x0e000000; /* virtex 6 */
+
     microblaze_load_kernel(cpu, MEMORY_BASEADDR, ram_size,
                            machine->initrd_filename,
                            BINARY_DEVICE_TREE_FILE,
-                           machine_cpu_reset);
+                           NULL);
 
 }
 
--

1.7.1

Alistair Francis

author

2015-06-03 07:01 UTC #18 lore raw

PATCH 7/8 s3adsp1800: Remove the hardcoded values from the reset

In reply to Alistair Francis

Remove the hardcoded values from the machine specific reset function, as the same values are already set in the standard MicroBlaze reset.

This also allows the entire reset function to be deleted, as PVR registers are now preserved on reset.

Signed-off-by Alistair Francis <[email protected]>

---
 hw/microblaze/petalogix_s3adsp1800_mmu.c |    9 +--------
 1 files changed, 1 insertions(+), 8 deletions(-)

hw/microblaze/petalogix_s3adsp1800_mmu.c +1 -8

index 84f6e74..7109e63 100644
@@ -51,13 +51,6 @@
 #define ETHLITE_IRQ         1
 #define UARTLITE_IRQ        3
 
-static void machine_cpu_reset(MicroBlazeCPU *cpu)
-{
-    CPUMBState *env = &cpu->env;
-
-    env->pvr.regs[10] = 0x0c000000; /* spartan 3a dsp family.  */
-}
-
 static void
 petalogix_s3adsp1800_init(MachineState *machine)
 {

@@ -132,7 +125,7 @@ petalogix_s3adsp1800_init(MachineState *machine)
     microblaze_load_kernel(cpu, ddr_base, ram_size,
                            machine->initrd_filename,
                            BINARY_DEVICE_TREE_FILE,
-                           machine_cpu_reset);
+                           NULL);
 }
 
 static QEMUMachine petalogix_s3adsp1800_machine = {

Signature · 1 line

1.7.1

Edgar E. Iglesias

Reviewed-by on v1 7/8

2015-06-05 00:52 UTC #19 lore raw

Re: [Qemu-devel] [PATCH RESEND v1 7/8] s3adsp1800: Remove the hardcoded values from the reset

Quoted 8 lines · Alistair Francis

Remove the hardcoded values from the machine specific reset function, as the same values are already set in the standard MicroBlaze reset.
This also allows the entire reset function to be deleted, as PVR registers are now preserved on reset.
Signed-off-by Alistair Francis <[email protected]>

Reviewed-by Edgar E. Iglesias <[email protected]>

Quoted 34 lines

---
 hw/microblaze/petalogix_s3adsp1800_mmu.c |    9 +--------
 1 files changed, 1 insertions(+), 8 deletions(-)

hw/microblaze/petalogix_s3adsp1800_mmu.c +1 -8

index 84f6e74..7109e63 100644
@@ -51,13 +51,6 @@
 #define ETHLITE_IRQ         1
 #define UARTLITE_IRQ        3
 
-static void machine_cpu_reset(MicroBlazeCPU *cpu)
-{
-    CPUMBState *env = &cpu->env;
-
-    env->pvr.regs[10] = 0x0c000000; /* spartan 3a dsp family.  */
-}
-
 static void
 petalogix_s3adsp1800_init(MachineState *machine)
 {

@@ -132,7 +125,7 @@ petalogix_s3adsp1800_init(MachineState *machine)
     microblaze_load_kernel(cpu, ddr_base, ram_size,
                            machine->initrd_filename,
                            BINARY_DEVICE_TREE_FILE,
-                           machine_cpu_reset);
+                           NULL);
 }
 
 static QEMUMachine petalogix_s3adsp1800_machine = {

Signature · 1 line

1.7.1

Alistair Francis

author

2015-06-03 07:02 UTC #20 lore raw

PATCH 8/8 target-microblaze: Remove dead code

In reply to Alistair Francis

This code is already being run in the mb_cpu_realizefn() function. As PVR registers are preserved on reset this code is not required.

Signed-off-by Alistair Francis <[email protected]>

---
 target-microblaze/cpu.c |    4 ----
 1 files changed, 0 insertions(+), 4 deletions(-)

target-microblaze/cpu.c +0 -4

index 329d4d5..437250d 100644
@@ -129,10 +129,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 
     env->sregs[SR_PC] = cpu->cfg.base_vectors;
 
-#if defined(CONFIG_USER_ONLY)
-    env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp.  */
-#endif
-
     mcc->parent_realize(dev, errp);
 }

Signature · 1 line

1.7.1

Edgar E. Iglesias

Reviewed-by on v1 8/8

2015-06-05 00:52 UTC #21 lore raw

Re: [Qemu-devel] [PATCH RESEND v1 8/8] target-microblaze: Remove dead code

Quoted 3 lines · Alistair Francis

This code is already being run in the mb_cpu_realizefn() function. As PVR registers are preserved on reset this code is not required.

Reviewed-by Edgar E. Iglesias <[email protected]>

Quoted 24 lines

Signed-off-by Alistair Francis <[email protected]>

---
 target-microblaze/cpu.c |    4 ----
 1 files changed, 0 insertions(+), 4 deletions(-)

target-microblaze/cpu.c +0 -4

index 329d4d5..437250d 100644
@@ -129,10 +129,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 
     env->sregs[SR_PC] = cpu->cfg.base_vectors;
 
-#if defined(CONFIG_USER_ONLY)
-    env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp.  */
-#endif
-
     mcc->parent_realize(dev, errp);
 }

Signature · 1 line

1.7.1