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arm64: perf: heterogeneous PMU support

PATCH Superseded Mark Rutland 4 participants 12 messages Jun 11, 2015 – Jun 17, 2015

Subsystems (8)
Device tree bindings Arm (32-bit) Arm sub-architectures perf events +4 more subsystems

v2 of 4 Superseded Latest is v4 →

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Mark Rutland

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#0 lore raw

v2 cover arm64: perf: heterogeneous PMU support

This patch series reworks the 32-bit ARM perf code into a library, and migrates the arm64 perf code over to it, gaining support for heterogeneous PMUs. Support is then added for Cortex-A53 and Cortex-A57 as used in Juno systems.

Previously the librification [1] and arm64 migration [2] were separate series, but as the bulk of the librification has now been queued [3] and the remianing work is mostly tirivial.

The first six patches apply atop of Will's perf/updates branch [3]. The final patch must be applied atop of Liviu's for-upstream/juno-dts branch due to some recent rework of the Juno dts files.

With this series applied, perf can be used to monitor 64-bit systems with heterogeneous PMUs in an identical fashion to 32-bit systems, e.g.

$ perf stat -e armv8_cortex_a53/config=0x11/ -e armv8_cortex_a57/config=0x11/ ./a.out

Performance counter stats for './a.out':

         185250238 armv8_cortex_a53/config=0x11/                                    [55.34%]
         225006550 armv8_cortex_a57/config=0x11/                                    [43.96%]

       0.213953840 seconds time elapsed
$ perf stat -e cycles ./a.out

Performance counter stats for './a.out':

         830917902 cycles                    [64.60%]

       1.023141420 seconds time elapsed

Thanks,
Mark.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-May/346538.html
[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-May/346555.html
[3] https://git.kernel.org/cgit/linux/kernel/git/will/linux.git/log/?h=perf/updates
[4] http://linux-arm.org/git?p=linux-ld.git;a=shortlog;h=refs/heads/for-upstream/juno-dts

Mark Rutland (7):
arm: perf: factor arm_pmu core out to drivers
arm64: perf: factor out callchain code
arm64: perf: move to shared arm_pmu framework
arm64: perf: condense event number maps
arm64: perf: add Cortex-A53 support
arm64: perf: add Cortex-A57 support
arm64: dts: juno: describe PMUs separately

 Documentation/devicetree/bindings/arm/pmu.txt      |    2 +
 MAINTAINERS                                        |    6 +-
 arch/arm/Kconfig                                   |    8 +-
 arch/arm/kernel/Makefile                           |    3 +-
 arch/arm/kernel/perf_event_v6.c                    |    2 +-
 arch/arm/kernel/perf_event_v7.c                    |    2 +-
 arch/arm/kernel/perf_event_xscale.c                |    2 +-
 arch/arm/mach-ux500/cpu-db8500.c                   |    2 +-
 arch/arm64/Kconfig                                 |    8 +-
 arch/arm64/boot/dts/arm/juno-r1.dts                |   18 +-
 arch/arm64/boot/dts/arm/juno.dts                   |   18 +-
 arch/arm64/include/asm/perf_event.h                |    2 +-
 arch/arm64/include/asm/pmu.h                       |   83 -
 arch/arm64/kernel/Makefile                         |    4 +-
 arch/arm64/kernel/perf_callchain.c                 |  196 +++
 arch/arm64/kernel/perf_event.c                     | 1587 --------------------
 arch/arm64/kernel/perf_event_pmuv3.c               |  684 +++++++++
 drivers/Kconfig                                    |    2 +
 drivers/Makefile                                   |    1 +
 drivers/perf/Kconfig                               |   14 +
 drivers/perf/Makefile                              |    1 +
 .../kernel/perf_event.c => drivers/perf/arm_pmu.c  |    2 +-
 .../asm/pmu.h => include/linux/perf/arm_pmu.h      |    4 +-
 23 files changed, 941 insertions(+), 1710 deletions(-)
 delete mode 100644 arch/arm64/include/asm/pmu.h
 create mode 100644 arch/arm64/kernel/perf_callchain.c
 delete mode 100644 arch/arm64/kernel/perf_event.c
 create mode 100644 arch/arm64/kernel/perf_event_pmuv3.c
 create mode 100644 drivers/perf/Kconfig
 create mode 100644 drivers/perf/Makefile
 rename arch/arm/kernel/perf_event.c => drivers/perf/arm_pmu.c (99%)
 rename arch/arm/include/asm/pmu.h => include/linux/perf/arm_pmu.h (98%)
Signature · 1 line
1.9.1
author maintainer
#1 lore raw

PATCH v2 1/7 arm: perf: factor arm_pmu core out to drivers

To enable sharing of the arm_pmu code with arm64, this patch factors it out to drivers/perf/. A new drivers/perf directory is added for performance monitor drivers to live under.

MAINTAINERS is updated accordingly, with myself added as a reviewer as suggested by Will Deacon. The wildcard for arch/arm is updated to cover perf_regs.c and perf_callchain.c, which were added previously without a corresponding MAINTAINERS update.

Signed-off-by Mark Rutland <[email protected]>
Cc Arnaldo Carvalho de Melo <[email protected]>
Cc Greg Kroah-Hartman <[email protected]>
Cc Ingo Molnar <[email protected]>
Cc Linus Walleij <[email protected]>
Cc Paul Mackerras <[email protected]>
Cc Peter Zijlstra <[email protected]>
Cc Russell King <[email protected]>
Cc Will Deacon <[email protected]>
---
 MAINTAINERS                                                |  6 ++++--
 arch/arm/Kconfig                                           |  8 ++------
 arch/arm/kernel/Makefile                                   |  3 +--
 arch/arm/kernel/perf_event_v6.c                            |  2 +-
 arch/arm/kernel/perf_event_v7.c                            |  2 +-
 arch/arm/kernel/perf_event_xscale.c                        |  2 +-
 arch/arm/mach-ux500/cpu-db8500.c                           |  2 +-
 drivers/Kconfig                                            |  2 ++
 drivers/Makefile                                           |  1 +
 drivers/perf/Kconfig                                       | 14 ++++++++++++++
 drivers/perf/Makefile                                      |  1 +
 arch/arm/kernel/perf_event.c => drivers/perf/arm_pmu.c     |  2 +-
 arch/arm/include/asm/pmu.h => include/linux/perf/arm_pmu.h |  4 ++--
 13 files changed, 32 insertions(+), 17 deletions(-)
 create mode 100644 drivers/perf/Kconfig
 create mode 100644 drivers/perf/Makefile
 rename arch/arm/kernel/perf_event.c => drivers/perf/arm_pmu.c (99%)
 rename arch/arm/include/asm/pmu.h => include/linux/perf/arm_pmu.h (98%)
MAINTAINERS +4 -2
index 2e5bbc0..d6dca2c 100644
@@ -798,12 +798,14 @@ F:	arch/arm/include/asm/floppy.h
 
 ARM PMU PROFILING AND DEBUGGING
 M:	Will Deacon <[email protected]>
+R:	Mark Rutland <[email protected]>
 S:	Maintained
-F:	arch/arm/kernel/perf_event*
+F:	arch/arm/kernel/perf_*
 F:	arch/arm/oprofile/common.c
-F:	arch/arm/include/asm/pmu.h
 F:	arch/arm/kernel/hw_breakpoint.c
 F:	arch/arm/include/asm/hw_breakpoint.h
+F:	drivers/perf/arm_pmu.c
+F:	include/linux/perf/arm_pmu.h
 
 ARM PORT
 M:	Russell King <[email protected]>
arch/arm/Kconfig +2 -6
index 45df48b..74864d9 100644
@@ -1663,12 +1663,8 @@ config HIGHPTE
 	depends on HIGHMEM
 
 config HW_PERF_EVENTS
-	bool "Enable hardware performance counter support for perf events"
-	depends on PERF_EVENTS
-	default y
-	help
-	  Enable hardware performance counter support for perf events. If
-	  disabled, perf events will use software events only.
+	def_bool y
+	depends on ARM_PMU
 
 config SYS_SUPPORTS_HUGETLBFS
        def_bool y
arch/arm/kernel/Makefile +1 -2
index d274a1f..f4db513 100644
@@ -70,8 +70,7 @@ obj-$(CONFIG_CPU_PJ4)		+= pj4-cp0.o
 obj-$(CONFIG_CPU_PJ4B)		+= pj4-cp0.o
 obj-$(CONFIG_IWMMXT)		+= iwmmxt.o
 obj-$(CONFIG_PERF_EVENTS)	+= perf_regs.o perf_callchain.o
-obj-$(CONFIG_HW_PERF_EVENTS)	+= perf_event.o \
-				   perf_event_xscale.o perf_event_v6.o \
+obj-$(CONFIG_HW_PERF_EVENTS)	+= perf_event_xscale.o perf_event_v6.o \
 				   perf_event_v7.o
 CFLAGS_pj4-cp0.o		:= -marm
 AFLAGS_iwmmxt.o			:= -Wa,-mcpu=iwmmxt
arch/arm/kernel/perf_event_v6.c +1 -1
index 09f83e4..09413e7 100644
@@ -34,9 +34,9 @@
 
 #include <asm/cputype.h>
 #include <asm/irq_regs.h>
-#include <asm/pmu.h>
 
 #include <linux/of.h>
+#include <linux/perf/arm_pmu.h>
 #include <linux/platform_device.h>
 
 enum armv6_perf_types {
arch/arm/kernel/perf_event_v7.c +1 -1
index f9b37f8..126dc67 100644
@@ -21,11 +21,11 @@
 #include <asm/cp15.h>
 #include <asm/cputype.h>
 #include <asm/irq_regs.h>
-#include <asm/pmu.h>
 #include <asm/vfp.h>
 #include "../vfp/vfpinstr.h"
 
 #include <linux/of.h>
+#include <linux/perf/arm_pmu.h>
 #include <linux/platform_device.h>
 
 /*
arch/arm/kernel/perf_event_xscale.c +1 -1
index 304d056..aa0499e 100644
@@ -16,9 +16,9 @@
 
 #include <asm/cputype.h>
 #include <asm/irq_regs.h>
-#include <asm/pmu.h>
 
 #include <linux/of.h>
+#include <linux/perf/arm_pmu.h>
 #include <linux/platform_device.h>
 
 enum xscale_perf_types {
arch/arm/mach-ux500/cpu-db8500.c +1 -1
index 6f63954..281d4cd 100644
@@ -20,10 +20,10 @@
 #include <linux/mfd/dbx500-prcmu.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
+#include <linux/perf/arm_pmu.h>
 #include <linux/regulator/machine.h>
 #include <linux/random.h>
 
-#include <asm/pmu.h>
 #include <asm/mach/map.h>
 
 #include "setup.h"
drivers/Kconfig +2 -0
index c0cc96b..feffb33 100644
@@ -176,6 +176,8 @@ source "drivers/powercap/Kconfig"
 
 source "drivers/mcb/Kconfig"
 
+source "drivers/perf/Kconfig"
+
 source "drivers/ras/Kconfig"
 
 source "drivers/thunderbolt/Kconfig"
drivers/Makefile +1 -0
index 46d2554..fbdfe07 100644
@@ -161,6 +161,7 @@ obj-$(CONFIG_NTB)		+= ntb/
 obj-$(CONFIG_FMC)		+= fmc/
 obj-$(CONFIG_POWERCAP)		+= powercap/
 obj-$(CONFIG_MCB)		+= mcb/
+obj-$(CONFIG_PERF_EVENTS)	+= perf/
 obj-$(CONFIG_RAS)		+= ras/
 obj-$(CONFIG_THUNDERBOLT)	+= thunderbolt/
 obj-$(CONFIG_CORESIGHT)		+= hwtracing/coresight/
drivers/perf/Kconfig new file +14 -0
new file mode 100644
index 0000000..f556b92ae
@@ -0,0 +1,14 @@
+#
+# Performance Monitor Drivers
+#
+
+menu "Performance monitor support"
+
+config ARM_PMU
+	depends on PERF_EVENTS && ARM
+	bool "ARM PMU framework"
+	default y
+	help
+	  Say y if you want to use performance monitors on ARM systems.
+
+endmenu
drivers/perf/Makefile new file +1 -0
new file mode 100644
index 0000000..acd2397
@@ -0,0 +1 @@
+obj-$(CONFIG_ARM_PMU) += arm_pmu.o
drivers/perf/arm_pmu.c renamed from arch/arm/kernel/perf_event.c +1 -1
similarity index 99%
rename from arch/arm/kernel/perf_event.c
rename to drivers/perf/arm_pmu.c
index 357f57e..daf0a0d 100644
@@ -16,6 +16,7 @@
 #include <linux/export.h>
 #include <linux/kernel.h>
 #include <linux/of.h>
+#include <linux/perf/arm_pmu.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>

@@ -24,7 +25,6 @@
 
 #include <asm/cputype.h>
 #include <asm/irq_regs.h>
-#include <asm/pmu.h>
 
 static int
 armpmu_map_cache_event(const unsigned (*cache_map)
include/linux/perf/arm_pmu.h renamed from arch/arm/include/asm/pmu.h +2 -2
similarity index 98%
rename from arch/arm/include/asm/pmu.h
rename to include/linux/perf/arm_pmu.h
index 3fc87df..bfa673b 100644
@@ -30,7 +30,7 @@ struct arm_pmu_platdata {
 				  irq_handler_t pmu_handler);
 };
 
-#ifdef CONFIG_HW_PERF_EVENTS
+#ifdef CONFIG_ARM_PMU
 
 /*
  * The ARMv7 CPU PMU supports up to 32 event counters.

@@ -149,6 +149,6 @@ int arm_pmu_device_probe(struct platform_device *pdev,
 			 const struct of_device_id *of_table,
 			 const struct pmu_probe_info *probe_table);
 
-#endif /* CONFIG_HW_PERF_EVENTS */
+#endif /* CONFIG_ARM_PMU */
 
 #endif /* __ARM_PMU_H__ */
Signature · 1 line
1.9.1
#2 lore raw

PATCH v2 1/7 arm: perf: factor arm_pmu core out to drivers

Hi Mark,

Quoted 18 lines · Mark Rutland

To enable sharing of the arm_pmu code with arm64, this patch factors it out to drivers/perf/. A new drivers/perf directory is added for performance monitor drivers to live under.

MAINTAINERS is updated accordingly, with myself added as a reviewer as suggested by Will Deacon. The wildcard for arch/arm is updated to cover perf_regs.c and perf_callchain.c, which were added previously without a corresponding MAINTAINERS update.

Signed-off-by Mark Rutland <[email protected]>
Cc Arnaldo Carvalho de Melo <[email protected]>
Cc Greg Kroah-Hartman <[email protected]>
Cc Ingo Molnar <[email protected]>
Cc Linus Walleij <[email protected]>
Cc Paul Mackerras <[email protected]>
Cc Peter Zijlstra <[email protected]>
Cc Russell King <[email protected]>
Cc Will Deacon <[email protected]>
Quoted 2 lines
---
 MAINTAINERS                                                |  6 ++++--

Can you put the MAINTAINERS changes in a separate patch, please?

Quoted 4 lines
 arch/arm/Kconfig                                           |  8 ++------
 arch/arm/kernel/Makefile                                   |  3 +--
 arch/arm/kernel/perf_event_v6.c                            |  2 +-
 arch/arm/kernel/perf_event_v7.c                            |  2 +-
Quoted 8 lines
 arch/arm/kernel/perf_event_xscale.c                        |  2 +-
 arch/arm/mach-ux500/cpu-db8500.c                           |  2 +-
 drivers/Kconfig                                            |  2 ++
 drivers/Makefile                                           |  1 +
 drivers/perf/Kconfig                                       | 14 ++++++++++++++
 drivers/perf/Makefile                                      |  1 +
 arch/arm/kernel/perf_event.c => drivers/perf/arm_pmu.c     |  2 +-
 arch/arm/include/asm/pmu.h => include/linux/perf/arm_pmu.h |  4 ++--

I wonder whether that's such a good name for the subsystem. We already have a bunch of perf_* headers directly under include/linux/ for the perf core interfaces, so maybe drivers/pmu/ would be better?

Will

#3 lore raw

PATCH v2 1/7 arm: perf: factor arm_pmu core out to drivers

Quoted 3 lines · Will Deacon

I wonder whether that's such a good name for the subsystem. We already have a bunch of perf_* headers directly under include/linux/ for the perf core interfaces, so maybe drivers/pmu/ would be better?

I think drivers/perf/ is better than drivers/pmu/. PMU can mean many things - performance monitor unit, power management unit, ...

There comes a point where the use of TLAs becomes excessive, confusing and annoying, and I think this is it.

Signature · 2 lines
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#4 lore raw

PATCH v2 1/7 arm: perf: factor arm_pmu core out to drivers

Quoted 10 lines · Russell King - ARM Linux
Quoted 3 lines · Will Deacon

I wonder whether that's such a good name for the subsystem. We already have a bunch of perf_* headers directly under include/linux/ for the perf core interfaces, so maybe drivers/pmu/ would be better?

I think drivers/perf/ is better than drivers/pmu/. PMU can mean many things - performance monitor unit, power management unit, ...

There comes a point where the use of TLAs becomes excessive, confusing and annoying, and I think this is it.

Okey doke, if the perf core guys don't mind the slightly odd namespace split of <include/linux/perf_*.h> for the core stuff and <include/linux/perf/*.h> for the PMU drivers, then we can stick with Mark's proposal.

Will

author maintainer
#5 lore raw

PATCH v2 2/7 arm64: perf: factor out callchain code

In reply to Mark Rutland

We currently bundle the callchain handling code with the PMU code, despite the fact the two are distinct, and the former can be useful even in the absence of the latter.

Follow the example of arch/arm and factor the callchain handling into its own file dependent on CONFIG_PERF_EVENTS rather than CONFIG_HW_PERF_EVENTS.

Signed-off-by Mark Rutland <[email protected]>
Cc Will Deacon <[email protected]>
---
 arch/arm64/include/asm/perf_event.h |   2 +-
 arch/arm64/kernel/Makefile          |   2 +-
 arch/arm64/kernel/perf_callchain.c  | 196 ++++++++++++++++++++++++++++++++++++
 arch/arm64/kernel/perf_event.c      | 178 --------------------------------
 4 files changed, 198 insertions(+), 180 deletions(-)
 create mode 100644 arch/arm64/kernel/perf_callchain.c
arch/arm64/include/asm/perf_event.h +1 -1
index d26d1d5..dc4cf4e 100644
@@ -17,7 +17,7 @@
 #ifndef __ASM_PERF_EVENT_H
 #define __ASM_PERF_EVENT_H
 
-#ifdef CONFIG_HW_PERF_EVENTS
+#ifdef CONFIG_PERF_EVENTS
 struct pt_regs;
 extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
 extern unsigned long perf_misc_flags(struct pt_regs *regs);
arch/arm64/kernel/Makefile +1 -1
index 426d076..e89063e 100644
@@ -25,7 +25,7 @@ arm64-obj-$(CONFIG_COMPAT)		+= sys32.o kuser32.o signal32.o 	\
 arm64-obj-$(CONFIG_FUNCTION_TRACER)	+= ftrace.o entry-ftrace.o
 arm64-obj-$(CONFIG_MODULES)		+= arm64ksyms.o module.o
 arm64-obj-$(CONFIG_SMP)			+= smp.o smp_spin_table.o topology.o
-arm64-obj-$(CONFIG_PERF_EVENTS)		+= perf_regs.o
+arm64-obj-$(CONFIG_PERF_EVENTS)		+= perf_regs.o perf_callchain.o
 arm64-obj-$(CONFIG_HW_PERF_EVENTS)	+= perf_event.o
 arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)	+= hw_breakpoint.o
 arm64-obj-$(CONFIG_CPU_PM)		+= sleep.o suspend.o
arch/arm64/kernel/perf_callchain.c new file +196 -0

196 lines not on this page · raw message

arch/arm64/kernel/perf_event.c +0 -178

187 lines not on this page · raw message

Signature · 1 line
1.9.1
author maintainer
#6 lore raw

PATCH v2 3/7 arm64: perf: move to shared arm_pmu framework

In reply to Mark Rutland

Now that the arm_pmu framework has been factored out to drivers/perf we can make use of it for arm64, gaining support for heterogeneous PMUs and unifying the two codebases before they diverge further.

The as yet unused PMU name for PMUv3 is changed to armv8_pmuv3, matching the style previously applied to the 32-bit PMUs.

Signed-off-by Mark Rutland <[email protected]>
Cc will Deacon <[email protected]>
---
 arch/arm64/Kconfig                   |    8 +-
 arch/arm64/include/asm/pmu.h         |   83 --
 arch/arm64/kernel/Makefile           |    2 +-
 arch/arm64/kernel/perf_event.c       | 1409 ----------------------------------
 arch/arm64/kernel/perf_event_pmuv3.c |  653 ++++++++++++++++
 drivers/perf/Kconfig                 |    2 +-
 6 files changed, 657 insertions(+), 1500 deletions(-)
 delete mode 100644 arch/arm64/include/asm/pmu.h
 delete mode 100644 arch/arm64/kernel/perf_event.c
 create mode 100644 arch/arm64/kernel/perf_event_pmuv3.c
arch/arm64/Kconfig +2 -6
index 4269dba..cc06bff 100644
@@ -535,12 +535,8 @@ config HAVE_ARCH_PFN_VALID
 	def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
 
 config HW_PERF_EVENTS
-	bool "Enable hardware performance counter support for perf events"
-	depends on PERF_EVENTS
-	default y
-	help
-	  Enable hardware performance counter support for perf events. If
-	  disabled, perf events will use software events only.
+	def_bool y
+	depends on ARM_PMU
 
 config SYS_SUPPORTS_HUGETLBFS
 	def_bool y
arch/arm64/include/asm/pmu.h deleted +0 -83

83 lines not on this page · raw message

arch/arm64/kernel/Makefile +1 -1
index e89063e..8a94901 100644
@@ -26,7 +26,7 @@ arm64-obj-$(CONFIG_FUNCTION_TRACER)	+= ftrace.o entry-ftrace.o
 arm64-obj-$(CONFIG_MODULES)		+= arm64ksyms.o module.o
 arm64-obj-$(CONFIG_SMP)			+= smp.o smp_spin_table.o topology.o
 arm64-obj-$(CONFIG_PERF_EVENTS)		+= perf_regs.o perf_callchain.o
-arm64-obj-$(CONFIG_HW_PERF_EVENTS)	+= perf_event.o
+arm64-obj-$(CONFIG_HW_PERF_EVENTS)	+= perf_event_pmuv3.o
 arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)	+= hw_breakpoint.o
 arm64-obj-$(CONFIG_CPU_PM)		+= sleep.o suspend.o
 arm64-obj-$(CONFIG_CPU_IDLE)		+= cpuidle.o
arch/arm64/kernel/perf_event.c deleted +0 -1409

1,409 lines not on this page · raw message

arch/arm64/kernel/perf_event_pmuv3.c new file +653 -0

653 lines not on this page · raw message

drivers/perf/Kconfig +1 -1
index f556b92ae..5cac510 100644
@@ -5,7 +5,7 @@
 menu "Performance monitor support"
 
 config ARM_PMU
-	depends on PERF_EVENTS && ARM
+	depends on PERF_EVENTS && (ARM || ARM64)
 	bool "ARM PMU framework"
 	default y
 	help
Signature · 1 line
1.9.1
author maintainer
#7 lore raw

PATCH v2 4/7 arm64: perf: condense event number maps

In reply to Mark Rutland

Most of the cache events an architecture might support do not map well to those provided by the ARM architecture, and as such most entries in the event number maps are *_UNSUPPORTED. Unfortuantely as 0 is a valid physical event identifier, the *_UNSUPPORTED macros expand to a non-zero value and thus each unsupported event must be explicitly intiailised as such. This leads to large diffs when adding support for a new CPU, and makes it difficult to spot the important information.

This patch makes use of the new PERF_*_ALL_UNSUPORTED macros to intiailise all entries to *_UNSUPPORTED before overriding this for the specific events we actually support, resulting in a significant source code reduction.

Signed-off-by Mark Rutland <[email protected]>
Cc Will Deacon <[email protected]>
---
 arch/arm64/kernel/perf_event_pmuv3.c | 114 ++++-------------------------------
 1 file changed, 12 insertions(+), 102 deletions(-)
arch/arm64/kernel/perf_event_pmuv3.c +12 -102
index 1f3bbf6..1cc7206 100644
@@ -71,118 +71,28 @@ enum armv8_pmuv3_perf_types {
 
 /* PMUv3 HW events mapping. */
 static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
+	PERF_MAP_ALL_UNSUPPORTED,
 	[PERF_COUNT_HW_CPU_CYCLES]		= ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES,
 	[PERF_COUNT_HW_INSTRUCTIONS]		= ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED,
 	[PERF_COUNT_HW_CACHE_REFERENCES]	= ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
 	[PERF_COUNT_HW_CACHE_MISSES]		= ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
-	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= HW_OP_UNSUPPORTED,
 	[PERF_COUNT_HW_BRANCH_MISSES]		= ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
-	[PERF_COUNT_HW_BUS_CYCLES]		= HW_OP_UNSUPPORTED,
-	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= HW_OP_UNSUPPORTED,
-	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND]	= HW_OP_UNSUPPORTED,
 };
 
 static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 						[PERF_COUNT_HW_CACHE_OP_MAX]
 						[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
-	[C(L1D)] = {
-		[C(OP_READ)] = {
-			[C(RESULT_ACCESS)]	= ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
-			[C(RESULT_MISS)]	= ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
-		},
-		[C(OP_WRITE)] = {
-			[C(RESULT_ACCESS)]	= ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
-			[C(RESULT_MISS)]	= ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
-		},
-		[C(OP_PREFETCH)] = {
-			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
-		},
-	},
-	[C(L1I)] = {
-		[C(OP_READ)] = {
-			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
-		},
-		[C(OP_WRITE)] = {
-			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
-		},
-		[C(OP_PREFETCH)] = {
-			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
-		},
-	},
-	[C(LL)] = {
-		[C(OP_READ)] = {
-			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
-		},
-		[C(OP_WRITE)] = {
-			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
-		},
-		[C(OP_PREFETCH)] = {
-			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
-		},
-	},
-	[C(DTLB)] = {
-		[C(OP_READ)] = {
-			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
-		},
-		[C(OP_WRITE)] = {
-			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
-		},
-		[C(OP_PREFETCH)] = {
-			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
-		},
-	},
-	[C(ITLB)] = {
-		[C(OP_READ)] = {
-			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
-		},
-		[C(OP_WRITE)] = {
-			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
-		},
-		[C(OP_PREFETCH)] = {
-			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
-		},
-	},
-	[C(BPU)] = {
-		[C(OP_READ)] = {
-			[C(RESULT_ACCESS)]	= ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
-			[C(RESULT_MISS)]	= ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
-		},
-		[C(OP_WRITE)] = {
-			[C(RESULT_ACCESS)]	= ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
-			[C(RESULT_MISS)]	= ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
-		},
-		[C(OP_PREFETCH)] = {
-			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
-		},
-	},
-	[C(NODE)] = {
-		[C(OP_READ)] = {
-			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
-		},
-		[C(OP_WRITE)] = {
-			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
-		},
-		[C(OP_PREFETCH)] = {
-			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
-			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
-		},
-	},
+	PERF_CACHE_MAP_ALL_UNSUPPORTED,
+
+	[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]	= ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
+	[C(L1D)][C(OP_READ)][C(RESULT_MISS)]	= ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
+	[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)]	= ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
+	[C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]	= ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
+
+	[C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]	= ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
+	[C(BPU)][C(OP_READ)][C(RESULT_MISS)]	= ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
+	[C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)]	= ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
+	[C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]	= ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
 };
 
 /*
Signature · 1 line
1.9.1
author maintainer
#8 lore raw

PATCH v2 5/7 arm64: perf: add Cortex-A53 support

In reply to Mark Rutland

The Cortex-A53 PMU supports a few events outside of the required PMUv3 set that are rather useful.

This patch adds the event map data for said events.

Signed-off-by Mark Rutland <[email protected]>
Cc Will Deacon <[email protected]>
---
 Documentation/devicetree/bindings/arm/pmu.txt |  1 +
 arch/arm64/kernel/perf_event_pmuv3.c          | 64 ++++++++++++++++++++++++++-
 2 files changed, 63 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/arm/pmu.txt +1 -0
index 3b5f5d1..a65e5cf 100644
@@ -8,6 +8,7 @@ Required properties:
 
 - compatible : should be one of
 	"arm,armv8-pmuv3"
+	"arm.cortex-a53-pmu"
 	"arm,cortex-a17-pmu"
 	"arm,cortex-a15-pmu"
 	"arm,cortex-a12-pmu"
arch/arm64/kernel/perf_event_pmuv3.c +62 -2

107 lines not on this page · raw message

Signature · 1 line
1.9.1
author maintainer
#9 lore raw

PATCH v2 6/7 arm64: perf: add Cortex-A57 support

In reply to Mark Rutland

The Cortex-A57 PMU supports a few events outside of the required PMUv3 set that are rather useful.

This patch adds the event map data for said events.

Signed-off-by Mark Rutland <[email protected]>
Cc Will Deacon <[email protected]>
---
 Documentation/devicetree/bindings/arm/pmu.txt |  1 +
 arch/arm64/kernel/perf_event_pmuv3.c          | 61 +++++++++++++++++++++++++++
 2 files changed, 62 insertions(+)
Documentation/devicetree/bindings/arm/pmu.txt +1 -0
index a65e5cf..9a06761 100644
@@ -8,6 +8,7 @@ Required properties:
 
 - compatible : should be one of
 	"arm,armv8-pmuv3"
+	"arm.cortex-a57-pmu"
 	"arm.cortex-a53-pmu"
 	"arm,cortex-a17-pmu"
 	"arm,cortex-a15-pmu"
arch/arm64/kernel/perf_event_pmuv3.c +61 -0

94 lines not on this page · raw message

Signature · 1 line
1.9.1
author maintainer
#10 lore raw

PATCH v2 7/7 arm64: dts: juno: describe PMUs separately

In reply to Mark Rutland

The A57 and A53 PMUs in support different events, so describe them separately in the Juno dts files.

Signed-off-by Mark Rutland <[email protected]>
Cc Liviu Dudau <[email protected]>
Cc Will Deacon <[email protected]>
---
 arch/arm64/boot/dts/arm/juno-r1.dts | 18 +++++++++++-------
 arch/arm64/boot/dts/arm/juno.dts    | 18 +++++++++++-------
 2 files changed, 22 insertions(+), 14 deletions(-)
arch/arm64/boot/dts/arm/juno-r1.dts +11 -7
index c627511..734e127 100644
@@ -91,17 +91,21 @@
 		};
 	};
 
-	pmu {
-		compatible = "arm,armv8-pmuv3";
+	pmu_a57 {
+		compatible = "arm,cortex-a57-pmu";
 		interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&A57_0>,
+				     <&A57_1>;
+	};
+
+	pmu_a53 {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&A57_0>,
-				     <&A57_1>,
-				     <&A53_0>,
+		interrupt-affinity = <&A53_0>,
 				     <&A53_1>,
 				     <&A53_2>,
 				     <&A53_3>;
arch/arm64/boot/dts/arm/juno.dts +11 -7
index d7cbdd4..ffa05ae 100644
@@ -91,17 +91,21 @@
 		};
 	};
 
-	pmu {
-		compatible = "arm,armv8-pmuv3";
+	pmu_a57 {
+		compatible = "arm,cortex-a57-pmu";
 		interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&A57_0>,
+				     <&A57_1>;
+	};
+
+	pmu_a53 {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&A57_0>,
-				     <&A57_1>,
-				     <&A53_0>,
+		interrupt-affinity = <&A53_0>,
 				     <&A53_1>,
 				     <&A53_2>,
 				     <&A53_3>;
Signature · 1 line
1.9.1
maintainer
#11 lore raw

PATCH v2 7/7 arm64: dts: juno: describe PMUs separately

Quoted 6 lines · Mark Rutland

The A57 and A53 PMUs in support different events, so describe them separately in the Juno dts files.

Signed-off-by Mark Rutland <[email protected]>
Cc Liviu Dudau <[email protected]>
Cc Will Deacon <[email protected]>
Acked-by Liviu Dudau <[email protected]>

Thanks,
Liviu

Quoted 74 lines
---
 arch/arm64/boot/dts/arm/juno-r1.dts | 18 +++++++++++-------
 arch/arm64/boot/dts/arm/juno.dts    | 18 +++++++++++-------
 2 files changed, 22 insertions(+), 14 deletions(-)
arch/arm64/boot/dts/arm/juno-r1.dts +11 -7
index c627511..734e127 100644
@@ -91,17 +91,21 @@
 		};
 	};
 
-	pmu {
-		compatible = "arm,armv8-pmuv3";
+	pmu_a57 {
+		compatible = "arm,cortex-a57-pmu";
 		interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&A57_0>,
+				     <&A57_1>;
+	};
+
+	pmu_a53 {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&A57_0>,
-				     <&A57_1>,
-				     <&A53_0>,
+		interrupt-affinity = <&A53_0>,
 				     <&A53_1>,
 				     <&A53_2>,
 				     <&A53_3>;
arch/arm64/boot/dts/arm/juno.dts +11 -7
index d7cbdd4..ffa05ae 100644
@@ -91,17 +91,21 @@
 		};
 	};
 
-	pmu {
-		compatible = "arm,armv8-pmuv3";
+	pmu_a57 {
+		compatible = "arm,cortex-a57-pmu";
 		interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&A57_0>,
+				     <&A57_1>;
+	};
+
+	pmu_a53 {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&A57_0>,
-				     <&A57_1>,
-				     <&A53_0>,
+		interrupt-affinity = <&A53_0>,
 				     <&A53_1>,
 				     <&A53_2>,
 				     <&A53_3>;
Signature · 1 line
1.9.1
Signature · 8 lines
====================
| I would like to |
| fix the world,  |
| but they're not |
| giving me the   |
 \ source code!  /
  ---------------
    ?\_(?)_/?