DRA7 Timer12 Support

Add the DT node for Timer12 present on DRA7 family of SoCs. Timer12 is present in PD_WKUPAON power domain, and has the same capabilities as the other timers, except for the fact that it serves as a secure timer on HS devices and is clocked only from the secure 32K clock.

The node is marked disabled for now, and the kernel should refrain from using this secure timer on HS devices.

Signed-off-by Suman Anna <[email protected]>

---
 arch/arm/boot/dts/dra7.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

arch/arm/boot/dts/dra7.dtsi +0 -0

index e289c706d27d..37d632dad576 100644
@@ -762,6 +762,16 @@
 			ti,hwmods = "timer11";

according to Tony we should avoid using status at all for in-SoC devices.

Tony, can you confirm I understood you correctly ?

Quoted 5 lines · Felipe Balbi

according to Tony we should avoid using status at all for in-SoC devices.

Tony, can you confirm I understood you correctly ?

Yes. With status = "disabled" kernel completely ignores the device and struct device is not created at all even with the device being there. In general we're better off trying to probe the device and idle it.

The only time we really want to mark something with status = "disabled" is if some coprocessor firmware is using that device and the kernel should not touch it at all.

Quoted 12 lines · Tony Lindgren

Quoted 5 lines · Felipe Balbi

according to Tony we should avoid using status at all for in-SoC devices.

Tony, can you confirm I understood you correctly ?

Yes. With status = "disabled" kernel completely ignores the device and struct device is not created at all even with the device being there. In general we're better off trying to probe the device and idle it.

Quoted 4 lines

The only time we really want to mark something with status = "disabled" is if some coprocessor firmware is using that device and the kernel should not touch it at all.

Not always, since some of the PM clocking logic depends on the state machine variables within the kernel.

We are also using this to deal with paper-spins (atleast in the DRA7 case) and the DTS include model, wherein certain instances may not be present on all variations of the SoC, and enabled specifically on the instances that matter. Obviously, it could be done the other way too, but as far as what Nishanth mentioned sometime back, we are following the former for DRA7.

In anycase, the status property on the Timer12 node can be removed, it doesn't fall into the above category, and we are fixing it up properly on HS devices in the kernel.

Add the hwmod data for GPTimer 12. GPTimer 12 is present in WKUPAON power domain and is clocked from a secure 32K clock. GPTimer 12 serves as a secure timer on HS devices, but is available for kernel on regular GP devices.

The hwmod link is registered only on GP devices. The hwmod data also reused the existing timer class instead of reintroducing the identical dra7xx_timer_secure_sysc class which was dropped in commit edec17863362 ("ARM: DRA7: hwmod: Fix the hwmod class for GPTimer4").

Signed-off-by Suman Anna <[email protected]>

---
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 36 +++++++++++++++++++++++++++++--
 1 file changed, 34 insertions(+), 2 deletions(-)

arch/arm/mach-omap2/omap_hwmod_7xx_data.c +34 -2

index 562247bced49..37a10f87fbcd 100644
@@ -1929,6 +1929,20 @@ static struct omap_hwmod dra7xx_timer11_hwmod = {
 	},
 };
 
+/* timer12 */
+static struct omap_hwmod dra7xx_timer12_hwmod = {
+	.name		= "timer12",
+	.class		= &dra7xx_timer_hwmod_class,
+	.clkdm_name	= "wkupaon_clkdm",
+	.main_clk	= "secure_32k_clk_src_ck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
+		},
+	},
+};
+
 /* timer13 */
 static struct omap_hwmod dra7xx_timer13_hwmod = {
 	.name		= "timer13",

@@ -3135,6 +3149,14 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_wkup -> timer12 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
+	.master		= &dra7xx_l4_wkup_hwmod,
+	.slave		= &dra7xx_timer12_hwmod,
+	.clk		= "wkupaon_iclk_mux",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* l4_per3 -> timer13 */
 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
 	.master		= &dra7xx_l4_per3_hwmod,

@@ -3429,6 +3451,13 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
 	NULL,
 };
 
+/* GP-only hwmod links */
+static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
+	&dra7xx_l4_wkup__timer12,
+	NULL,
+};
+
+/* SoC variant specific hwmod links */
 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
 	&dra7xx_l4_per3__usb_otg_ss4,
 	NULL,

@@ -3446,9 +3475,12 @@ int __init dra7xx_hwmod_init(void)
 	ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
 
 	if (!ret && soc_is_dra74x())
-		return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
+		ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
 	else if (!ret && soc_is_dra72x())
-		return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
+		ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
+
+	if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP)
+		ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);
 
 	return ret;
 }

Signature · 1 line

2.6.0