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clk: add Dove PLL divider support for GPU, VMeta and AXI clocks

PATCH Superseded Russell King 2 participants 2 messages Nov 26, 2015 – Nov 27, 2015

Subsystems (2)
Common clk Arm/Marvell Kirkwood and Armada 370, 375, 38x, 39x, XP, 3700, 7K/8K, CN9130 SoC support

v1 of 3 Superseded Latest is v3 →

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Russell King

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PATCH 2/3 clk: add Dove PLL divider support for GPU, VMeta and AXI clocks

Add support for the Dove PLL dividers, which are used to generate the clocks for the AXI bus, as well as the GPU and VMeta peripherals.

Signed-off-by Russell King <[email protected]>
---
 drivers/clk/mvebu/Makefile       |   2 +-
 drivers/clk/mvebu/dove-divider.c | 262 +++++++++++++++++++++++++++++++++++++++
 drivers/clk/mvebu/dove.c         |   6 +
 3 files changed, 269 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/mvebu/dove-divider.c
drivers/clk/mvebu/Makefile +1 -1
index 645ac7ea3565..8866115486f7 100644
@@ -7,6 +7,6 @@ obj-$(CONFIG_ARMADA_375_CLK)	+= armada-375.o
 obj-$(CONFIG_ARMADA_38X_CLK)	+= armada-38x.o
 obj-$(CONFIG_ARMADA_39X_CLK)	+= armada-39x.o
 obj-$(CONFIG_ARMADA_XP_CLK)	+= armada-xp.o
-obj-$(CONFIG_DOVE_CLK)		+= dove.o
+obj-$(CONFIG_DOVE_CLK)		+= dove.o dove-divider.o
 obj-$(CONFIG_KIRKWOOD_CLK)	+= kirkwood.o
 obj-$(CONFIG_ORION_CLK)		+= orion.o
drivers/clk/mvebu/dove-divider.c new file +262 -0

262 lines not on this page · raw message

drivers/clk/mvebu/dove.c +6 -0
index b8c2424ac926..59fad9546c84 100644
@@ -17,6 +17,7 @@
 #include <linux/io.h>
 #include <linux/of.h>
 #include "common.h"
+#include "dove-divider.h"
 
 /*
  * Core Clocks

@@ -184,9 +185,14 @@ static void __init dove_clk_init(struct device_node *np)
 {
 	struct device_node *cgnp =
 		of_find_compatible_node(NULL, NULL, "marvell,dove-gating-clock");
+	struct device_node *ddnp =
+		of_find_compatible_node(NULL, NULL, "marvell,dove-divider-clock");
 
 	mvebu_coreclk_setup(np, &dove_coreclks);
 
+	if (ddnp)
+		dove_divider_clk_init(ddnp);
+
 	if (cgnp)
 		mvebu_clk_gating_setup(cgnp, dove_gating_desc);
 }
Signature · 1 line
2.1.0
maintainer
#1 lore raw

PATCH 2/3 clk: add Dove PLL divider support for GPU, VMeta and AXI clocks

Hi Russell

Quoted 8 lines
drivers/clk/mvebu/dove-divider.c new file +8 -0
+static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate,
+			     unsigned long parent_rate, bool set)
+{
+	unsigned int divider, max;
+
+	divider = DIV_ROUND_CLOSEST(parent_rate, rate);
+
+	if (dc->divider_table) {

drivers/clk/mvebu/dove-divider.c line 83

Quoted 10 lines
drivers/clk/mvebu/dove-divider.c new file +10 -0
+		unsigned int i;
+
+		for (i = 0; dc->divider_table[i]; i++)
+			if (divider == dc->divider_table[i]) {
+				divider = i;
+				break;
+			}
+
+		if (dc->divider_table[i])
+			return -EINVAL;

Is this condition correct? If we have reached the 0 at the end of the table, -EINVAL makes sense. But that would need a !

Andrew