Cavium ThunderX PMU support

Add a compatible string for the Cavium ThunderX PMU.

Signed-off-by Jan Glauber <[email protected]>

---
 Documentation/devicetree/bindings/arm/pmu.txt | 1 +
 arch/arm64/boot/dts/cavium/thunder-88xx.dtsi  | 5 +++++
 2 files changed, 6 insertions(+)

Documentation/devicetree/bindings/arm/pmu.txt +1 -0

index 5651883..d3999a1 100644
@@ -25,6 +25,7 @@ Required properties:
 	"qcom,scorpion-pmu"
 	"qcom,scorpion-mp-pmu"
 	"qcom,krait-pmu"
+	"cavium,thunder-pmu"
 - interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
                interrupt (PPI) then 1 interrupt should be specified.
 

arch/arm64/boot/dts/cavium/thunder-88xx.dtsi +5 -0

index 9cb7cf9..2eb9b22 100644
@@ -360,6 +360,11 @@
 		             <1 10 0xff01>;
 	};
 
+	pmu {
+		compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3";
+		interrupts = <1 7 4>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <2>;

Signature · 1 line

1.9.1

Quoted 1 line · Jan Glauber

Add a compatible string for the Cavium ThunderX PMU.

Stupid question, but is "thunder" the name of the CPU or the SoC or ...?

Whatever we use to describe the PMU, should probably also identify the CPU uniquely.

Will

Quoted 35 lines

Signed-off-by Jan Glauber <[email protected]>

---
  Documentation/devicetree/bindings/arm/pmu.txt | 1 +
  arch/arm64/boot/dts/cavium/thunder-88xx.dtsi  | 5 +++++
  2 files changed, 6 insertions(+)

Documentation/devicetree/bindings/arm/pmu.txt +1 -0

index 5651883..d3999a1 100644
@@ -25,6 +25,7 @@ Required properties:
  	"qcom,scorpion-pmu"
  	"qcom,scorpion-mp-pmu"
  	"qcom,krait-pmu"
+	"cavium,thunder-pmu"
  - interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
                 interrupt (PPI) then 1 interrupt should be specified.
 

arch/arm64/boot/dts/cavium/thunder-88xx.dtsi +5 -1

index 9cb7cf9..2eb9b22 100644
@@ -360,6 +360,11 @@
  		             <1 10 0xff01>;
  	};
 
+	pmu {
+		compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3";
+		interrupts = <1 7 4>;
+	};
+
  	soc {
  		compatible = "simple-bus";
  		#address-cells = <2>;
--

Quoted 2 lines

1.9.1

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Quoted 1 line · Jan Glauber

Add a compatible string for the Cavium ThunderX PMU.

Stupid question, but is "thunder" the name of the CPU or the SoC or ...?

Whatever we use to describe the PMU, should probably also identify the CPU uniquely.

Will

Quoted 37 lines

Signed-off-by Jan Glauber <[email protected]>

---
 Documentation/devicetree/bindings/arm/pmu.txt | 1 +
 arch/arm64/boot/dts/cavium/thunder-88xx.dtsi  | 5 +++++
 2 files changed, 6 insertions(+)

Documentation/devicetree/bindings/arm/pmu.txt +1 -0

index 5651883..d3999a1 100644
@@ -25,6 +25,7 @@ Required properties:
 	"qcom,scorpion-pmu"
 	"qcom,scorpion-mp-pmu"
 	"qcom,krait-pmu"
+	"cavium,thunder-pmu"
 - interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
                interrupt (PPI) then 1 interrupt should be specified.
 

arch/arm64/boot/dts/cavium/thunder-88xx.dtsi +5 -0

index 9cb7cf9..2eb9b22 100644
@@ -360,6 +360,11 @@
 		             <1 10 0xff01>;
 	};
 
+	pmu {
+		compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3";
+		interrupts = <1 7 4>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <2>;

Signature · 1 line

1.9.1

With the long cycle counter bit (LC) disabled the cycle counter is not working on ThunderX SOC (ThunderX only implements Aarch64). Also, according to documentation LC == 0 is deprecated.

To keep the code simple the patch does not introduce 64 bit wide counter functions. Instead writing the cycle counter always sets the upper 32 bits so overflow interrupts are generated as before.

Original patch from Andrew Pinksi <[email protected]>

Quoted 8 lines · Jan Glauber

With the long cycle counter bit (LC) disabled the cycle counter is not working on ThunderX SOC (ThunderX only implements Aarch64). Also, according to documentation LC == 0 is deprecated.

To keep the code simple the patch does not introduce 64 bit wide counter functions. Instead writing the cycle counter always sets the upper 32 bits so overflow interrupts are generated as before.

Quoted 1 line

Original patch from Andrew Pinksi <[email protected]>

What does this mean? Do we need Andrew's S-o-B, or is this a fresh patch?

Will

Quoted 4 lines · Jan Glauber

With the long cycle counter bit (LC) disabled the cycle counter is not working on ThunderX SOC (ThunderX only implements Aarch64). Also, according to documentation LC == 0 is deprecated.

Quoted 5 lines

To keep the code simple the patch does not introduce 64 bit wide counter functions. Instead writing the cycle counter always sets the upper 32 bits so overflow interrupts are generated as before.

Original patch from Andrew Pinksi <[email protected]>

What does this mean? Do we need Andrew's S-o-B, or is this a fresh patch?

Will

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Quoted 4 lines · Jan Glauber

With the long cycle counter bit (LC) disabled the cycle counter is not working on ThunderX SOC (ThunderX only implements Aarch64). Also, according to documentation LC == 0 is deprecated.

Quoted 5 lines

To keep the code simple the patch does not introduce 64 bit wide counter functions. Instead writing the cycle counter always sets the upper 32 bits so overflow interrupts are generated as before.

Original patch from Andrew Pinksi <[email protected]>

What does this mean? Do we need Andrew's S-o-B, or is this a fresh patch?

Will

Quoted 9 lines · Will Deacon

Quoted 8 lines · Jan Glauber

With the long cycle counter bit (LC) disabled the cycle counter is not working on ThunderX SOC (ThunderX only implements Aarch64). Also, according to documentation LC == 0 is deprecated.

To keep the code simple the patch does not introduce 64 bit wide counter functions. Instead writing the cycle counter always sets the upper 32 bits so overflow interrupts are generated as before.

Quoted 3 lines

Quoted 1 line

Original patch from Andrew Pinksi <[email protected]>

What does this mean? Do we need Andrew's S-o-B, or is this a fresh patch?

Please let me know if I should repost or not, FWIW I got Andrew's S-o-B on the patch.

With the long cycle counter bit (LC) disabled the cycle counter is not working on ThunderX SOC (ThunderX only implements Aarch64). Also, according to documentation LC == 0 is deprecated.

To keep the code simple the patch does not introduce 64 bit wide counter functions. Instead writing the cycle counter always sets the upper 32 bits so overflow interrupts are generated as before.

Original patch from Andrew Pinksi <[email protected]>

Signed-off-by Jan Glauber <[email protected]>

---
 arch/arm64/kernel/perf_event.c | 21 ++++++++++++++++-----
 1 file changed, 16 insertions(+), 5 deletions(-)

arch/arm64/kernel/perf_event.c +0 -0

index 0ed05f6..c68fa98 100644

Hi Jan,

I've queued this lot on my perf/updates branch, but I just noticed an oddity whilst dealing with some potential conflicts with the kvm tree.

Quoted 15 lines · Jan Glauber

With the long cycle counter bit (LC) disabled the cycle counter is not working on ThunderX SOC (ThunderX only implements Aarch64). Also, according to documentation LC == 0 is deprecated.

To keep the code simple the patch does not introduce 64 bit wide counter functions. Instead writing the cycle counter always sets the upper 32 bits so overflow interrupts are generated as before.

Original patch from Andrew Pinksi <[email protected]>

Signed-off-by Jan Glauber <[email protected]>

---
 arch/arm64/kernel/perf_event.c | 21 ++++++++++++++++-----
 1 file changed, 16 insertions(+), 5 deletions(-)

arch/arm64/kernel/perf_event.c static const struct attribute_group *armv8_pmuv3_attr_groups[] = { · line 411

Quoted 12 lines

arch/arm64/kernel/perf_event.c +1 -0

index 0ed05f6..c68fa98 100644
@@ -405,6 +405,7 @@ static const struct attribute_group *armv8_pmuv3_attr_groups[] = {
 #define ARMV8_PMCR_D		(1 << 3) /* CCNT counts every 64th cpu cycle */
 #define ARMV8_PMCR_X		(1 << 4) /* Export to ETM */
 #define ARMV8_PMCR_DP		(1 << 5) /* Disable CCNT if non-invasive debug*/
+#define ARMV8_PMCR_LC		(1 << 6) /* Overflow on 64 bit cycle counter */
 #define	ARMV8_PMCR_N_SHIFT	11	 /* Number of counters supported */
 #define	ARMV8_PMCR_N_MASK	0x1f
 #define	ARMV8_PMCR_MASK		0x3f	 /* Mask for writable bits */

You haven't extended this mask to cover the LC bit, so it will be ignored by armv8pmu_pmcr_write afaict.

How did you test this? I can easily update the mask, but it would be good to know that it doesn't end up cause a breakage.

Will

Hi Jan,

I've queued this lot on my perf/updates branch, but I just noticed an oddity whilst dealing with some potential conflicts with the kvm tree.

Quoted 20 lines · Jan Glauber

With the long cycle counter bit (LC) disabled the cycle counter is not working on ThunderX SOC (ThunderX only implements Aarch64). Also, according to documentation LC == 0 is deprecated.

To keep the code simple the patch does not introduce 64 bit wide counter functions. Instead writing the cycle counter always sets the upper 32 bits so overflow interrupts are generated as before.

Original patch from Andrew Pinksi <[email protected]>

Signed-off-by Jan Glauber <[email protected]>

---
 arch/arm64/kernel/perf_event.c | 21 ++++++++++++++++-----
 1 file changed, 16 insertions(+), 5 deletions(-)

arch/arm64/kernel/perf_event.c +0 -0

index 0ed05f6..c68fa98 100644

arch/arm64/kernel/perf_event.c static const struct attribute_group *armv8_pmuv3_attr_groups[] = { · line 411

Quoted 7 lines

arch/arm64/kernel/perf_event.c +1 -0

@@ -405,6 +405,7 @@ static const struct attribute_group *armv8_pmuv3_attr_groups[] = {
 #define ARMV8_PMCR_D		(1 << 3) /* CCNT counts every 64th cpu cycle */
 #define ARMV8_PMCR_X		(1 << 4) /* Export to ETM */
 #define ARMV8_PMCR_DP		(1 << 5) /* Disable CCNT if non-invasive debug*/
+#define ARMV8_PMCR_LC		(1 << 6) /* Overflow on 64 bit cycle counter */
 #define	ARMV8_PMCR_N_SHIFT	11	 /* Number of counters supported */
 #define	ARMV8_PMCR_N_MASK	0x1f
 #define	ARMV8_PMCR_MASK		0x3f	 /* Mask for writable bits */

You haven't extended this mask to cover the LC bit, so it will be ignored by armv8pmu_pmcr_write afaict.

How did you test this? I can easily update the mask, but it would be good to know that it doesn't end up cause a breakage.

Will